Lines Matching refs:lane_ctrl_ch_en_reg
527 u32 offset_reg, lane_ctrl_ch_en_reg; in amd_sdw_transport_params() local
537 lane_ctrl_ch_en_reg = in amd_sdw_transport_params()
538 acp63_sdw0_dp_reg[params->port_num].lane_ctrl_ch_en_reg; in amd_sdw_transport_params()
545 lane_ctrl_ch_en_reg = in amd_sdw_transport_params()
546 acp63_sdw1_dp_reg[params->port_num].lane_ctrl_ch_en_reg; in amd_sdw_transport_params()
558 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[params->port_num].lane_ctrl_ch_en_reg; in amd_sdw_transport_params()
586 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_transport_params()
588 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_transport_params()
598 u32 lane_ctrl_ch_en_reg; in amd_sdw_port_enable() local
604 lane_ctrl_ch_en_reg = in amd_sdw_port_enable()
605 acp63_sdw0_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; in amd_sdw_port_enable()
608 lane_ctrl_ch_en_reg = in amd_sdw_port_enable()
609 acp63_sdw1_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; in amd_sdw_port_enable()
617 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; in amd_sdw_port_enable()
627 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_port_enable()
630 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_port_enable()
632 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_port_enable()