484 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)  in tegra_pmc_readl()  function
530 		return tegra_pmc_readl(pmc, offset);  in tegra_pmc_scratch_readl()
552 		return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;  in tegra_powergate_state()
554 		return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;  in tegra_powergate_state()
610 	return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);  in tegra_powergate_toggle_ready()
1141 	value = tegra_pmc_readl(pmc, PMC_CNTRL);  in tegra_pmc_restart()
1581 		value = tegra_pmc_readl(pmc, offset);  in tegra_io_pad_poll()
1701 	value = tegra_pmc_readl(pmc, status);  in tegra_io_pad_is_powered()
1722 		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);  in tegra_io_pad_set_voltage()
1732 		value = tegra_pmc_readl(pmc, PMC_PWR_DET);  in tegra_io_pad_set_voltage()
1737 		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);  in tegra_io_pad_set_voltage()
1767 		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);  in tegra_io_pad_get_voltage()
1769 		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);  in tegra_io_pad_get_voltage()
1821 	value = tegra_pmc_readl(pmc, PMC_CNTRL);  in tegra_pmc_enter_suspend_mode()
1967 	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
1993 	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
2161 	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);  in reset_reason_show()
2178 	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);  in reset_level_show()
2324 	value = tegra_pmc_readl(pmc, offset);  in tegra210_pmc_irq_set_wake()
2350 	value = tegra_pmc_readl(pmc, offset);  in tegra210_pmc_irq_set_type()
2541 	tegra_pmc_readl(pmc, offset);  in pmc_clk_fence_udelay()
2551 	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;  in pmc_clk_mux_get_parent()
2562 	val = tegra_pmc_readl(pmc, clk->offs);  in pmc_clk_mux_set_parent()
2576 	val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);  in pmc_clk_is_enabled()
2585 	val = tegra_pmc_readl(pmc, offs);  in pmc_clk_set_state()
2647 	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;  in pmc_clk_gate_is_enabled()
2811 	*value = tegra_pmc_readl(pmc, offset);  in tegra_pmc_regmap_readl()
3223 	value = tegra_pmc_readl(pmc, PMC_CNTRL);  in tegra20_pmc_init()
3227 	value = tegra_pmc_readl(pmc, PMC_CNTRL);  in tegra20_pmc_init()
3243 	value = tegra_pmc_readl(pmc, PMC_CNTRL);  in tegra20_pmc_init()
3264 	value = tegra_pmc_readl(pmc, PMC_CNTRL);  in tegra20_pmc_setup_irq_polarity()