Lines Matching +full:sdmmc3 +full:- +full:hv
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
59 #include <dt-bindings/gpio/tegra194-gpio.h>
60 #include <dt-bindings/gpio/tegra234-gpio.h>
61 #include <dt-bindings/soc/tegra-pmc.h>
391 * struct tegra_pmc - NVIDIA Tegra PMC
407 * @corereq_high: core power request is active-high
408 * @sysclkreq_high: system clock request is active-high
421 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
422 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
488 if (pmc->tz_only) { in tegra_pmc_readl()
492 if (pmc->dev) in tegra_pmc_readl()
493 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
503 return readl(pmc->base + offset); in tegra_pmc_readl()
511 if (pmc->tz_only) { in tegra_pmc_writel()
515 if (pmc->dev) in tegra_pmc_writel()
516 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
523 writel(value, pmc->base + offset); in tegra_pmc_writel()
529 if (pmc->tz_only) in tegra_pmc_scratch_readl()
532 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
538 if (pmc->tz_only) in tegra_pmc_scratch_writel()
541 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
551 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
559 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
564 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
571 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
572 return -EINVAL; in tegra_powergate_lookup()
574 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
578 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
582 return -ENODEV; in tegra_powergate_lookup()
594 * if there is contention with a HW-initiated toggling (i.e. CPU core in tegra20_powergate_set()
595 * power-gated), the command should be retried in that case. in tegra20_powergate_set()
603 } while (ret == -ETIMEDOUT && retries--); in tegra20_powergate_set()
643 * tegra_powergate_set() - set the state of a partition
653 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
654 return -EINVAL; in tegra_powergate_set()
656 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
659 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
663 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
665 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
675 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
682 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
702 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
713 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_prepare_clocks()
714 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); in tegra_powergate_prepare_clocks()
716 if (!pg->clk_rates[i]) { in tegra_powergate_prepare_clocks()
717 err = -EINVAL; in tegra_powergate_prepare_clocks()
721 if (pg->clk_rates[i] <= safe_rate) in tegra_powergate_prepare_clocks()
730 err = clk_set_rate(pg->clks[i], safe_rate); in tegra_powergate_prepare_clocks()
738 while (i--) in tegra_powergate_prepare_clocks()
739 clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_prepare_clocks()
749 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_unprepare_clocks()
750 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_unprepare_clocks()
762 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
763 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
771 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
772 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
780 while (i--) in tegra_powergate_enable_clocks()
781 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
791 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
797 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
813 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
819 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
825 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
826 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
847 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
866 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
876 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
889 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
904 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
910 pg->genpd.name, err); in tegra_genpd_power_on()
914 reset_control_release(pg->reset); in tegra_genpd_power_on()
923 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
926 err = reset_control_acquire(pg->reset); in tegra_genpd_power_off()
929 pg->genpd.name, err); in tegra_genpd_power_off()
936 pg->genpd.name, err); in tegra_genpd_power_off()
937 reset_control_release(pg->reset); in tegra_genpd_power_off()
944 * tegra_powergate_power_on() - power on partition
950 return -EINVAL; in tegra_powergate_power_on()
957 * tegra_powergate_power_off() - power off partition
963 return -EINVAL; in tegra_powergate_power_off()
970 * tegra_powergate_is_powered() - check if partition is powered
977 return -EINVAL; in tegra_powergate_is_powered()
983 * tegra_powergate_remove_clamping() - remove power clamps for partition
989 return -EINVAL; in tegra_powergate_remove_clamping()
996 * tegra_powergate_sequence_power_up() - power up partition
1010 return -EINVAL; in tegra_powergate_sequence_power_up()
1014 return -ENOMEM; in tegra_powergate_sequence_power_up()
1016 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_sequence_power_up()
1017 if (!pg->clk_rates) { in tegra_powergate_sequence_power_up()
1018 kfree(pg->clks); in tegra_powergate_sequence_power_up()
1019 return -ENOMEM; in tegra_powergate_sequence_power_up()
1022 pg->id = id; in tegra_powergate_sequence_power_up()
1023 pg->clks = &clk; in tegra_powergate_sequence_power_up()
1024 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
1025 pg->reset = rst; in tegra_powergate_sequence_power_up()
1026 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
1030 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
1033 kfree(pg->clk_rates); in tegra_powergate_sequence_power_up()
1041 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1051 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1052 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1054 return -EINVAL; in tegra_get_cpu_powergate_id()
1058 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1073 * tegra_pmc_cpu_power_on() - power on CPU partition
1088 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1106 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1116 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_program_reboot_reason()
1120 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1176 seq_printf(s, "------------------\n"); in powergate_show()
1178 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1183 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1201 return -ENODEV; in tegra_powergate_of_get_clks()
1203 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
1204 if (!pg->clks) in tegra_powergate_of_get_clks()
1205 return -ENOMEM; in tegra_powergate_of_get_clks()
1207 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_of_get_clks()
1208 if (!pg->clk_rates) { in tegra_powergate_of_get_clks()
1209 kfree(pg->clks); in tegra_powergate_of_get_clks()
1210 return -ENOMEM; in tegra_powergate_of_get_clks()
1214 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
1215 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
1216 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
1221 pg->num_clks = count; in tegra_powergate_of_get_clks()
1226 while (i--) in tegra_powergate_of_get_clks()
1227 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
1229 kfree(pg->clk_rates); in tegra_powergate_of_get_clks()
1230 kfree(pg->clks); in tegra_powergate_of_get_clks()
1238 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1241 pg->reset = of_reset_control_array_get_exclusive_released(np); in tegra_powergate_of_get_resets()
1242 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
1243 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
1248 err = reset_control_acquire(pg->reset); in tegra_powergate_of_get_resets()
1255 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
1257 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
1261 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1266 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1267 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
1275 struct device *dev = pmc->dev; in tegra_powergate_add()
1282 return -ENOMEM; in tegra_powergate_add()
1284 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1287 err = -ENODEV; in tegra_powergate_add()
1295 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1297 pg->id = id; in tegra_powergate_add()
1298 pg->genpd.name = np->name; in tegra_powergate_add()
1299 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
1300 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
1301 pg->pmc = pmc; in tegra_powergate_add()
1303 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1324 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
1331 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
1338 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
1343 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
1346 reset_control_put(pg->reset); in tegra_powergate_add()
1349 while (pg->num_clks--) in tegra_powergate_add()
1350 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
1352 kfree(pg->clks); in tegra_powergate_add()
1355 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1365 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1375 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); in tegra_pmc_core_pd_set_performance_state()
1377 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", in tegra_pmc_core_pd_set_performance_state()
1382 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1383 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1384 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1389 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", in tegra_pmc_core_pd_set_performance_state()
1403 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1405 return -ENOMEM; in tegra_pmc_core_pd_add()
1407 genpd->name = "core"; in tegra_pmc_core_pd_add()
1408 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; in tegra_pmc_core_pd_add()
1410 err = devm_pm_opp_set_regulators(pmc->dev, rname); in tegra_pmc_core_pd_add()
1412 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1417 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1423 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1427 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1448 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_init()
1465 if (of_parse_phandle_with_args(child, "power-domains", in tegra_powergate_init()
1466 "#power-domain-cells", in tegra_powergate_init()
1488 reset_control_put(pg->reset); in tegra_powergate_remove()
1490 while (pg->num_clks--) in tegra_powergate_remove()
1491 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_remove()
1493 kfree(pg->clks); in tegra_powergate_remove()
1495 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1521 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_remove_all()
1533 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1534 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1535 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1548 if (pad->dpd == UINT_MAX) in tegra_io_pad_prepare()
1549 return -EINVAL; in tegra_io_pad_prepare()
1551 *request = pad->request; in tegra_io_pad_prepare()
1552 *status = pad->status; in tegra_io_pad_prepare()
1553 *mask = BIT(pad->dpd); in tegra_io_pad_prepare()
1555 if (pmc->clk) { in tegra_io_pad_prepare()
1556 rate = pmc->rate; in tegra_io_pad_prepare()
1558 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1559 return -ENODEV; in tegra_io_pad_prepare()
1588 return -ETIMEDOUT; in tegra_io_pad_poll()
1593 if (pmc->clk) in tegra_io_pad_unprepare()
1598 * tegra_io_pad_power_enable() - enable power to I/O pad
1612 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_enable()
1613 return -ENOENT; in tegra_io_pad_power_enable()
1616 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1620 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1628 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1635 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1641 * tegra_io_pad_power_disable() - disable power to I/O pad
1655 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_disable()
1656 return -ENOENT; in tegra_io_pad_power_disable()
1659 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1663 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1671 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1678 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1691 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_is_powered()
1692 return -ENOENT; in tegra_io_pad_is_powered()
1695 if (pad->dpd == UINT_MAX) in tegra_io_pad_is_powered()
1696 return -EINVAL; in tegra_io_pad_is_powered()
1698 status = pad->status; in tegra_io_pad_is_powered()
1699 mask = BIT(pad->dpd); in tegra_io_pad_is_powered()
1714 return -ENOENT; in tegra_io_pad_set_voltage()
1716 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1717 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1719 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1721 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1725 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1727 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1731 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1733 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1740 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1742 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1747 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1761 return -ENOENT; in tegra_io_pad_get_voltage()
1763 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1764 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1766 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1771 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1780 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1788 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1803 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1813 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1817 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1832 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1833 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1837 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1841 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1845 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1849 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1854 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1856 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1857 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1859 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1861 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1862 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1864 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1866 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1868 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1870 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1871 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1873 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1874 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1876 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1878 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1879 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1881 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1882 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1884 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1885 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1887 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1888 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1890 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1892 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1893 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1895 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1896 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1903 if (pmc->soc->max_wake_events > 0) { in tegra_pmc_init()
1904 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1905 if (!pmc->wake_type_level_map) in tegra_pmc_init()
1906 return -ENOMEM; in tegra_pmc_init()
1908 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1909 if (!pmc->wake_type_dual_edge_map) in tegra_pmc_init()
1910 return -ENOMEM; in tegra_pmc_init()
1912 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1913 if (!pmc->wake_sw_status_map) in tegra_pmc_init()
1914 return -ENOMEM; in tegra_pmc_init()
1916 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1917 if (!pmc->wake_cntrl_level_map) in tegra_pmc_init()
1918 return -ENOMEM; in tegra_pmc_init()
1921 if (pmc->soc->init) in tegra_pmc_init()
1922 pmc->soc->init(pmc); in tegra_pmc_init()
1931 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1935 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1938 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1940 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1944 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1949 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1950 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1954 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1955 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1959 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1960 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1964 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
1987 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1997 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
2007 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
2015 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
2025 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2050 return -EINVAL; in tegra_io_pad_pinconf_get()
2054 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2062 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2070 return -EINVAL; in tegra_io_pad_pinconf_get()
2091 return -EINVAL; in tegra_io_pad_pinconf_set()
2100 err = tegra_io_pad_power_disable(pad->id); in tegra_io_pad_pinconf_set()
2102 err = tegra_io_pad_power_enable(pad->id); in tegra_io_pad_pinconf_set()
2109 return -EINVAL; in tegra_io_pad_pinconf_set()
2110 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2115 return -EINVAL; in tegra_io_pad_pinconf_set()
2137 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2140 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2141 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2142 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2144 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2146 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2147 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2148 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2161 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2162 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2163 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2165 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2168 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2178 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2179 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2180 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2182 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2185 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2192 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2195 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2203 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2217 if (WARN_ON(fwspec->param_count < 2)) in tegra_pmc_irq_translate()
2218 return -EINVAL; in tegra_pmc_irq_translate()
2220 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
2221 *type = fwspec->param[1]; in tegra_pmc_irq_translate()
2229 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc()
2230 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2236 return -EINVAL; in tegra_pmc_irq_alloc()
2238 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
2239 const struct tegra_wake_event *event = &soc->wake_events[i]; in tegra_pmc_irq_alloc()
2242 if (fwspec->param_count == 2) { in tegra_pmc_irq_alloc()
2245 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
2249 event->id, in tegra_pmc_irq_alloc()
2250 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2255 if (event->irq == 0) { in tegra_pmc_irq_alloc()
2256 err = irq_domain_disconnect_hierarchy(domain->parent, virq); in tegra_pmc_irq_alloc()
2260 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2263 spec.param[1] = event->irq; in tegra_pmc_irq_alloc()
2264 spec.param[2] = fwspec->param[1]; in tegra_pmc_irq_alloc()
2273 if (fwspec->param_count == 3) { in tegra_pmc_irq_alloc()
2274 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2275 event->gpio.pin != fwspec->param[1]) in tegra_pmc_irq_alloc()
2279 event->id, in tegra_pmc_irq_alloc()
2280 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2283 if (!err && domain->parent) in tegra_pmc_irq_alloc()
2284 err = irq_domain_disconnect_hierarchy(domain->parent, in tegra_pmc_irq_alloc()
2290 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2291 if (i == soc->num_wake_events) in tegra_pmc_irq_alloc()
2308 offset = data->hwirq / 32; in tegra210_pmc_irq_set_wake()
2309 bit = data->hwirq % 32; in tegra210_pmc_irq_set_wake()
2319 if (data->hwirq >= 32) in tegra210_pmc_irq_set_wake()
2342 offset = data->hwirq / 32; in tegra210_pmc_irq_set_type()
2343 bit = data->hwirq % 32; in tegra210_pmc_irq_set_type()
2345 if (data->hwirq >= 32) in tegra210_pmc_irq_set_type()
2368 return -EINVAL; in tegra210_pmc_irq_set_type()
2381 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2383 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2384 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); in tegra186_pmc_set_wake_filters()
2393 offset = data->hwirq / 32; in tegra186_pmc_irq_set_wake()
2394 bit = data->hwirq % 32; in tegra186_pmc_irq_set_wake()
2397 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2400 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2407 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2410 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2420 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2426 set_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2427 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2433 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2434 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2439 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2440 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2444 return -EINVAL; in tegra186_pmc_irq_set_type()
2447 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2454 if (data->parent_data) in tegra_irq_mask_parent()
2460 if (data->parent_data) in tegra_irq_unmask_parent()
2466 if (data->parent_data) in tegra_irq_eoi_parent()
2474 if (data->parent_data) in tegra_irq_set_affinity_parent()
2477 return -EINVAL; in tegra_irq_set_affinity_parent()
2485 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2494 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2495 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2496 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2497 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2498 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2499 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2500 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2502 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2504 if (!pmc->domain) { in tegra_pmc_irq_init()
2505 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2506 return -ENOMEM; in tegra_pmc_irq_init()
2520 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2524 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2528 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2533 return notifier_from_errno(-EINVAL); in tegra_pmc_clk_notify_cb()
2551 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2562 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2563 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2564 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2565 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2566 pmc_clk_fence_udelay(clk->offs); in pmc_clk_mux_set_parent()
2576 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2595 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); in pmc_clk_enable()
2604 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2624 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2626 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_out_register()
2628 init.name = data->name; in tegra_pmc_clk_out_register()
2630 init.parent_names = data->parents; in tegra_pmc_clk_out_register()
2631 init.num_parents = data->num_parents; in tegra_pmc_clk_out_register()
2635 pmc_clk->hw.init = &init; in tegra_pmc_clk_out_register()
2636 pmc_clk->offs = offset; in tegra_pmc_clk_out_register()
2637 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
2638 pmc_clk->force_en_shift = data->force_en_shift; in tegra_pmc_clk_out_register()
2640 return clk_register(NULL, &pmc_clk->hw); in tegra_pmc_clk_out_register()
2647 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2654 pmc_clk_set_state(gate->offs, gate->shift, 1); in pmc_clk_gate_enable()
2663 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2680 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2682 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_gate_register()
2690 gate->hw.init = &init; in tegra_pmc_clk_gate_register()
2691 gate->offs = offset; in tegra_pmc_clk_gate_register()
2692 gate->shift = shift; in tegra_pmc_clk_gate_register()
2694 return clk_register(NULL, &gate->hw); in tegra_pmc_clk_gate_register()
2705 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2706 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2712 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2716 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2717 sizeof(*clk_data->clks), GFP_KERNEL); in tegra_pmc_clock_register()
2718 if (!clk_data->clks) in tegra_pmc_clock_register()
2721 clk_data->clk_num = TEGRA_PMC_CLK_MAX; in tegra_pmc_clock_register()
2724 clk_data->clks[i] = ERR_PTR(-ENOENT); in tegra_pmc_clock_register()
2726 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2729 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2733 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2734 data->name, PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2738 err = clk_register_clkdev(clk, data->name, NULL); in tegra_pmc_clock_register()
2740 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2742 data->name, err); in tegra_pmc_clock_register()
2746 clk_data->clks[data->clk_id] = clk; in tegra_pmc_clock_register()
2749 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2757 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2768 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2776 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2782 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; in tegra_pmc_clock_register()
2787 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2840 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2841 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2844 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2854 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2868 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2869 return -ENODEV; in tegra_pmc_probe()
2871 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2875 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, in tegra_pmc_probe()
2885 if (pmc->soc->has_single_mmio_aperture) { in tegra_pmc_probe()
2886 pmc->wake = base; in tegra_pmc_probe()
2887 pmc->aotag = base; in tegra_pmc_probe()
2888 pmc->scratch = base; in tegra_pmc_probe()
2890 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); in tegra_pmc_probe()
2891 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2892 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2894 pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag"); in tegra_pmc_probe()
2895 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2896 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2902 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2903 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2904 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2906 pmc->scratch = NULL; in tegra_pmc_probe()
2910 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); in tegra_pmc_probe()
2911 if (IS_ERR(pmc->clk)) in tegra_pmc_probe()
2912 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), in tegra_pmc_probe()
2916 * PMC should be last resort for restarting since it soft-resets in tegra_pmc_probe()
2919 if (pmc->scratch) { in tegra_pmc_probe()
2920 err = devm_register_reboot_notifier(&pdev->dev, in tegra_pmc_probe()
2923 dev_err(&pdev->dev, in tegra_pmc_probe()
2930 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2935 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2941 * PMC should be primary power-off method if it soft-resets CPU, in tegra_pmc_probe()
2944 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2949 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2959 if (pmc->clk) { in tegra_pmc_probe()
2960 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2961 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, in tegra_pmc_probe()
2962 &pmc->clk_nb); in tegra_pmc_probe()
2964 dev_err(&pdev->dev, in tegra_pmc_probe()
2969 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2972 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2976 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); in tegra_pmc_probe()
2992 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3000 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
3001 iounmap(pmc->base); in tegra_pmc_probe()
3002 pmc->base = base; in tegra_pmc_probe()
3003 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
3005 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3010 if (pmc->soc->set_wake_filters) in tegra_pmc_probe()
3011 pmc->soc->set_wake_filters(pmc); in tegra_pmc_probe()
3018 tegra_powergate_remove_all(pdev->dev.of_node); in tegra_pmc_probe()
3020 device_remove_file(&pdev->dev, &dev_attr_reset_reason); in tegra_pmc_probe()
3021 device_remove_file(&pdev->dev, &dev_attr_reset_level); in tegra_pmc_probe()
3032 writel(value, pmc->wake + offset); in wke_32kwritel()
3041 value = readl(pmc->wake + offset); in wke_write_wake_level()
3047 writel(value, pmc->wake + offset); in wke_write_wake_level()
3054 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_write_wake_levels()
3055 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); in wke_write_wake_levels()
3068 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3078 * the polarity of the wake level from 0->1 while latching to force in wke_read_sw_wake_status()
3081 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3093 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); in wke_read_sw_wake_status()
3095 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_read_sw_wake_status()
3096 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); in wke_read_sw_wake_status()
3099 set_bit(wake + (i * 32), pmc->wake_sw_status_map); in wke_read_sw_wake_status()
3109 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_clear_wake_status()
3110 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in wke_clear_wake_status()
3111 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in wke_clear_wake_status()
3124 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); in tegra186_pmc_process_wake_events()
3131 irq = irq_find_mapping(pmc->domain, hwirq); in tegra186_pmc_process_wake_events()
3134 if (!desc || !desc->action || !desc->action->name) { in tegra186_pmc_process_wake_events()
3135 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); in tegra186_pmc_process_wake_events()
3139 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); in tegra186_pmc_process_wake_events()
3149 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in tegra186_pmc_wake_syscore_resume()
3150 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in tegra186_pmc_wake_syscore_resume()
3151 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in tegra186_pmc_wake_syscore_resume()
3161 /* flip the wakeup trigger for dual-edge triggered pads in tegra186_pmc_wake_syscore_suspend()
3164 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, in tegra186_pmc_wake_syscore_suspend()
3165 pmc->wake_sw_status_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3166 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, in tegra186_pmc_wake_syscore_suspend()
3167 pmc->wake_type_level_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3229 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3234 if (pmc->corereq_high) in tegra20_pmc_init()
3248 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3249 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3250 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3251 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3487 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"),
3489 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3491 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3492 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3493 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3494 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3496 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"),
3520 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"),
3522 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3524 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3525 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3526 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3527 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3529 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3605 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
3614 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
3627 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3628 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3629 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3630 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3631 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
3633 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"),
3635 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
3641 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
3646 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3655 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
3668 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3669 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3670 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3672 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3674 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3676 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3737 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3738 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3739 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3740 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3741 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3745 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
3750 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3751 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3752 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3753 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
3765 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
3767 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3768 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3770 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3771 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3778 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3779 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3780 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3781 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3782 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3786 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3791 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3792 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
3793 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3794 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
3811 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
3826 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; in tegra186_pmc_init()
3827 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; in tegra186_pmc_init()
3829 register_syscore_ops(&pmc->syscore); in tegra186_pmc_init()
3841 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
3843 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3851 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3934 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3935 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3936 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3937 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3938 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3940 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
3941 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
3945 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
3946 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
3948 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
3949 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
3950 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
3951 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
3952 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
3956 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
3957 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
3958 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3959 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3960 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3961 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
3962 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
3963 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
3965 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
3976 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3977 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3979 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3980 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3986 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3987 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3988 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3989 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3990 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3992 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
3993 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
3997 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
3998 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
4000 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
4001 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
4002 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
4003 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
4004 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
4008 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4073 TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
4074 TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
4075 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
4076 TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
4077 TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
4078 TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
4079 TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
4121 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4128 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
4129 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
4130 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
4131 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4139 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4146 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4147 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4148 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4149 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4205 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)),
4211 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),
4250 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4251 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4252 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4253 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4254 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4255 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4256 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4257 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4258 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4267 * Newer device-trees have power domains, but we need to prepare all in tegra_pmc_sync_state()
4271 if (!pmc->soc->supports_core_domain) in tegra_pmc_sync_state()
4275 * Older device-trees don't have core PD, and thus, there are in tegra_pmc_sync_state()
4279 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
4282 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
4284 /* this is a no-op if core regulator isn't used */ in tegra_pmc_sync_state()
4285 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4287 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4295 .name = "tegra-pmc",
4311 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4318 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4319 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4321 /* if we read all-zeroes, access is restricted to TZ only */ in tegra_pmc_detect_tz_only()
4328 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4345 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
4350 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
4351 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
4354 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
4370 * nice with multi-platform kernels. in tegra_pmc_early_init()
4382 return -ENXIO; in tegra_pmc_early_init()
4386 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
4387 if (!pmc->base) { in tegra_pmc_early_init()
4390 return -ENXIO; in tegra_pmc_early_init()
4394 pmc->soc = match->data; in tegra_pmc_early_init()
4396 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
4397 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
4400 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
4401 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
4402 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
4406 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
4408 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
4410 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()