Lines Matching +full:pex +full:- +full:clk +full:- +full:bias
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
37 #include <linux/pinctrl/pinconf-generic.h>
57 #include <dt-bindings/interrupt-controller/arm-gic.h>
58 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
59 #include <dt-bindings/gpio/tegra186-gpio.h>
60 #include <dt-bindings/gpio/tegra194-gpio.h>
61 #include <dt-bindings/gpio/tegra234-gpio.h>
62 #include <dt-bindings/soc/tegra-pmc.h>
70 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
272 struct clk **clks;
392 * struct tegra_pmc - NVIDIA Tegra PMC
398 * @clk: pointer to pclk clock
408 * @corereq_high: core power request is active-high
409 * @sysclkreq_high: system clock request is active-high
422 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
423 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
434 struct clk *clk; member
489 if (pmc->tz_only) { in tegra_pmc_readl()
493 if (pmc->dev) in tegra_pmc_readl()
494 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
504 return readl(pmc->base + offset); in tegra_pmc_readl()
512 if (pmc->tz_only) { in tegra_pmc_writel()
516 if (pmc->dev) in tegra_pmc_writel()
517 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
524 writel(value, pmc->base + offset); in tegra_pmc_writel()
530 if (pmc->tz_only) in tegra_pmc_scratch_readl()
533 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
539 if (pmc->tz_only) in tegra_pmc_scratch_writel()
542 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
552 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
560 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
565 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
572 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
573 return -EINVAL; in tegra_powergate_lookup()
575 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
579 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
583 return -ENODEV; in tegra_powergate_lookup()
595 * if there is contention with a HW-initiated toggling (i.e. CPU core in tegra20_powergate_set()
596 * power-gated), the command should be retried in that case. in tegra20_powergate_set()
604 } while (ret == -ETIMEDOUT && retries--); in tegra20_powergate_set()
644 * tegra_powergate_set() - set the state of a partition
654 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
655 return -EINVAL; in tegra_powergate_set()
657 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
660 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
664 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
666 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
676 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
683 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
703 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
714 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_prepare_clocks()
715 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); in tegra_powergate_prepare_clocks()
717 if (!pg->clk_rates[i]) { in tegra_powergate_prepare_clocks()
718 err = -EINVAL; in tegra_powergate_prepare_clocks()
722 if (pg->clk_rates[i] <= safe_rate) in tegra_powergate_prepare_clocks()
731 err = clk_set_rate(pg->clks[i], safe_rate); in tegra_powergate_prepare_clocks()
739 while (i--) in tegra_powergate_prepare_clocks()
740 clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_prepare_clocks()
750 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_unprepare_clocks()
751 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_unprepare_clocks()
763 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
764 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
772 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
773 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
781 while (i--) in tegra_powergate_enable_clocks()
782 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
792 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
798 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
814 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
820 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
826 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
827 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
848 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
867 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
877 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
890 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
905 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
911 pg->genpd.name, err); in tegra_genpd_power_on()
915 reset_control_release(pg->reset); in tegra_genpd_power_on()
924 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
927 err = reset_control_acquire(pg->reset); in tegra_genpd_power_off()
930 pg->genpd.name, err); in tegra_genpd_power_off()
937 pg->genpd.name, err); in tegra_genpd_power_off()
938 reset_control_release(pg->reset); in tegra_genpd_power_off()
945 * tegra_powergate_power_on() - power on partition
951 return -EINVAL; in tegra_powergate_power_on()
958 * tegra_powergate_power_off() - power off partition
964 return -EINVAL; in tegra_powergate_power_off()
971 * tegra_powergate_is_powered() - check if partition is powered
978 return -EINVAL; in tegra_powergate_is_powered()
984 * tegra_powergate_remove_clamping() - remove power clamps for partition
990 return -EINVAL; in tegra_powergate_remove_clamping()
997 * tegra_powergate_sequence_power_up() - power up partition
999 * @clk: clock for partition
1002 * Must be called with clk disabled, and returns with clk enabled.
1004 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, in tegra_powergate_sequence_power_up() argument
1011 return -EINVAL; in tegra_powergate_sequence_power_up()
1015 return -ENOMEM; in tegra_powergate_sequence_power_up()
1017 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_sequence_power_up()
1018 if (!pg->clk_rates) { in tegra_powergate_sequence_power_up()
1019 kfree(pg->clks); in tegra_powergate_sequence_power_up()
1020 return -ENOMEM; in tegra_powergate_sequence_power_up()
1023 pg->id = id; in tegra_powergate_sequence_power_up()
1024 pg->clks = &clk; in tegra_powergate_sequence_power_up()
1025 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
1026 pg->reset = rst; in tegra_powergate_sequence_power_up()
1027 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
1031 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
1034 kfree(pg->clk_rates); in tegra_powergate_sequence_power_up()
1042 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1052 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1053 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1055 return -EINVAL; in tegra_get_cpu_powergate_id()
1059 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1074 * tegra_pmc_cpu_power_on() - power on CPU partition
1089 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1107 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1117 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_program_reboot_reason()
1121 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1177 seq_printf(s, "------------------\n"); in powergate_show()
1179 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1184 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1196 struct clk *clk; in tegra_powergate_of_get_clks() local
1202 return -ENODEV; in tegra_powergate_of_get_clks()
1204 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
1205 if (!pg->clks) in tegra_powergate_of_get_clks()
1206 return -ENOMEM; in tegra_powergate_of_get_clks()
1208 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_of_get_clks()
1209 if (!pg->clk_rates) { in tegra_powergate_of_get_clks()
1210 kfree(pg->clks); in tegra_powergate_of_get_clks()
1211 return -ENOMEM; in tegra_powergate_of_get_clks()
1215 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
1216 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
1217 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
1222 pg->num_clks = count; in tegra_powergate_of_get_clks()
1227 while (i--) in tegra_powergate_of_get_clks()
1228 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
1230 kfree(pg->clk_rates); in tegra_powergate_of_get_clks()
1231 kfree(pg->clks); in tegra_powergate_of_get_clks()
1239 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1242 pg->reset = of_reset_control_array_get_exclusive_released(np); in tegra_powergate_of_get_resets()
1243 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
1244 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
1249 err = reset_control_acquire(pg->reset); in tegra_powergate_of_get_resets()
1256 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
1258 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
1262 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1267 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1268 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
1276 struct device *dev = pmc->dev; in tegra_powergate_add()
1283 return -ENOMEM; in tegra_powergate_add()
1285 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1288 err = -ENODEV; in tegra_powergate_add()
1296 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1298 pg->id = id; in tegra_powergate_add()
1299 pg->genpd.name = np->name; in tegra_powergate_add()
1300 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
1301 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
1302 pg->pmc = pmc; in tegra_powergate_add()
1304 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1325 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
1332 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
1339 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
1344 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
1347 reset_control_put(pg->reset); in tegra_powergate_add()
1350 while (pg->num_clks--) in tegra_powergate_add()
1351 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
1353 kfree(pg->clks); in tegra_powergate_add()
1356 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1366 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1376 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); in tegra_pmc_core_pd_set_performance_state()
1378 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", in tegra_pmc_core_pd_set_performance_state()
1383 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1384 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1385 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1390 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", in tegra_pmc_core_pd_set_performance_state()
1404 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1406 return -ENOMEM; in tegra_pmc_core_pd_add()
1408 genpd->name = "core"; in tegra_pmc_core_pd_add()
1409 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; in tegra_pmc_core_pd_add()
1411 err = devm_pm_opp_set_regulators(pmc->dev, rname); in tegra_pmc_core_pd_add()
1413 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1418 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1424 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1428 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1449 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_init()
1466 if (of_parse_phandle_with_args(child, "power-domains", in tegra_powergate_init()
1467 "#power-domain-cells", in tegra_powergate_init()
1489 reset_control_put(pg->reset); in tegra_powergate_remove()
1491 while (pg->num_clks--) in tegra_powergate_remove()
1492 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_remove()
1494 kfree(pg->clks); in tegra_powergate_remove()
1496 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1522 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_remove_all()
1534 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1535 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1536 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1549 if (pad->dpd == UINT_MAX) in tegra_io_pad_prepare()
1550 return -EINVAL; in tegra_io_pad_prepare()
1552 *request = pad->request; in tegra_io_pad_prepare()
1553 *status = pad->status; in tegra_io_pad_prepare()
1554 *mask = BIT(pad->dpd); in tegra_io_pad_prepare()
1556 if (pmc->clk) { in tegra_io_pad_prepare()
1557 rate = pmc->rate; in tegra_io_pad_prepare()
1559 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1560 return -ENODEV; in tegra_io_pad_prepare()
1589 return -ETIMEDOUT; in tegra_io_pad_poll()
1594 if (pmc->clk) in tegra_io_pad_unprepare()
1599 * tegra_io_pad_power_enable() - enable power to I/O pad
1613 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_enable()
1614 return -ENOENT; in tegra_io_pad_power_enable()
1617 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1621 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1629 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1636 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1642 * tegra_io_pad_power_disable() - disable power to I/O pad
1656 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_disable()
1657 return -ENOENT; in tegra_io_pad_power_disable()
1660 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1664 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1672 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1679 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1692 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_is_powered()
1693 return -ENOENT; in tegra_io_pad_is_powered()
1696 if (pad->dpd == UINT_MAX) in tegra_io_pad_is_powered()
1697 return -EINVAL; in tegra_io_pad_is_powered()
1699 status = pad->status; in tegra_io_pad_is_powered()
1700 mask = BIT(pad->dpd); in tegra_io_pad_is_powered()
1715 return -ENOENT; in tegra_io_pad_set_voltage()
1717 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1718 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1720 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1722 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1726 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1728 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1732 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1734 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1741 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1743 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1748 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1762 return -ENOENT; in tegra_io_pad_get_voltage()
1764 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1765 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1767 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1772 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1781 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1789 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1804 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1814 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1818 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1833 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1834 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1838 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1842 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1846 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1850 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1855 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1857 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1858 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1860 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1862 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1863 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1865 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1867 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1869 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1871 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1872 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1874 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1875 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1877 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1879 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1880 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1882 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1883 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1885 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1886 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1888 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1889 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1891 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1893 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1894 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1896 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1897 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1904 if (pmc->soc->max_wake_events > 0) { in tegra_pmc_init()
1905 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1906 if (!pmc->wake_type_level_map) in tegra_pmc_init()
1907 return -ENOMEM; in tegra_pmc_init()
1909 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1910 if (!pmc->wake_type_dual_edge_map) in tegra_pmc_init()
1911 return -ENOMEM; in tegra_pmc_init()
1913 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1914 if (!pmc->wake_sw_status_map) in tegra_pmc_init()
1915 return -ENOMEM; in tegra_pmc_init()
1917 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1918 if (!pmc->wake_cntrl_level_map) in tegra_pmc_init()
1919 return -ENOMEM; in tegra_pmc_init()
1922 if (pmc->soc->init) in tegra_pmc_init()
1923 pmc->soc->init(pmc); in tegra_pmc_init()
1932 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1936 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1939 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1941 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1945 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1950 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1951 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1955 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1956 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1960 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1961 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1965 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
1988 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1998 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
2008 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
2016 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
2026 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2051 return -EINVAL; in tegra_io_pad_pinconf_get()
2055 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2063 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2071 return -EINVAL; in tegra_io_pad_pinconf_get()
2092 return -EINVAL; in tegra_io_pad_pinconf_set()
2101 err = tegra_io_pad_power_disable(pad->id); in tegra_io_pad_pinconf_set()
2103 err = tegra_io_pad_power_enable(pad->id); in tegra_io_pad_pinconf_set()
2110 return -EINVAL; in tegra_io_pad_pinconf_set()
2111 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2116 return -EINVAL; in tegra_io_pad_pinconf_set()
2138 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2141 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2142 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2143 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2145 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2147 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2148 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2149 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2162 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2163 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2164 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2166 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2169 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2179 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2180 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2181 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2183 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2186 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2193 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2196 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2204 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2218 if (WARN_ON(fwspec->param_count < 2)) in tegra_pmc_irq_translate()
2219 return -EINVAL; in tegra_pmc_irq_translate()
2221 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
2222 *type = fwspec->param[1]; in tegra_pmc_irq_translate()
2230 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc()
2231 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2237 return -EINVAL; in tegra_pmc_irq_alloc()
2239 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
2240 const struct tegra_wake_event *event = &soc->wake_events[i]; in tegra_pmc_irq_alloc()
2243 if (fwspec->param_count == 2) { in tegra_pmc_irq_alloc()
2246 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
2250 event->id, in tegra_pmc_irq_alloc()
2251 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2256 if (event->irq == 0) { in tegra_pmc_irq_alloc()
2257 err = irq_domain_disconnect_hierarchy(domain->parent, virq); in tegra_pmc_irq_alloc()
2261 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2264 spec.param[1] = event->irq; in tegra_pmc_irq_alloc()
2265 spec.param[2] = fwspec->param[1]; in tegra_pmc_irq_alloc()
2274 if (fwspec->param_count == 3) { in tegra_pmc_irq_alloc()
2275 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2276 event->gpio.pin != fwspec->param[1]) in tegra_pmc_irq_alloc()
2280 event->id, in tegra_pmc_irq_alloc()
2281 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2284 if (!err && domain->parent) in tegra_pmc_irq_alloc()
2285 err = irq_domain_disconnect_hierarchy(domain->parent, in tegra_pmc_irq_alloc()
2291 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2292 if (i == soc->num_wake_events) in tegra_pmc_irq_alloc()
2309 offset = data->hwirq / 32; in tegra210_pmc_irq_set_wake()
2310 bit = data->hwirq % 32; in tegra210_pmc_irq_set_wake()
2320 if (data->hwirq >= 32) in tegra210_pmc_irq_set_wake()
2343 offset = data->hwirq / 32; in tegra210_pmc_irq_set_type()
2344 bit = data->hwirq % 32; in tegra210_pmc_irq_set_type()
2346 if (data->hwirq >= 32) in tegra210_pmc_irq_set_type()
2369 return -EINVAL; in tegra210_pmc_irq_set_type()
2382 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2384 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2385 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); in tegra186_pmc_set_wake_filters()
2394 offset = data->hwirq / 32; in tegra186_pmc_irq_set_wake()
2395 bit = data->hwirq % 32; in tegra186_pmc_irq_set_wake()
2398 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2401 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2408 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2411 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2421 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2427 set_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2428 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2434 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2435 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2440 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2441 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2445 return -EINVAL; in tegra186_pmc_irq_set_type()
2448 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2455 if (data->parent_data) in tegra_irq_mask_parent()
2461 if (data->parent_data) in tegra_irq_unmask_parent()
2467 if (data->parent_data) in tegra_irq_eoi_parent()
2475 if (data->parent_data) in tegra_irq_set_affinity_parent()
2478 return -EINVAL; in tegra_irq_set_affinity_parent()
2486 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2495 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2496 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2497 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2498 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2499 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2500 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2501 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2503 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2505 if (!pmc->domain) { in tegra_pmc_irq_init()
2506 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2507 return -ENOMEM; in tegra_pmc_irq_init()
2521 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2525 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2529 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2534 return notifier_from_errno(-EINVAL); in tegra_pmc_clk_notify_cb()
2543 /* pmc clk propagation delay 2 us */ in pmc_clk_fence_udelay()
2549 struct pmc_clk *clk = to_pmc_clk(hw); in pmc_clk_mux_get_parent() local
2552 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2560 struct pmc_clk *clk = to_pmc_clk(hw); in pmc_clk_mux_set_parent() local
2563 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2564 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2565 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2566 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2567 pmc_clk_fence_udelay(clk->offs); in pmc_clk_mux_set_parent()
2574 struct pmc_clk *clk = to_pmc_clk(hw); in pmc_clk_is_enabled() local
2577 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2594 struct pmc_clk *clk = to_pmc_clk(hw); in pmc_clk_enable() local
2596 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); in pmc_clk_enable()
2603 struct pmc_clk *clk = to_pmc_clk(hw); in pmc_clk_disable() local
2605 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2617 static struct clk *
2625 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2627 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_out_register()
2629 init.name = data->name; in tegra_pmc_clk_out_register()
2631 init.parent_names = data->parents; in tegra_pmc_clk_out_register()
2632 init.num_parents = data->num_parents; in tegra_pmc_clk_out_register()
2636 pmc_clk->hw.init = &init; in tegra_pmc_clk_out_register()
2637 pmc_clk->offs = offset; in tegra_pmc_clk_out_register()
2638 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
2639 pmc_clk->force_en_shift = data->force_en_shift; in tegra_pmc_clk_out_register()
2641 return clk_register(NULL, &pmc_clk->hw); in tegra_pmc_clk_out_register()
2648 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2655 pmc_clk_set_state(gate->offs, gate->shift, 1); in pmc_clk_gate_enable()
2664 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2673 static struct clk *
2681 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2683 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_gate_register()
2691 gate->hw.init = &init; in tegra_pmc_clk_gate_register()
2692 gate->offs = offset; in tegra_pmc_clk_gate_register()
2693 gate->shift = shift; in tegra_pmc_clk_gate_register()
2695 return clk_register(NULL, &gate->hw); in tegra_pmc_clk_gate_register()
2701 struct clk *clk; in tegra_pmc_clock_register() local
2706 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2707 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2713 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2717 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2718 sizeof(*clk_data->clks), GFP_KERNEL); in tegra_pmc_clock_register()
2719 if (!clk_data->clks) in tegra_pmc_clock_register()
2722 clk_data->clk_num = TEGRA_PMC_CLK_MAX; in tegra_pmc_clock_register()
2725 clk_data->clks[i] = ERR_PTR(-ENOENT); in tegra_pmc_clock_register()
2727 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2730 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2732 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); in tegra_pmc_clock_register()
2733 if (IS_ERR(clk)) { in tegra_pmc_clock_register()
2734 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2735 data->name, PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2739 err = clk_register_clkdev(clk, data->name, NULL); in tegra_pmc_clock_register()
2741 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2743 data->name, err); in tegra_pmc_clock_register()
2747 clk_data->clks[data->clk_id] = clk; in tegra_pmc_clock_register()
2750 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2752 clk = tegra_pmc_clk_gate_register(pmc, in tegra_pmc_clock_register()
2757 if (IS_ERR(clk)) { in tegra_pmc_clock_register()
2758 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2760 PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2764 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", in tegra_pmc_clock_register()
2768 if (IS_ERR(clk)) { in tegra_pmc_clock_register()
2769 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2771 PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2775 err = clk_register_clkdev(clk, "pmc_blink", NULL); in tegra_pmc_clock_register()
2777 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2783 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; in tegra_pmc_clock_register()
2788 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2841 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2842 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2845 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2855 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2869 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2870 return -ENODEV; in tegra_pmc_probe()
2872 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2876 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, in tegra_pmc_probe()
2886 if (pmc->soc->has_single_mmio_aperture) { in tegra_pmc_probe()
2887 pmc->wake = base; in tegra_pmc_probe()
2888 pmc->aotag = base; in tegra_pmc_probe()
2889 pmc->scratch = base; in tegra_pmc_probe()
2891 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); in tegra_pmc_probe()
2892 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2893 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2895 pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag"); in tegra_pmc_probe()
2896 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2897 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2903 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2904 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2905 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2907 pmc->scratch = NULL; in tegra_pmc_probe()
2911 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); in tegra_pmc_probe()
2912 if (IS_ERR(pmc->clk)) in tegra_pmc_probe()
2913 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), in tegra_pmc_probe()
2917 * PMC should be last resort for restarting since it soft-resets in tegra_pmc_probe()
2920 if (pmc->scratch) { in tegra_pmc_probe()
2921 err = devm_register_reboot_notifier(&pdev->dev, in tegra_pmc_probe()
2924 dev_err(&pdev->dev, in tegra_pmc_probe()
2931 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2936 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2942 * PMC should be primary power-off method if it soft-resets CPU, in tegra_pmc_probe()
2945 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2950 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2956 * PCLK clock rate can't be retrieved using CLK API because it in tegra_pmc_probe()
2958 * CLK notifier, hence we're caching the rate's value locally. in tegra_pmc_probe()
2960 if (pmc->clk) { in tegra_pmc_probe()
2961 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2962 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, in tegra_pmc_probe()
2963 &pmc->clk_nb); in tegra_pmc_probe()
2965 dev_err(&pdev->dev, in tegra_pmc_probe()
2966 "failed to register clk notifier\n"); in tegra_pmc_probe()
2970 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2973 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2977 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); in tegra_pmc_probe()
2993 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3001 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
3002 iounmap(pmc->base); in tegra_pmc_probe()
3003 pmc->base = base; in tegra_pmc_probe()
3004 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
3006 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3011 if (pmc->soc->set_wake_filters) in tegra_pmc_probe()
3012 pmc->soc->set_wake_filters(pmc); in tegra_pmc_probe()
3019 tegra_powergate_remove_all(pdev->dev.of_node); in tegra_pmc_probe()
3021 device_remove_file(&pdev->dev, &dev_attr_reset_reason); in tegra_pmc_probe()
3022 device_remove_file(&pdev->dev, &dev_attr_reset_level); in tegra_pmc_probe()
3033 writel(value, pmc->wake + offset); in wke_32kwritel()
3042 value = readl(pmc->wake + offset); in wke_write_wake_level()
3048 writel(value, pmc->wake + offset); in wke_write_wake_level()
3055 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_write_wake_levels()
3056 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); in wke_write_wake_levels()
3069 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3079 * the polarity of the wake level from 0->1 while latching to force in wke_read_sw_wake_status()
3082 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3094 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); in wke_read_sw_wake_status()
3096 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_read_sw_wake_status()
3097 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); in wke_read_sw_wake_status()
3100 set_bit(wake + (i * 32), pmc->wake_sw_status_map); in wke_read_sw_wake_status()
3110 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_clear_wake_status()
3111 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in wke_clear_wake_status()
3112 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in wke_clear_wake_status()
3125 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); in tegra186_pmc_process_wake_events()
3132 irq = irq_find_mapping(pmc->domain, hwirq); in tegra186_pmc_process_wake_events()
3135 if (!desc || !desc->action || !desc->action->name) { in tegra186_pmc_process_wake_events()
3136 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); in tegra186_pmc_process_wake_events()
3140 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); in tegra186_pmc_process_wake_events()
3150 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in tegra186_pmc_wake_syscore_resume()
3151 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in tegra186_pmc_wake_syscore_resume()
3152 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in tegra186_pmc_wake_syscore_resume()
3162 /* flip the wakeup trigger for dual-edge triggered pads in tegra186_pmc_wake_syscore_suspend()
3165 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, in tegra186_pmc_wake_syscore_suspend()
3166 pmc->wake_sw_status_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3167 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, in tegra186_pmc_wake_syscore_suspend()
3168 pmc->wake_type_level_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3230 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3235 if (pmc->corereq_high) in tegra20_pmc_init()
3249 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3250 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3251 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3252 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3490 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3492 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3493 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3494 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3495 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3523 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3525 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3526 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3527 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3528 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3606 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
3615 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
3628 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3629 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3630 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3631 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3632 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
3636 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
3642 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
3647 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3656 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
3669 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3670 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3672 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3673 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
3683 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3738 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3739 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3740 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3741 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3742 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3746 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
3751 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3752 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3753 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3754 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
3766 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
3768 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3769 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3771 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3772 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3779 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3780 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3781 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3782 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3783 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3787 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3792 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3793 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
3794 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3795 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3813 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
3827 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; in tegra186_pmc_init()
3828 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; in tegra186_pmc_init()
3830 register_syscore_ops(&pmc->syscore); in tegra186_pmc_init()
3842 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
3844 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3852 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3935 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3936 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3937 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3938 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3939 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3941 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
3942 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
3946 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
3947 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
3949 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
3950 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
3951 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
3952 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
3953 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
3957 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
3958 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
3959 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3960 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3961 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3962 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
3963 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
3964 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
3966 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
3977 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3978 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3980 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3981 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3987 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3988 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3989 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3990 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3991 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3993 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
3994 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
3998 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
3999 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
4001 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
4002 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
4003 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
4004 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
4005 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4074 TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
4075 TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
4076 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
4077 TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
4078 TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
4079 TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
4080 TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
4122 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4129 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
4130 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
4131 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
4132 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4140 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4147 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4148 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4149 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4150 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4206 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)),
4212 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),
4251 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4252 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4253 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4254 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4255 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4256 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4257 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4258 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4259 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4268 * Newer device-trees have power domains, but we need to prepare all in tegra_pmc_sync_state()
4272 if (!pmc->soc->supports_core_domain) in tegra_pmc_sync_state()
4276 * Older device-trees don't have core PD, and thus, there are in tegra_pmc_sync_state()
4280 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
4283 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
4285 /* this is a no-op if core regulator isn't used */ in tegra_pmc_sync_state()
4286 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4288 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4296 .name = "tegra-pmc",
4312 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4319 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4320 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4322 /* if we read all-zeroes, access is restricted to TZ only */ in tegra_pmc_detect_tz_only()
4329 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4346 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
4351 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
4352 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
4355 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
4371 * nice with multi-platform kernels. in tegra_pmc_early_init()
4383 return -ENXIO; in tegra_pmc_early_init()
4387 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
4388 if (!pmc->base) { in tegra_pmc_early_init()
4391 return -ENXIO; in tegra_pmc_early_init()
4395 pmc->soc = match->data; in tegra_pmc_early_init()
4397 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
4398 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
4401 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
4402 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
4403 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
4407 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
4409 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
4411 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()