19 #define FUSE_SKU_INFO	0x10
21 #define ERD_ERR_CONFIG 0x120c
22 #define ERD_MASK_INBAND_ERR 0x1
26 	(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
28 	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
44 	return (tegra_read_chipid() >> 8) & 0xff;  in tegra_get_chip_id()
49 	return (tegra_read_chipid() >> 4) & 0xf;  in tegra_get_major_rev()
54 	return (tegra_read_chipid() >> 16) & 0xf;  in tegra_get_minor_rev()
59 	return (tegra_read_chipid() >> 20) & 0xf;  in tegra_get_platform()
69 		if (tegra_get_platform() == 0)  in tegra_is_silicon()
122 	return 0;  in tegra194_miscreg_mask_serror()
209 			apbmisc.start = 0x70000800;  in tegra_init_apbmisc()
210 			apbmisc.end = 0x70000863;  in tegra_init_apbmisc()
215 				straps.start = 0x7000e864;  in tegra_init_apbmisc()
216 				straps.end = 0x7000e867;  in tegra_init_apbmisc()
218 				straps.start = 0x70000008;  in tegra_init_apbmisc()
219 				straps.end = 0x7000000b;  in tegra_init_apbmisc()
239 		if (of_address_to_resource(np, 0, &apbmisc) < 0) {  in tegra_init_apbmisc()
244 		if (of_address_to_resource(np, 1, &straps) < 0) {  in tegra_init_apbmisc()
269 	int rcount = 0;  in tegra_acpi_init_apbmisc()
272 	adev = acpi_dev_get_first_match_dev(apbmisc_acpi_match[0].id, NULL, -1);  in tegra_acpi_init_apbmisc()
279 	if (ret < 0) {  in tegra_acpi_init_apbmisc()
287 	 * resources[0]: apbmisc.  in tegra_acpi_init_apbmisc()
297 	if (!resources[0]) {  in tegra_acpi_init_apbmisc()
307 	tegra_init_apbmisc_resources(resources[0], resources[1]);  in tegra_acpi_init_apbmisc()