Lines Matching +full:mt8195 +full:- +full:efuse
1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/nvmem-consumer.h>
147 inode->i_private); \
162 inode->i_private); \
177 * enum svsb_sw_id - SVS Bank Software ID
193 * enum svsb_type - SVS Bank 2-line: Type and Role
194 * @SVSB_TYPE_NONE: One-line type Bank - Global role
195 * @SVSB_TYPE_LOW: Two-line type Bank - Low bank role
196 * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role
207 * enum svsb_phase - svs bank phase enumeration
218 * svs bank general phase-enabled order:
219 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
373 * struct svs_platform - svs platform control
379 * @efuse_max: total number of svs efuse
380 * @tefuse_max: total number of thermal efuse
382 * @efuse: svs efuse data received from NVMEM framework
383 * @tefuse: thermal efuse data received from NVMEM framework
396 u32 *efuse; member
414 * struct svs_bank_pdata - SVS Bank immutable config parameters
419 * @ctl0: TS-x selection
422 * @turn_freq_base: Reference frequency for 2-line turn point
435 * @type: SVS Bank Type (1 or 2-line) and Role (high/low)
468 * struct svs_bank - svs bank representation
495 * @bts: svs efuse data
496 * @mts: svs efuse data
497 * @bdes: svs efuse data
498 * @mdes: svs efuse data
499 * @mtdes: svs efuse data
500 * @dcbdet: svs efuse data
501 * @dcmdet: svs efuse data
502 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
559 return readl_relaxed(svsp->base + svsp->regs[rg_i]); in svs_readl_relaxed()
565 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); in svs_writel_relaxed()
570 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); in svs_switch_bank()
582 return (opp_u_volt - svsb_volt_base) / svsb_volt_step; in svs_opp_volt_to_bank_volt()
587 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_sync_bank_volts_from_opp()
591 for (i = 0; i < bdata->opp_count; i++) { in svs_sync_bank_volts_from_opp()
592 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, in svs_sync_bank_volts_from_opp()
593 svsb->opp_dfreq[i], in svs_sync_bank_volts_from_opp()
596 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n", in svs_sync_bank_volts_from_opp()
597 svsb->opp_dfreq[i], PTR_ERR(opp)); in svs_sync_bank_volts_from_opp()
602 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, in svs_sync_bank_volts_from_opp()
603 bdata->volt_step, in svs_sync_bank_volts_from_opp()
604 bdata->volt_base); in svs_sync_bank_volts_from_opp()
613 int ret = -EPERM, tzone_temp = 0; in svs_adjust_pm_opp_volts()
614 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_adjust_pm_opp_volts()
617 mutex_lock(&svsb->lock); in svs_adjust_pm_opp_volts()
620 * 2-line bank updates its corresponding opp volts. in svs_adjust_pm_opp_volts()
621 * 1-line bank updates all opp volts. in svs_adjust_pm_opp_volts()
623 if (bdata->type == SVSB_TYPE_HIGH) { in svs_adjust_pm_opp_volts()
625 opp_stop = svsb->turn_pt; in svs_adjust_pm_opp_volts()
626 } else if (bdata->type == SVSB_TYPE_LOW) { in svs_adjust_pm_opp_volts()
627 opp_start = svsb->turn_pt; in svs_adjust_pm_opp_volts()
628 opp_stop = bdata->opp_count; in svs_adjust_pm_opp_volts()
631 opp_stop = bdata->opp_count; in svs_adjust_pm_opp_volts()
635 if (!IS_ERR_OR_NULL(svsb->tzd)) { in svs_adjust_pm_opp_volts()
636 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); in svs_adjust_pm_opp_volts()
637 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && in svs_adjust_pm_opp_volts()
638 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { in svs_adjust_pm_opp_volts()
639 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", in svs_adjust_pm_opp_volts()
640 bdata->tzone_name, ret, svsb->temp); in svs_adjust_pm_opp_volts()
641 svsb->phase = SVSB_PHASE_ERROR; in svs_adjust_pm_opp_volts()
644 if (tzone_temp >= bdata->tzone_htemp) in svs_adjust_pm_opp_volts()
645 temp_voffset += bdata->tzone_htemp_voffset; in svs_adjust_pm_opp_volts()
646 else if (tzone_temp <= bdata->tzone_ltemp) in svs_adjust_pm_opp_volts()
647 temp_voffset += bdata->tzone_ltemp_voffset; in svs_adjust_pm_opp_volts()
649 /* 2-line bank update all opp volts when running mon mode */ in svs_adjust_pm_opp_volts()
650 if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH || in svs_adjust_pm_opp_volts()
651 bdata->type == SVSB_TYPE_LOW)) { in svs_adjust_pm_opp_volts()
653 opp_stop = bdata->opp_count; in svs_adjust_pm_opp_volts()
659 switch (svsb->phase) { in svs_adjust_pm_opp_volts()
661 opp_volt = svsb->opp_dvolt[i]; in svs_adjust_pm_opp_volts()
668 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); in svs_adjust_pm_opp_volts()
670 bdata->volt_step, in svs_adjust_pm_opp_volts()
671 bdata->volt_base); in svs_adjust_pm_opp_volts()
674 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); in svs_adjust_pm_opp_volts()
675 ret = -EINVAL; in svs_adjust_pm_opp_volts()
679 opp_volt = min(opp_volt, svsb->opp_dvolt[i]); in svs_adjust_pm_opp_volts()
680 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, in svs_adjust_pm_opp_volts()
681 svsb->opp_dfreq[i], in svs_adjust_pm_opp_volts()
683 svsb->opp_dvolt[i]); in svs_adjust_pm_opp_volts()
685 dev_err(svsb->dev, "set %uuV fail: %d\n", in svs_adjust_pm_opp_volts()
692 mutex_unlock(&svsb->lock); in svs_adjust_pm_opp_volts()
702 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) in svs_bank_disable_and_restore_default_volts()
711 svsb->phase = SVSB_PHASE_ERROR; in svs_bank_disable_and_restore_default_volts()
718 struct svs_platform *svsp = (struct svs_platform *)m->private; in svs_dump_debug_show()
723 for (i = 0; i < svsp->efuse_max; i++) in svs_dump_debug_show()
724 if (svsp->efuse && svsp->efuse[i]) in svs_dump_debug_show()
726 i, svsp->efuse[i]); in svs_dump_debug_show()
728 for (i = 0; i < svsp->tefuse_max; i++) in svs_dump_debug_show()
729 if (svsp->tefuse) in svs_dump_debug_show()
731 i, svsp->tefuse[i]); in svs_dump_debug_show()
733 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) { in svs_dump_debug_show()
734 svsb = &svsp->banks[idx]; in svs_dump_debug_show()
747 svs_reg_addr = (unsigned long)(svsp->base + in svs_dump_debug_show()
748 svsp->regs[j]); in svs_dump_debug_show()
750 svs_reg_addr, svsb->reg_data[i][j]); in svs_dump_debug_show()
762 struct svs_bank *svsb = (struct svs_bank *)m->private; in svs_enable_debug_show()
764 switch (svsb->phase) { in svs_enable_debug_show()
789 struct svs_bank *svsb = file_inode(filp)->i_private; in svs_enable_debug_write()
790 struct svs_platform *svsp = dev_get_drvdata(svsb->dev); in svs_enable_debug_write()
795 return -EINVAL; in svs_enable_debug_write()
807 svsb->mode_support = SVSB_MODE_ALL_DISABLE; in svs_enable_debug_write()
819 struct svs_bank *svsb = (struct svs_bank *)m->private; in svs_status_debug_show()
824 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); in svs_status_debug_show()
827 svsb->name, svsb->vbin_turn_pt, svsb->turn_pt); in svs_status_debug_show()
830 svsb->name, tzone_temp, svsb->vbin_turn_pt, in svs_status_debug_show()
831 svsb->turn_pt); in svs_status_debug_show()
833 for (i = 0; i < svsb->pdata.opp_count; i++) { in svs_status_debug_show()
834 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, in svs_status_debug_show()
835 svsb->opp_dfreq[i], true); in svs_status_debug_show()
838 svsb->name, svsb->opp_dfreq[i], in svs_status_debug_show()
844 i, svsb->opp_dfreq[i], i, in svs_status_debug_show()
847 i, svsb->volt[i], i, svsb->freq_pct[i]); in svs_status_debug_show()
879 dev_err(svsp->dev, "cannot create %s: %ld\n", in svs_create_debug_cmds()
889 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", in svs_create_debug_cmds()
895 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_create_debug_cmds()
896 svsb = &svsp->banks[idx]; in svs_create_debug_cmds()
898 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) in svs_create_debug_cmds()
901 svsb_dir = debugfs_create_dir(svsb->name, svs_dir); in svs_create_debug_cmds()
903 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", in svs_create_debug_cmds()
904 d, svsb->name, PTR_ERR(svsb_dir)); in svs_create_debug_cmds()
913 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", in svs_create_debug_cmds()
914 d, svsb->name, svsb_entries[i].name, in svs_create_debug_cmds()
933 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx)); in interpolate()
940 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_get_bank_volts_v3()
941 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; in svs_get_bank_volts_v3()
943 u32 middle_index = (bdata->opp_count / 2); in svs_get_bank_volts_v3()
945 if (svsb->phase == SVSB_PHASE_MON && in svs_get_bank_volts_v3()
946 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) in svs_get_bank_volts_v3()
952 /* Target is to set svsb->volt[] by algorithm */ in svs_get_bank_volts_v3()
954 if (bdata->type == SVSB_TYPE_HIGH) { in svs_get_bank_volts_v3()
955 /* volt[0] ~ volt[turn_pt - 1] */ in svs_get_bank_volts_v3()
960 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
963 } else if (bdata->type == SVSB_TYPE_LOW) { in svs_get_bank_volts_v3()
964 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ in svs_get_bank_volts_v3()
965 j = bdata->opp_count - 7; in svs_get_bank_volts_v3()
966 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); in svs_get_bank_volts_v3()
968 for (i = j; i < bdata->opp_count; i++) { in svs_get_bank_volts_v3()
972 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
976 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */ in svs_get_bank_volts_v3()
978 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt], in svs_get_bank_volts_v3()
979 svsb->freq_pct[j], in svs_get_bank_volts_v3()
980 svsb->volt[turn_pt], in svs_get_bank_volts_v3()
981 svsb->volt[j], in svs_get_bank_volts_v3()
982 svsb->freq_pct[i]); in svs_get_bank_volts_v3()
985 if (bdata->type == SVSB_TYPE_HIGH) { in svs_get_bank_volts_v3()
986 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ in svs_get_bank_volts_v3()
987 j = turn_pt - 7; in svs_get_bank_volts_v3()
988 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); in svs_get_bank_volts_v3()
994 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
998 /* volt[1] ~ volt[j - 1] by interpolate */ in svs_get_bank_volts_v3()
1000 svsb->volt[i] = interpolate(svsb->freq_pct[0], in svs_get_bank_volts_v3()
1001 svsb->freq_pct[j], in svs_get_bank_volts_v3()
1002 svsb->volt[0], in svs_get_bank_volts_v3()
1003 svsb->volt[j], in svs_get_bank_volts_v3()
1004 svsb->freq_pct[i]); in svs_get_bank_volts_v3()
1005 } else if (bdata->type == SVSB_TYPE_LOW) { in svs_get_bank_volts_v3()
1006 /* volt[turn_pt] ~ volt[opp_count - 1] */ in svs_get_bank_volts_v3()
1007 for (i = turn_pt; i < bdata->opp_count; i++) { in svs_get_bank_volts_v3()
1011 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
1017 if (bdata->type == SVSB_TYPE_HIGH) { in svs_get_bank_volts_v3()
1019 opp_stop = svsb->turn_pt; in svs_get_bank_volts_v3()
1020 } else if (bdata->type == SVSB_TYPE_LOW) { in svs_get_bank_volts_v3()
1021 opp_start = svsb->turn_pt; in svs_get_bank_volts_v3()
1022 opp_stop = bdata->opp_count; in svs_get_bank_volts_v3()
1026 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) in svs_get_bank_volts_v3()
1027 svsb->volt[i] -= svsb->dvt_fixed; in svs_get_bank_volts_v3()
1030 if (svsb->opp_dfreq[0] > svsb->freq_base) { in svs_get_bank_volts_v3()
1031 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], in svs_get_bank_volts_v3()
1032 bdata->volt_step, in svs_get_bank_volts_v3()
1033 bdata->volt_base); in svs_get_bank_volts_v3()
1036 for (i = 0; i < bdata->opp_count; i++) { in svs_get_bank_volts_v3()
1037 if (svsb->opp_dfreq[i] <= svsb->freq_base) { in svs_get_bank_volts_v3()
1038 svsb->vbin_turn_pt = i; in svs_get_bank_volts_v3()
1044 for (i = 1; i < svsb->vbin_turn_pt; i++) in svs_get_bank_volts_v3()
1045 svsb->volt[i] = interpolate(svsb->freq_pct[0], in svs_get_bank_volts_v3()
1046 svsb->freq_pct[svsb->vbin_turn_pt], in svs_get_bank_volts_v3()
1047 svsb->volt[0], in svs_get_bank_volts_v3()
1048 svsb->volt[svsb->vbin_turn_pt], in svs_get_bank_volts_v3()
1049 svsb->freq_pct[i]); in svs_get_bank_volts_v3()
1055 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_set_bank_freq_pct_v3()
1058 u32 middle_index = (bdata->opp_count / 2); in svs_set_bank_freq_pct_v3()
1060 for (i = 0; i < bdata->opp_count; i++) { in svs_set_bank_freq_pct_v3()
1061 if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) { in svs_set_bank_freq_pct_v3()
1062 svsb->turn_pt = i; in svs_set_bank_freq_pct_v3()
1067 turn_pt = svsb->turn_pt; in svs_set_bank_freq_pct_v3()
1071 if (bdata->type == SVSB_TYPE_HIGH) { in svs_set_bank_freq_pct_v3()
1078 freq_pct30 = svsb->freq_pct[0]; in svs_set_bank_freq_pct_v3()
1080 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */ in svs_set_bank_freq_pct_v3()
1085 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1088 } else if (bdata->type == SVSB_TYPE_LOW) { in svs_set_bank_freq_pct_v3()
1091 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] in svs_set_bank_freq_pct_v3()
1093 freq_pct30 = svsb->freq_pct[turn_pt]; in svs_set_bank_freq_pct_v3()
1095 j = bdata->opp_count - 7; in svs_set_bank_freq_pct_v3()
1096 for (i = j; i < bdata->opp_count; i++) { in svs_set_bank_freq_pct_v3()
1100 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1105 if (bdata->type == SVSB_TYPE_HIGH) { in svs_set_bank_freq_pct_v3()
1108 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] in svs_set_bank_freq_pct_v3()
1110 freq_pct30 = svsb->freq_pct[0]; in svs_set_bank_freq_pct_v3()
1112 j = turn_pt - 7; in svs_set_bank_freq_pct_v3()
1117 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1120 } else if (bdata->type == SVSB_TYPE_LOW) { in svs_set_bank_freq_pct_v3()
1121 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ in svs_set_bank_freq_pct_v3()
1122 for (i = turn_pt; i < bdata->opp_count; i++) { in svs_set_bank_freq_pct_v3()
1126 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1138 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_get_bank_volts_v2()
1142 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); in svs_get_bank_volts_v2()
1143 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); in svs_get_bank_volts_v2()
1144 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); in svs_get_bank_volts_v2()
1145 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); in svs_get_bank_volts_v2()
1148 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); in svs_get_bank_volts_v2()
1149 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); in svs_get_bank_volts_v2()
1150 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); in svs_get_bank_volts_v2()
1151 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); in svs_get_bank_volts_v2()
1154 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i], in svs_get_bank_volts_v2()
1155 svsb->freq_pct[i + 2], in svs_get_bank_volts_v2()
1156 svsb->volt[i], in svs_get_bank_volts_v2()
1157 svsb->volt[i + 2], in svs_get_bank_volts_v2()
1158 svsb->freq_pct[i + 1]); in svs_get_bank_volts_v2()
1160 svsb->volt[15] = interpolate(svsb->freq_pct[12], in svs_get_bank_volts_v2()
1161 svsb->freq_pct[14], in svs_get_bank_volts_v2()
1162 svsb->volt[12], in svs_get_bank_volts_v2()
1163 svsb->volt[14], in svs_get_bank_volts_v2()
1164 svsb->freq_pct[15]); in svs_get_bank_volts_v2()
1166 for (i = 0; i < bdata->opp_count; i++) in svs_get_bank_volts_v2()
1167 svsb->volt[i] += svsb->volt_od; in svs_get_bank_volts_v2()
1170 if (svsb->opp_dfreq[0] > svsb->freq_base) { in svs_get_bank_volts_v2()
1171 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], in svs_get_bank_volts_v2()
1172 bdata->volt_step, in svs_get_bank_volts_v2()
1173 bdata->volt_base); in svs_get_bank_volts_v2()
1176 for (i = 0; i < bdata->opp_count; i++) { in svs_get_bank_volts_v2()
1177 if (svsb->opp_dfreq[i] <= svsb->freq_base) { in svs_get_bank_volts_v2()
1178 svsb->vbin_turn_pt = i; in svs_get_bank_volts_v2()
1184 for (i = 1; i < svsb->vbin_turn_pt; i++) in svs_get_bank_volts_v2()
1185 svsb->volt[i] = interpolate(svsb->freq_pct[0], in svs_get_bank_volts_v2()
1186 svsb->freq_pct[svsb->vbin_turn_pt], in svs_get_bank_volts_v2()
1187 svsb->volt[0], in svs_get_bank_volts_v2()
1188 svsb->volt[svsb->vbin_turn_pt], in svs_get_bank_volts_v2()
1189 svsb->freq_pct[i]); in svs_get_bank_volts_v2()
1197 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | in svs_set_bank_freq_pct_v2()
1198 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) | in svs_set_bank_freq_pct_v2()
1199 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) | in svs_set_bank_freq_pct_v2()
1200 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]); in svs_set_bank_freq_pct_v2()
1202 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) | in svs_set_bank_freq_pct_v2()
1203 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) | in svs_set_bank_freq_pct_v2()
1204 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) | in svs_set_bank_freq_pct_v2()
1205 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]); in svs_set_bank_freq_pct_v2()
1215 struct svs_bank *svsb = &svsp->banks[bank_idx]; in svs_set_bank_phase()
1216 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_set_bank_phase()
1221 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | in svs_set_bank_phase()
1222 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); in svs_set_bank_phase()
1225 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) | in svs_set_bank_phase()
1226 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | in svs_set_bank_phase()
1227 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); in svs_set_bank_phase()
1230 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) | in svs_set_bank_phase()
1231 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); in svs_set_bank_phase()
1234 svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG); in svs_set_bank_phase()
1235 svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG); in svs_set_bank_phase()
1238 bdata->set_freq_pct(svsp, svsb); in svs_set_bank_phase()
1242 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) | in svs_set_bank_phase()
1243 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax); in svs_set_bank_phase()
1248 svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT); in svs_set_bank_phase()
1249 svs_writel_relaxed(svsp, bdata->ctl0, CTL0); in svs_set_bank_phase()
1254 svs_writel_relaxed(svsp, bdata->vboot, VBOOT); in svs_set_bank_phase()
1259 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) | in svs_set_bank_phase()
1260 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in); in svs_set_bank_phase()
1266 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) | in svs_set_bank_phase()
1267 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts); in svs_set_bank_phase()
1273 dev_err(svsb->dev, "requested unknown target phase: %u\n", in svs_set_bank_phase()
1283 struct svs_bank *svsb = &svsp->banks[bank_idx]; in svs_save_bank_register_data()
1287 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); in svs_save_bank_register_data()
1293 struct svs_bank *svsb = &svsp->banks[bank_idx]; in svs_error_isr_handler()
1295 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", in svs_error_isr_handler()
1297 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n", in svs_error_isr_handler()
1300 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n", in svs_error_isr_handler()
1303 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); in svs_error_isr_handler()
1307 svsb->phase = SVSB_PHASE_ERROR; in svs_error_isr_handler()
1315 struct svs_bank *svsb = &svsp->banks[bank_idx]; in svs_init01_isr_handler()
1318 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", in svs_init01_isr_handler()
1325 svsb->phase = SVSB_PHASE_INIT01; in svs_init01_isr_handler()
1327 svsb->dc_voffset_in = val & GENMASK(15, 0); in svs_init01_isr_handler()
1328 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || in svs_init01_isr_handler()
1329 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && in svs_init01_isr_handler()
1330 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) in svs_init01_isr_handler()
1331 svsb->dc_voffset_in = 0; in svs_init01_isr_handler()
1333 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) & in svs_init01_isr_handler()
1338 svsb->core_sel &= ~SVSB_DET_CLK_EN; in svs_init01_isr_handler()
1344 struct svs_bank *svsb = &svsp->banks[bank_idx]; in svs_init02_isr_handler()
1345 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_init02_isr_handler()
1347 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", in svs_init02_isr_handler()
1354 svsb->phase = SVSB_PHASE_INIT02; in svs_init02_isr_handler()
1355 bdata->get_volts(svsp, svsb); in svs_init02_isr_handler()
1364 struct svs_bank *svsb = &svsp->banks[bank_idx]; in svs_mon_mode_isr_handler()
1365 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_mon_mode_isr_handler()
1369 svsb->phase = SVSB_PHASE_MON; in svs_mon_mode_isr_handler()
1370 bdata->get_volts(svsp, svsb); in svs_mon_mode_isr_handler()
1372 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); in svs_mon_mode_isr_handler()
1384 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_isr()
1385 svsb = &svsp->banks[idx]; in svs_isr()
1386 bdata = &svsb->pdata; in svs_isr()
1387 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); in svs_isr()
1392 if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) { in svs_isr()
1418 if (svsb->phase == SVSB_PHASE_INIT01 || in svs_isr()
1419 svsb->phase == SVSB_PHASE_INIT02) in svs_isr()
1420 complete(&svsb->init_completion); in svs_isr()
1429 for (i = 0; i < svsp->bank_max; i++) in svs_mode_available()
1430 if (svsp->banks[i].mode_support & mode) in svs_mode_available()
1450 /* Svs bank init01 preparation - power enable */ in svs_init01()
1451 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1452 svsb = &svsp->banks[idx]; in svs_init01()
1453 bdata = &svsb->pdata; in svs_init01()
1455 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1458 ret = regulator_enable(svsb->buck); in svs_init01()
1460 dev_err(svsb->dev, "%s enable fail: %d\n", in svs_init01()
1461 bdata->buck_name, ret); in svs_init01()
1466 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST); in svs_init01()
1468 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret); in svs_init01()
1470 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { in svs_init01()
1471 if (!pm_runtime_enabled(svsb->opp_dev)) { in svs_init01()
1472 pm_runtime_enable(svsb->opp_dev); in svs_init01()
1473 svsb->pm_runtime_enabled_count++; in svs_init01()
1476 ret = pm_runtime_resume_and_get(svsb->opp_dev); in svs_init01()
1478 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); in svs_init01()
1485 * Svs bank init01 preparation - vboot voltage adjustment in svs_init01()
1489 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1490 svsb = &svsp->banks[idx]; in svs_init01()
1491 bdata = &svsb->pdata; in svs_init01()
1493 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1501 opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, in svs_init01()
1502 bdata->volt_step, in svs_init01()
1503 bdata->volt_base); in svs_init01()
1505 for (i = 0; i < bdata->opp_count; i++) { in svs_init01()
1506 opp_freq = svsb->opp_dfreq[i]; in svs_init01()
1507 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { in svs_init01()
1508 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, in svs_init01()
1514 dev_err(svsb->dev, in svs_init01()
1522 ret = dev_pm_opp_disable(svsb->opp_dev, in svs_init01()
1523 svsb->opp_dfreq[i]); in svs_init01()
1525 dev_err(svsb->dev, in svs_init01()
1527 svsb->opp_dfreq[i], ret); in svs_init01()
1535 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1536 svsb = &svsp->banks[idx]; in svs_init01()
1537 bdata = &svsb->pdata; in svs_init01()
1539 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1542 opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, in svs_init01()
1543 bdata->volt_step, in svs_init01()
1544 bdata->volt_base); in svs_init01()
1546 buck_volt = regulator_get_voltage(svsb->buck); in svs_init01()
1548 dev_err(svsb->dev, in svs_init01()
1551 ret = -EPERM; in svs_init01()
1559 time_left = wait_for_completion_timeout(&svsb->init_completion, in svs_init01()
1562 dev_err(svsb->dev, "init01 completion timeout\n"); in svs_init01()
1563 ret = -EBUSY; in svs_init01()
1569 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1570 svsb = &svsp->banks[idx]; in svs_init01()
1571 bdata = &svsb->pdata; in svs_init01()
1573 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1576 for (i = 0; i < bdata->opp_count; i++) { in svs_init01()
1577 r = dev_pm_opp_enable(svsb->opp_dev, in svs_init01()
1578 svsb->opp_dfreq[i]); in svs_init01()
1580 dev_err(svsb->dev, "opp %uHz enable fail: %d\n", in svs_init01()
1581 svsb->opp_dfreq[i], r); in svs_init01()
1584 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { in svs_init01()
1585 r = pm_runtime_put_sync(svsb->opp_dev); in svs_init01()
1587 dev_err(svsb->dev, "mtcmos off fail: %d\n", r); in svs_init01()
1589 if (svsb->pm_runtime_enabled_count > 0) { in svs_init01()
1590 pm_runtime_disable(svsb->opp_dev); in svs_init01()
1591 svsb->pm_runtime_enabled_count--; in svs_init01()
1595 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL); in svs_init01()
1597 dev_notice(svsb->dev, "set normal mode fail: %d\n", r); in svs_init01()
1599 r = regulator_disable(svsb->buck); in svs_init01()
1601 dev_err(svsb->dev, "%s disable fail: %d\n", in svs_init01()
1602 bdata->buck_name, r); in svs_init01()
1622 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1623 svsb = &svsp->banks[idx]; in svs_init02()
1625 if (!(svsb->mode_support & SVSB_MODE_INIT02)) in svs_init02()
1628 reinit_completion(&svsb->init_completion); in svs_init02()
1633 time_left = wait_for_completion_timeout(&svsb->init_completion, in svs_init02()
1636 dev_err(svsb->dev, "init02 completion timeout\n"); in svs_init02()
1637 ret = -EBUSY; in svs_init02()
1643 * 2-line high/low bank update its corresponding opp voltages only. in svs_init02()
1647 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1648 svsb = &svsp->banks[idx]; in svs_init02()
1649 bdata = &svsb->pdata; in svs_init02()
1651 if (!(svsb->mode_support & SVSB_MODE_INIT02)) in svs_init02()
1654 if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) { in svs_init02()
1656 dev_err(svsb->dev, "sync volt fail\n"); in svs_init02()
1657 ret = -EPERM; in svs_init02()
1666 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1667 svsb = &svsp->banks[idx]; in svs_init02()
1680 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mon_mode()
1681 svsb = &svsp->banks[idx]; in svs_mon_mode()
1683 if (!(svsb->mode_support & SVSB_MODE_MON)) in svs_mon_mode()
1715 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_suspend()
1716 struct svs_bank *svsb = &svsp->banks[idx]; in svs_suspend()
1721 ret = reset_control_assert(svsp->rst); in svs_suspend()
1723 dev_err(svsp->dev, "cannot assert reset %d\n", ret); in svs_suspend()
1727 clk_disable_unprepare(svsp->main_clk); in svs_suspend()
1737 ret = clk_prepare_enable(svsp->main_clk); in svs_resume()
1739 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); in svs_resume()
1743 ret = reset_control_deassert(svsp->rst); in svs_resume()
1745 dev_err(svsp->dev, "cannot deassert reset %d\n", ret); in svs_resume()
1758 dev_err(svsp->dev, "assert reset: %d\n", in svs_resume()
1759 reset_control_assert(svsp->rst)); in svs_resume()
1762 clk_disable_unprepare(svsp->main_clk); in svs_resume()
1776 dev_set_drvdata(svsp->dev, svsp); in svs_bank_resource_setup()
1778 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_bank_resource_setup()
1779 svsb = &svsp->banks[idx]; in svs_bank_resource_setup()
1780 bdata = &svsb->pdata; in svs_bank_resource_setup()
1782 if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) { in svs_bank_resource_setup()
1783 dev_err(svsb->dev, "unknown bank sw_id or type\n"); in svs_bank_resource_setup()
1784 return -EINVAL; in svs_bank_resource_setup()
1787 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL); in svs_bank_resource_setup()
1788 if (!svsb->dev) in svs_bank_resource_setup()
1789 return -ENOMEM; in svs_bank_resource_setup()
1791 svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s", in svs_bank_resource_setup()
1792 svs_swid_names[bdata->sw_id], in svs_bank_resource_setup()
1793 svs_type_names[bdata->type]); in svs_bank_resource_setup()
1794 if (!svsb->name) in svs_bank_resource_setup()
1795 return -ENOMEM; in svs_bank_resource_setup()
1797 ret = dev_set_name(svsb->dev, "%s", svsb->name); in svs_bank_resource_setup()
1801 dev_set_drvdata(svsb->dev, svsp); in svs_bank_resource_setup()
1803 ret = devm_pm_opp_of_add_table(svsb->opp_dev); in svs_bank_resource_setup()
1805 dev_err(svsb->dev, "add opp table fail: %d\n", ret); in svs_bank_resource_setup()
1809 mutex_init(&svsb->lock); in svs_bank_resource_setup()
1810 init_completion(&svsb->init_completion); in svs_bank_resource_setup()
1812 if (svsb->mode_support & SVSB_MODE_INIT01) { in svs_bank_resource_setup()
1813 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, in svs_bank_resource_setup()
1814 bdata->buck_name); in svs_bank_resource_setup()
1815 if (IS_ERR(svsb->buck)) { in svs_bank_resource_setup()
1816 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", in svs_bank_resource_setup()
1817 bdata->buck_name); in svs_bank_resource_setup()
1818 return PTR_ERR(svsb->buck); in svs_bank_resource_setup()
1822 if (!IS_ERR_OR_NULL(bdata->tzone_name)) { in svs_bank_resource_setup()
1824 "%s-thermal", bdata->tzone_name); in svs_bank_resource_setup()
1825 svsb->tzd = thermal_zone_get_zone_by_name(tz_name_buf); in svs_bank_resource_setup()
1826 if (IS_ERR(svsb->tzd)) { in svs_bank_resource_setup()
1827 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", in svs_bank_resource_setup()
1829 return PTR_ERR(svsb->tzd); in svs_bank_resource_setup()
1833 count = dev_pm_opp_get_opp_count(svsb->opp_dev); in svs_bank_resource_setup()
1834 if (bdata->opp_count != count) { in svs_bank_resource_setup()
1835 dev_err(svsb->dev, in svs_bank_resource_setup()
1837 bdata->opp_count, count); in svs_bank_resource_setup()
1841 for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) { in svs_bank_resource_setup()
1842 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); in svs_bank_resource_setup()
1844 dev_err(svsb->dev, "cannot find freq = %ld\n", in svs_bank_resource_setup()
1849 svsb->opp_dfreq[i] = freq; in svs_bank_resource_setup()
1850 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp); in svs_bank_resource_setup()
1851 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i], in svs_bank_resource_setup()
1852 svsb->freq_base); in svs_bank_resource_setup()
1866 cell = nvmem_cell_get(svsp->dev, nvmem_cell_name); in svs_get_efuse_data()
1868 dev_err(svsp->dev, "no \"%s\"? %ld\n", in svs_get_efuse_data()
1889 if (fmap->index < 0) in svs_get_fuse_val()
1892 val = fuse_array[fmap->index] >> fmap->ofst; in svs_get_fuse_val()
1893 val &= GENMASK(nbits - 1, 0); in svs_get_fuse_val()
1903 for (i = 0; i < svsp->efuse_max; i++) { in svs_is_available()
1904 if (svsp->efuse[i]) in svs_is_available()
1917 const struct svs_fusemap *gfmap = pdata->glb_fuse_map; in svs_common_parse_efuse()
1926 /* Get golden temperature from SVS-Thermal calibration */ in svs_common_parse_efuse()
1927 val = svs_get_fuse_val(svsp->tefuse, &tfm, 8); in svs_common_parse_efuse()
1933 ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8); in svs_common_parse_efuse()
1934 vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2); in svs_common_parse_efuse()
1936 for (i = 0; i < svsp->bank_max; i++) { in svs_common_parse_efuse()
1937 struct svs_bank *svsb = &svsp->banks[i]; in svs_common_parse_efuse()
1938 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_common_parse_efuse()
1939 const struct svs_fusemap *dfmap = bdata->dev_fuse_map; in svs_common_parse_efuse()
1942 svsb->vmin = 0x1e; in svs_common_parse_efuse()
1945 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; in svs_common_parse_efuse()
1947 svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); in svs_common_parse_efuse()
1948 svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); in svs_common_parse_efuse()
1949 svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); in svs_common_parse_efuse()
1950 svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); in svs_common_parse_efuse()
1951 svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); in svs_common_parse_efuse()
1952 svsb->vmax += svsb->dvt_fixed; in svs_common_parse_efuse()
1954 svsb->mts = (svsp->ts_coeff * 2) / 1000; in svs_common_parse_efuse()
1955 svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4; in svs_common_parse_efuse()
1971 for (i = 0; i < svsp->efuse_max; i++) in svs_mt8183_efuse_parsing()
1972 if (svsp->efuse[i]) in svs_mt8183_efuse_parsing()
1973 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", in svs_mt8183_efuse_parsing()
1974 i, svsp->efuse[i]); in svs_mt8183_efuse_parsing()
1976 if (!svsp->efuse[2]) { in svs_mt8183_efuse_parsing()
1977 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n"); in svs_mt8183_efuse_parsing()
1981 /* Svs efuse parsing */ in svs_mt8183_efuse_parsing()
1982 ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4); in svs_mt8183_efuse_parsing()
1984 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
1985 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
1986 bdata = &svsb->pdata; in svs_mt8183_efuse_parsing()
1987 const struct svs_fusemap *dfmap = bdata->dev_fuse_map; in svs_mt8183_efuse_parsing()
1990 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; in svs_mt8183_efuse_parsing()
1992 svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); in svs_mt8183_efuse_parsing()
1993 svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); in svs_mt8183_efuse_parsing()
1994 svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); in svs_mt8183_efuse_parsing()
1995 svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); in svs_mt8183_efuse_parsing()
1996 svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); in svs_mt8183_efuse_parsing()
1998 switch (bdata->sw_id) { in svs_mt8183_efuse_parsing()
2002 svsb->volt_od += 10; in svs_mt8183_efuse_parsing()
2004 svsb->volt_od += 2; in svs_mt8183_efuse_parsing()
2008 svsb->volt_od += 15; in svs_mt8183_efuse_parsing()
2010 svsb->volt_od += 12; in svs_mt8183_efuse_parsing()
2014 svsb->freq_base = 800000000; /* 800MHz */ in svs_mt8183_efuse_parsing()
2015 svsb->dvt_fixed = 2; in svs_mt8183_efuse_parsing()
2019 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); in svs_mt8183_efuse_parsing()
2024 /* Thermal efuse parsing */ in svs_mt8183_efuse_parsing()
2025 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); in svs_mt8183_efuse_parsing()
2026 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); in svs_mt8183_efuse_parsing()
2028 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
2029 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
2030 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
2031 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
2032 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
2033 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
2035 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0); in svs_mt8183_efuse_parsing()
2036 adc_cali_en_t = svsp->tefuse[0] & BIT(0); in svs_mt8183_efuse_parsing()
2037 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); in svs_mt8183_efuse_parsing()
2039 ts_id = (svsp->tefuse[1] >> 9) & BIT(0); in svs_mt8183_efuse_parsing()
2043 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); in svs_mt8183_efuse_parsing()
2047 o_slope = 1534 - o_slope * 10; in svs_mt8183_efuse_parsing()
2053 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || in svs_mt8183_efuse_parsing()
2054 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || in svs_mt8183_efuse_parsing()
2055 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || in svs_mt8183_efuse_parsing()
2056 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || in svs_mt8183_efuse_parsing()
2057 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || in svs_mt8183_efuse_parsing()
2058 o_vtsabb < -8 || o_vtsabb > 484 || in svs_mt8183_efuse_parsing()
2060 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); in svs_mt8183_efuse_parsing()
2064 ge = ((adc_ge_t - 512) * 10000) / 4096; in svs_mt8183_efuse_parsing()
2065 oe = (adc_oe_t - 512); in svs_mt8183_efuse_parsing()
2068 format[0] = (o_vtsmcu[0] + 3350 - oe); in svs_mt8183_efuse_parsing()
2069 format[1] = (o_vtsmcu[1] + 3350 - oe); in svs_mt8183_efuse_parsing()
2070 format[2] = (o_vtsmcu[2] + 3350 - oe); in svs_mt8183_efuse_parsing()
2071 format[3] = (o_vtsmcu[3] + 3350 - oe); in svs_mt8183_efuse_parsing()
2072 format[4] = (o_vtsmcu[4] + 3350 - oe); in svs_mt8183_efuse_parsing()
2073 format[5] = (o_vtsabb + 3350 - oe); in svs_mt8183_efuse_parsing()
2081 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
2082 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
2083 bdata = &svsb->pdata; in svs_mt8183_efuse_parsing()
2084 svsb->mts = mts; in svs_mt8183_efuse_parsing()
2086 switch (bdata->sw_id) { in svs_mt8183_efuse_parsing()
2100 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); in svs_mt8183_efuse_parsing()
2109 svsb->bts = (temp0 + temp2 - 250) * 4 / 10; in svs_mt8183_efuse_parsing()
2115 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
2116 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
2117 svsb->mode_support &= ~SVSB_MODE_MON; in svs_mt8183_efuse_parsing()
2131 dev_err(svsp->dev, "cannot find %s node\n", node_name); in svs_get_subsys_device()
2132 return ERR_PTR(-ENODEV); in svs_get_subsys_device()
2138 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name); in svs_get_subsys_device()
2139 return ERR_PTR(-ENXIO); in svs_get_subsys_device()
2144 return &pdev->dev; in svs_get_subsys_device()
2157 sup_link = device_link_add(svsp->dev, dev, in svs_add_device_link()
2160 dev_err(svsp->dev, "sup_link is NULL\n"); in svs_add_device_link()
2161 return ERR_PTR(-EINVAL); in svs_add_device_link()
2164 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) in svs_add_device_link()
2165 return ERR_PTR(-EPROBE_DEFER); in svs_add_device_link()
2175 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); in svs_mt8192_platform_probe()
2176 if (IS_ERR(svsp->rst)) in svs_mt8192_platform_probe()
2177 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), in svs_mt8192_platform_probe()
2180 dev = svs_add_device_link(svsp, "thermal-sensor"); in svs_mt8192_platform_probe()
2182 return dev_err_probe(svsp->dev, PTR_ERR(dev), in svs_mt8192_platform_probe()
2185 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8192_platform_probe()
2186 struct svs_bank *svsb = &svsp->banks[idx]; in svs_mt8192_platform_probe()
2187 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_mt8192_platform_probe()
2189 switch (bdata->sw_id) { in svs_mt8192_platform_probe()
2192 svsb->opp_dev = get_cpu_device(bdata->cpu_id); in svs_mt8192_platform_probe()
2195 svsb->opp_dev = svs_add_device_link(svsp, "cci"); in svs_mt8192_platform_probe()
2198 if (bdata->type == SVSB_TYPE_LOW) in svs_mt8192_platform_probe()
2199 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); in svs_mt8192_platform_probe()
2201 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); in svs_mt8192_platform_probe()
2204 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); in svs_mt8192_platform_probe()
2205 return -EINVAL; in svs_mt8192_platform_probe()
2208 if (IS_ERR(svsb->opp_dev)) in svs_mt8192_platform_probe()
2209 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), in svs_mt8192_platform_probe()
2222 dev = svs_add_device_link(svsp, "thermal-sensor"); in svs_mt8183_platform_probe()
2224 return dev_err_probe(svsp->dev, PTR_ERR(dev), in svs_mt8183_platform_probe()
2227 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_platform_probe()
2228 struct svs_bank *svsb = &svsp->banks[idx]; in svs_mt8183_platform_probe()
2229 const struct svs_bank_pdata *bdata = &svsb->pdata; in svs_mt8183_platform_probe()
2231 switch (bdata->sw_id) { in svs_mt8183_platform_probe()
2234 svsb->opp_dev = get_cpu_device(bdata->cpu_id); in svs_mt8183_platform_probe()
2237 svsb->opp_dev = svs_add_device_link(svsp, "cci"); in svs_mt8183_platform_probe()
2240 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); in svs_mt8183_platform_probe()
2243 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); in svs_mt8183_platform_probe()
2244 return -EINVAL; in svs_mt8183_platform_probe()
2247 if (IS_ERR(svsb->opp_dev)) in svs_mt8183_platform_probe()
2248 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), in svs_mt8183_platform_probe()
2491 .tzone_name = "cpu-big",
2525 .tzone_name = "cpu-little",
2742 .name = "mt8195-svs",
2755 .name = "mt8192-svs",
2764 { -1, 0 }, { 19, 4 }
2769 .name = "mt8188-svs",
2778 { -1, 0 }, { -1, 0 }
2783 .name = "mt8186-svs",
2792 { -1, 0 }, { -1, 0 }
2797 .name = "mt8183-svs",
2805 { 0, 4 }, { -1, 0 }
2810 { .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data },
2811 { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data },
2812 { .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data },
2813 { .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data },
2814 { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data },
2825 svsp_data = of_device_get_match_data(&pdev->dev); in svs_probe()
2827 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); in svs_probe()
2829 return -ENOMEM; in svs_probe()
2831 svsp->dev = &pdev->dev; in svs_probe()
2832 svsp->banks = svsp_data->banks; in svs_probe()
2833 svsp->regs = svsp_data->regs; in svs_probe()
2834 svsp->bank_max = svsp_data->bank_max; in svs_probe()
2835 svsp->ts_coeff = svsp_data->ts_coeff; in svs_probe()
2837 ret = svsp_data->probe(svsp); in svs_probe()
2841 ret = svs_get_efuse_data(svsp, "svs-calibration-data", in svs_probe()
2842 &svsp->efuse, &svsp->efuse_max); in svs_probe()
2844 return dev_err_probe(&pdev->dev, ret, "Cannot read SVS calibration\n"); in svs_probe()
2846 ret = svs_get_efuse_data(svsp, "t-calibration-data", in svs_probe()
2847 &svsp->tefuse, &svsp->tefuse_max); in svs_probe()
2849 dev_err_probe(&pdev->dev, ret, "Cannot read SVS-Thermal calibration\n"); in svs_probe()
2853 if (!svsp_data->efuse_parsing(svsp, svsp_data)) { in svs_probe()
2854 ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n"); in svs_probe()
2860 dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n"); in svs_probe()
2870 svsp->main_clk = devm_clk_get(svsp->dev, "main"); in svs_probe()
2871 if (IS_ERR(svsp->main_clk)) { in svs_probe()
2872 ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk), in svs_probe()
2877 ret = clk_prepare_enable(svsp->main_clk); in svs_probe()
2879 dev_err_probe(svsp->dev, ret, "cannot enable main clk\n"); in svs_probe()
2883 svsp->base = of_iomap(svsp->dev->of_node, 0); in svs_probe()
2884 if (IS_ERR_OR_NULL(svsp->base)) { in svs_probe()
2885 ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n"); in svs_probe()
2889 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, in svs_probe()
2890 IRQF_ONESHOT, svsp_data->name, svsp); in svs_probe()
2892 dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq); in svs_probe()
2898 dev_err_probe(svsp->dev, ret, "svs start fail\n"); in svs_probe()
2905 dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n"); in svs_probe()
2913 iounmap(svsp->base); in svs_probe()
2915 clk_disable_unprepare(svsp->main_clk); in svs_probe()
2917 kfree(svsp->tefuse); in svs_probe()
2919 kfree(svsp->efuse); in svs_probe()
2928 .name = "mtk-svs",