Lines Matching +full:mt8135 +full:- +full:pwrap
1 // SPDX-License-Identifier: GPL-2.0-only
79 /* Group of bits used for shown pwrap capability */
425 /* MT8135 only regs */
1337 * pwrap operations are highly associated with the PMIC types,
1346 * struct pwrap_slv_type - PMIC device wrapper definitions
1383 /* Flags indicating the capability for the target pwrap */
1391 return readl(wrp->base + wrp->master->regs[reg]); in pwrap_readl()
1396 writel(val, wrp->base + wrp->master->regs[reg]); in pwrap_writel()
1404 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_get_fsm_state()
1460 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_read16()
1471 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_read16()
1516 return wrp->slave->regops->pwrap_read(wrp, adr, rdata); in pwrap_read()
1531 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { in pwrap_write16()
1561 * for the synchronization between two successive 16-bit in pwrap_write32()
1562 * pwrap_writel operations composing one 32-bit bus writing. in pwrap_write32()
1563 * Otherwise, we'll find the result fails on the lower 16-bit in pwrap_write32()
1564 * pwrap writing. in pwrap_write32()
1575 return wrp->slave->regops->pwrap_write(wrp, adr, wdata); in pwrap_write()
1611 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, in pwrap_reset_spislave()
1613 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, in pwrap_reset_spislave()
1615 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, in pwrap_reset_spislave()
1619 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, in pwrap_reset_spislave()
1625 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); in pwrap_reset_spislave()
1636 * pwrap_init_sidly - configure serial input delay
1647 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 in pwrap_init_sidly()
1652 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, in pwrap_init_sidly()
1655 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); in pwrap_init_sidly()
1661 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", in pwrap_init_sidly()
1663 return -EIO; in pwrap_init_sidly()
1678 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); in pwrap_init_dual_io()
1679 if (wrp->slave->comp_dew_regs) in pwrap_init_dual_io()
1680 pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1); in pwrap_init_dual_io()
1686 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); in pwrap_init_dual_io()
1693 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL); in pwrap_init_dual_io()
1694 if (wrp->slave->comp_dew_regs) in pwrap_init_dual_io()
1695 comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs, in pwrap_init_dual_io()
1698 dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n", in pwrap_init_dual_io()
1700 wrp->slave->comp_dew_regs && !comp_read_ok ? in pwrap_init_dual_io()
1702 return -EFAULT; in pwrap_init_dual_io()
1710 * phase during data transactions on the pwrap bus.
1735 switch (wrp->master->type) { in pwrap_common_init_reg_clock()
1737 if (wrp->slave->type == PMIC_MT6331) { in pwrap_common_init_reg_clock()
1738 const u32 *dew_regs = wrp->slave->dew_regs; in pwrap_common_init_reg_clock()
1742 if (wrp->slave->comp_type == PMIC_MT6332) { in pwrap_common_init_reg_clock()
1743 dew_regs = wrp->slave->comp_dew_regs; in pwrap_common_init_reg_clock()
1766 switch (wrp->slave->type) { in pwrap_mt2701_init_reg_clock()
1774 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], in pwrap_mt2701_init_reg_clock()
1805 bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs); in pwrap_is_pmic_cipher_ready()
1811 if (wrp->slave->comp_dew_regs) in pwrap_is_pmic_cipher_ready()
1812 ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs); in pwrap_is_pmic_cipher_ready()
1836 switch (wrp->master->type) { in pwrap_init_cipher()
1862 pwrap_config_cipher(wrp, wrp->slave->dew_regs); in pwrap_init_cipher()
1865 if (wrp->slave->comp_type > 0) in pwrap_init_cipher()
1866 pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); in pwrap_init_cipher()
1868 switch (wrp->slave->type) { in pwrap_init_cipher()
1870 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], in pwrap_init_cipher()
1872 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], in pwrap_init_cipher()
1878 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], in pwrap_init_cipher()
1889 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret); in pwrap_init_cipher()
1897 dev_err(wrp->dev, in pwrap_init_cipher()
1903 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1); in pwrap_init_cipher()
1907 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret); in pwrap_init_cipher()
1914 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], in pwrap_init_cipher()
1916 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], in pwrap_init_cipher()
1919 dev_err(wrp->dev, "rdata=0x%04X\n", rdata); in pwrap_init_cipher()
1920 return -EFAULT; in pwrap_init_cipher()
1936 /* Signature checking - using CRC */ in pwrap_init_security()
1937 ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); in pwrap_init_security()
1938 if (ret == 0 && wrp->slave->comp_dew_regs) in pwrap_init_security()
1939 ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1); in pwrap_init_security()
1945 crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL]; in pwrap_init_security()
1946 if (wrp->slave->comp_dew_regs) in pwrap_init_security()
1947 crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16; in pwrap_init_security()
1953 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); in pwrap_init_security()
1960 /* enable pwrap events and pwrap bridge in AP side */ in pwrap_mt8135_init_soc_specific()
1963 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); in pwrap_mt8135_init_soc_specific()
1964 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); in pwrap_mt8135_init_soc_specific()
1965 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); in pwrap_mt8135_init_soc_specific()
1966 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); in pwrap_mt8135_init_soc_specific()
1967 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); in pwrap_mt8135_init_soc_specific()
1968 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); in pwrap_mt8135_init_soc_specific()
1969 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); in pwrap_mt8135_init_soc_specific()
1972 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], in pwrap_mt8135_init_soc_specific()
1974 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], in pwrap_mt8135_init_soc_specific()
1976 dev_err(wrp->dev, "enable dewrap fail\n"); in pwrap_mt8135_init_soc_specific()
1977 return -EFAULT; in pwrap_mt8135_init_soc_specific()
1986 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], in pwrap_mt8173_init_soc_specific()
1988 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], in pwrap_mt8173_init_soc_specific()
1990 dev_err(wrp->dev, "enable dewrap fail\n"); in pwrap_mt8173_init_soc_specific()
1991 return -EFAULT; in pwrap_mt8173_init_soc_specific()
2000 switch (wrp->slave->type) { in pwrap_mt2701_init_soc_specific()
2019 if (wrp->slave->type == PMIC_MT6331) in pwrap_mt6795_init_soc_specific()
2022 if (wrp->slave->comp_type == PMIC_MT6332) in pwrap_mt6795_init_soc_specific()
2041 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); in pwrap_mt8183_init_soc_specific()
2058 if (wrp->rstc) in pwrap_init()
2059 reset_control_reset(wrp->rstc); in pwrap_init()
2060 if (wrp->rstc_bridge) in pwrap_init()
2061 reset_control_reset(wrp->rstc_bridge); in pwrap_init()
2063 switch (wrp->master->type) { in pwrap_init()
2075 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { in pwrap_init()
2084 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); in pwrap_init()
2088 ret = wrp->master->init_reg_clock(wrp); in pwrap_init()
2092 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { in pwrap_init()
2099 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { in pwrap_init()
2106 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) { in pwrap_init()
2113 if (wrp->master->type == PWRAP_MT8135) in pwrap_init()
2122 if (wrp->master->init_soc_specific) { in pwrap_init()
2123 ret = wrp->master->init_soc_specific(wrp); in pwrap_init()
2133 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { in pwrap_init()
2134 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); in pwrap_init()
2135 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); in pwrap_init()
2147 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata); in pwrap_interrupt()
2150 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) { in pwrap_interrupt()
2152 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata); in pwrap_interrupt()
2261 { .compatible = "mediatek,mt6380-regulator", .data = &pmic_mt6380 },
2448 { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },
2449 { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },
2450 { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },
2451 { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 },
2452 { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 },
2453 { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 },
2454 { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 },
2455 { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 },
2456 { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 },
2457 { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 },
2458 { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 },
2459 { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 },
2460 { .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 },
2461 { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 },
2472 struct device_node *np = pdev->dev.of_node; in pwrap_probe()
2475 if (np->child) in pwrap_probe()
2476 of_slave_id = of_match_node(of_slave_match_tbl, np->child); in pwrap_probe()
2479 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n"); in pwrap_probe()
2480 return -EINVAL; in pwrap_probe()
2483 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL); in pwrap_probe()
2485 return -ENOMEM; in pwrap_probe()
2489 wrp->master = of_device_get_match_data(&pdev->dev); in pwrap_probe()
2490 wrp->slave = of_slave_id->data; in pwrap_probe()
2491 wrp->dev = &pdev->dev; in pwrap_probe()
2493 wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap"); in pwrap_probe()
2494 if (IS_ERR(wrp->base)) in pwrap_probe()
2495 return PTR_ERR(wrp->base); in pwrap_probe()
2497 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) { in pwrap_probe()
2498 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap"); in pwrap_probe()
2499 if (IS_ERR(wrp->rstc)) { in pwrap_probe()
2500 ret = PTR_ERR(wrp->rstc); in pwrap_probe()
2501 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret); in pwrap_probe()
2506 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { in pwrap_probe()
2507 wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge"); in pwrap_probe()
2508 if (IS_ERR(wrp->bridge_base)) in pwrap_probe()
2509 return PTR_ERR(wrp->bridge_base); in pwrap_probe()
2511 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, in pwrap_probe()
2512 "pwrap-bridge"); in pwrap_probe()
2513 if (IS_ERR(wrp->rstc_bridge)) { in pwrap_probe()
2514 ret = PTR_ERR(wrp->rstc_bridge); in pwrap_probe()
2515 dev_dbg(wrp->dev, in pwrap_probe()
2516 "cannot get pwrap-bridge reset: %d\n", ret); in pwrap_probe()
2521 ret = devm_clk_bulk_get_all_enable(wrp->dev, &clk); in pwrap_probe()
2523 return dev_err_probe(wrp->dev, ret, in pwrap_probe()
2527 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { in pwrap_probe()
2539 dev_dbg(wrp->dev, "init failed with %d\n", ret); in pwrap_probe()
2544 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_probe()
2546 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186)) in pwrap_probe()
2552 dev_dbg(wrp->dev, "initialization isn't finished\n"); in pwrap_probe()
2553 return -ENODEV; in pwrap_probe()
2557 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_probe()
2564 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); in pwrap_probe()
2565 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) in pwrap_probe()
2566 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); in pwrap_probe()
2568 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) in pwrap_probe()
2573 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); in pwrap_probe()
2578 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) in pwrap_probe()
2579 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); in pwrap_probe()
2585 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, in pwrap_probe()
2587 "mt-pmic-pwrap", wrp); in pwrap_probe()
2591 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap); in pwrap_probe()
2592 if (IS_ERR(wrp->regmap)) in pwrap_probe()
2593 return PTR_ERR(wrp->regmap); in pwrap_probe()
2595 ret = of_platform_populate(np, NULL, NULL, wrp->dev); in pwrap_probe()
2597 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", in pwrap_probe()
2607 .name = "mt-pmic-pwrap",
2616 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");