Lines Matching +full:mt6323 +full:- +full:regulator
1 // SPDX-License-Identifier: GPL-2.0-only
103 /* MT6323 only regs */
1346 * struct pwrap_slv_type - PMIC device wrapper definitions
1391 return readl(wrp->base + wrp->master->regs[reg]);
1396 writel(val, wrp->base + wrp->master->regs[reg]);
1404 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1460 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1471 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1516 return wrp->slave->regops->pwrap_read(wrp, adr, rdata);
1531 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
1561 * for the synchronization between two successive 16-bit
1562 * pwrap_writel operations composing one 32-bit bus writing.
1563 * Otherwise, we'll find the result fails on the lower 16-bit
1575 return wrp->slave->regops->pwrap_write(wrp, adr, wdata);
1611 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1613 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1615 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1619 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1625 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1636 * pwrap_init_sidly - configure serial input delay
1647 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1652 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs,
1655 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1661 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1663 return -EIO;
1678 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1679 if (wrp->slave->comp_dew_regs)
1680 pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1);
1686 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1693 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL);
1694 if (wrp->slave->comp_dew_regs)
1695 comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs,
1698 dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n",
1700 wrp->slave->comp_dew_regs && !comp_read_ok ?
1702 return -EFAULT;
1735 switch (wrp->master->type) {
1737 if (wrp->slave->type == PMIC_MT6331) {
1738 const u32 *dew_regs = wrp->slave->dew_regs;
1742 if (wrp->slave->comp_type == PMIC_MT6332) {
1743 dew_regs = wrp->slave->comp_dew_regs;
1766 switch (wrp->slave->type) {
1774 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1805 bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs);
1811 if (wrp->slave->comp_dew_regs)
1812 ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs);
1836 switch (wrp->master->type) {
1862 pwrap_config_cipher(wrp, wrp->slave->dew_regs);
1865 if (wrp->slave->comp_type > 0)
1866 pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs);
1868 switch (wrp->slave->type) {
1870 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1872 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1878 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1889 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1897 dev_err(wrp->dev,
1903 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1907 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1914 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1916 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1919 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1920 return -EFAULT;
1936 /* Signature checking - using CRC */
1937 ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1938 if (ret == 0 && wrp->slave->comp_dew_regs)
1939 ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1945 crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL];
1946 if (wrp->slave->comp_dew_regs)
1947 crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16;
1953 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1963 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1964 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1965 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1966 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1967 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1968 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1969 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1972 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1974 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1976 dev_err(wrp->dev, "enable dewrap fail\n");
1977 return -EFAULT;
1986 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1988 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1990 dev_err(wrp->dev, "enable dewrap fail\n");
1991 return -EFAULT;
2000 switch (wrp->slave->type) {
2019 if (wrp->slave->type == PMIC_MT6331)
2022 if (wrp->slave->comp_type == PMIC_MT6332)
2041 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
2058 if (wrp->rstc)
2059 reset_control_reset(wrp->rstc);
2060 if (wrp->rstc_bridge)
2061 reset_control_reset(wrp->rstc_bridge);
2063 switch (wrp->master->type) {
2075 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
2084 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
2088 ret = wrp->master->init_reg_clock(wrp);
2092 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
2099 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
2106 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
2113 if (wrp->master->type == PWRAP_MT8135)
2122 if (wrp->master->init_soc_specific) {
2123 ret = wrp->master->init_soc_specific(wrp);
2133 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2134 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
2135 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
2147 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
2150 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
2152 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
2251 { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },
2258 /* The MT6380 PMIC only implements a regulator, so we bind it
2261 { .compatible = "mediatek,mt6380-regulator", .data = &pmic_mt6380 },
2448 { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },
2449 { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },
2450 { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },
2451 { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 },
2452 { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 },
2453 { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 },
2454 { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 },
2455 { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 },
2456 { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 },
2457 { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 },
2458 { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 },
2459 { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 },
2460 { .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 },
2461 { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 },
2472 struct device_node *np = pdev->dev.of_node;
2475 if (np->child)
2476 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
2479 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
2480 return -EINVAL;
2483 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2485 return -ENOMEM;
2489 wrp->master = of_device_get_match_data(&pdev->dev);
2490 wrp->slave = of_slave_id->data;
2491 wrp->dev = &pdev->dev;
2493 wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap");
2494 if (IS_ERR(wrp->base))
2495 return PTR_ERR(wrp->base);
2497 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2498 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2499 if (IS_ERR(wrp->rstc)) {
2500 ret = PTR_ERR(wrp->rstc);
2501 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2506 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2507 wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge");
2508 if (IS_ERR(wrp->bridge_base))
2509 return PTR_ERR(wrp->bridge_base);
2511 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2512 "pwrap-bridge");
2513 if (IS_ERR(wrp->rstc_bridge)) {
2514 ret = PTR_ERR(wrp->rstc_bridge);
2515 dev_dbg(wrp->dev,
2516 "cannot get pwrap-bridge reset: %d\n", ret);
2521 ret = devm_clk_bulk_get_all_enabled(wrp->dev, &clk);
2523 return dev_err_probe(wrp->dev, ret,
2527 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2539 dev_dbg(wrp->dev, "init failed with %d\n", ret);
2544 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2546 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186))
2552 dev_dbg(wrp->dev, "initialization isn't finished\n");
2553 return -ENODEV;
2557 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2564 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2565 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2566 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2568 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2573 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2578 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2579 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2585 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2587 "mt-pmic-pwrap", wrp);
2591 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap);
2592 if (IS_ERR(wrp->regmap))
2593 return PTR_ERR(wrp->regmap);
2595 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2597 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2607 .name = "mt-pmic-pwrap",