Lines Matching +full:bd +full:- +full:address
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * QE UCC Slow API Set - UCC Slow specific routines implementations.
44 struct ucc_slow_info *us_info = uccs->us_info; in ucc_slow_graceful_stop_tx()
47 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_graceful_stop_tx()
55 struct ucc_slow_info *us_info = uccs->us_info; in ucc_slow_stop_tx()
58 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_stop_tx()
65 struct ucc_slow_info *us_info = uccs->us_info; in ucc_slow_restart_tx()
68 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_restart_tx()
78 us_regs = uccs->us_regs; in ucc_slow_enable()
81 gumr_l = ioread32be(&us_regs->gumr_l); in ucc_slow_enable()
84 uccs->enabled_tx = 1; in ucc_slow_enable()
88 uccs->enabled_rx = 1; in ucc_slow_enable()
90 iowrite32be(gumr_l, &us_regs->gumr_l); in ucc_slow_enable()
99 us_regs = uccs->us_regs; in ucc_slow_disable()
102 gumr_l = ioread32be(&us_regs->gumr_l); in ucc_slow_disable()
105 uccs->enabled_tx = 0; in ucc_slow_disable()
109 uccs->enabled_rx = 0; in ucc_slow_disable()
111 iowrite32be(gumr_l, &us_regs->gumr_l); in ucc_slow_disable()
125 struct qe_bd __iomem *bd; in ucc_slow_init() local
131 return -EINVAL; in ucc_slow_init()
134 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) { in ucc_slow_init()
136 return -EINVAL; in ucc_slow_init()
145 if ((!us_info->rfw) && in ucc_slow_init()
146 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) { in ucc_slow_init()
148 return -EINVAL; in ucc_slow_init()
155 return -ENOMEM; in ucc_slow_init()
157 uccs->rx_base_offset = -1; in ucc_slow_init()
158 uccs->tx_base_offset = -1; in ucc_slow_init()
159 uccs->us_pram_offset = -1; in ucc_slow_init()
162 uccs->us_info = us_info; in ucc_slow_init()
163 /* Set the PHY base address */ in ucc_slow_init()
164 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow)); in ucc_slow_init()
165 if (uccs->us_regs == NULL) { in ucc_slow_init()
168 return -ENOMEM; in ucc_slow_init()
171 us_regs = uccs->us_regs; in ucc_slow_init()
172 uccs->p_ucce = &us_regs->ucce; in ucc_slow_init()
173 uccs->p_uccm = &us_regs->uccm; in ucc_slow_init()
176 uccs->us_pram_offset = in ucc_slow_init()
178 if (uccs->us_pram_offset < 0) { in ucc_slow_init()
181 return -ENOMEM; in ucc_slow_init()
183 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_init()
184 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol, in ucc_slow_init()
185 uccs->us_pram_offset); in ucc_slow_init()
187 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset); in ucc_slow_init()
190 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW); in ucc_slow_init()
197 iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr); in ucc_slow_init()
199 INIT_LIST_HEAD(&uccs->confQ); in ucc_slow_init()
202 uccs->rx_base_offset = in ucc_slow_init()
203 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd), in ucc_slow_init()
205 if (uccs->rx_base_offset < 0) { in ucc_slow_init()
207 us_info->rx_bd_ring_len); in ucc_slow_init()
209 return -ENOMEM; in ucc_slow_init()
212 uccs->tx_base_offset = in ucc_slow_init()
213 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd), in ucc_slow_init()
215 if (uccs->tx_base_offset < 0) { in ucc_slow_init()
218 return -ENOMEM; in ucc_slow_init()
222 bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset); in ucc_slow_init()
223 for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) { in ucc_slow_init()
224 /* clear bd buffer */ in ucc_slow_init()
225 iowrite32be(0, &bd->buf); in ucc_slow_init()
226 /* set bd status and length */ in ucc_slow_init()
227 iowrite32be(0, (u32 __iomem *)bd); in ucc_slow_init()
228 bd++; in ucc_slow_init()
230 /* for last BD set Wrap bit */ in ucc_slow_init()
231 iowrite32be(0, &bd->buf); in ucc_slow_init()
232 iowrite32be(T_W, (u32 __iomem *)bd); in ucc_slow_init()
235 bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset); in ucc_slow_init()
236 for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) { in ucc_slow_init()
237 /* set bd status and length */ in ucc_slow_init()
238 iowrite32be(0, (u32 __iomem *)bd); in ucc_slow_init()
239 /* clear bd buffer */ in ucc_slow_init()
240 iowrite32be(0, &bd->buf); in ucc_slow_init()
241 bd++; in ucc_slow_init()
243 /* for last BD set Wrap bit */ in ucc_slow_init()
244 iowrite32be(R_W, (u32 __iomem *)bd); in ucc_slow_init()
245 iowrite32be(0, &bd->buf); in ucc_slow_init()
249 gumr = us_info->tcrc; in ucc_slow_init()
250 if (us_info->cdp) in ucc_slow_init()
252 if (us_info->ctsp) in ucc_slow_init()
254 if (us_info->cds) in ucc_slow_init()
256 if (us_info->ctss) in ucc_slow_init()
258 if (us_info->tfl) in ucc_slow_init()
260 if (us_info->rfw) in ucc_slow_init()
262 if (us_info->txsy) in ucc_slow_init()
264 if (us_info->rtsm) in ucc_slow_init()
266 iowrite32be(gumr, &us_regs->gumr_h); in ucc_slow_init()
269 gumr = (u32)us_info->tdcr | (u32)us_info->rdcr | (u32)us_info->tenc | in ucc_slow_init()
270 (u32)us_info->renc | (u32)us_info->diag | (u32)us_info->mode; in ucc_slow_init()
271 if (us_info->tci) in ucc_slow_init()
273 if (us_info->rinv) in ucc_slow_init()
275 if (us_info->tinv) in ucc_slow_init()
277 if (us_info->tend) in ucc_slow_init()
279 iowrite32be(gumr, &us_regs->gumr_l); in ucc_slow_init()
285 iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr); in ucc_slow_init()
286 iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr); in ucc_slow_init()
289 iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase); in ucc_slow_init()
290 iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase); in ucc_slow_init()
294 ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support); in ucc_slow_init()
296 ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support); in ucc_slow_init()
298 ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa); in ucc_slow_init()
300 if (!us_info->tsa) { in ucc_slow_init()
302 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock, in ucc_slow_init()
307 return -EINVAL; in ucc_slow_init()
310 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock, in ucc_slow_init()
315 return -EINVAL; in ucc_slow_init()
320 iowrite16be(us_info->uccm_mask, &us_regs->uccm); in ucc_slow_init()
327 iowrite16be(0xffff, &us_regs->ucce); in ucc_slow_init()
330 if (us_info->init_tx && us_info->init_rx) in ucc_slow_init()
332 else if (us_info->init_tx) in ucc_slow_init()
337 qe_issue_cmd(command, id, us_info->protocol, 0); in ucc_slow_init()
349 qe_muram_free(uccs->rx_base_offset); in ucc_slow_free()
350 qe_muram_free(uccs->tx_base_offset); in ucc_slow_free()
351 qe_muram_free(uccs->us_pram_offset); in ucc_slow_free()
353 if (uccs->us_regs) in ucc_slow_free()
354 iounmap(uccs->us_regs); in ucc_slow_free()