1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * QE UCC API Set - UCC specific routines implementations.
33 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_mii_mng()
34 		return -EINVAL;  in ucc_set_qe_mux_mii_mng()
37 	qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,  in ucc_set_qe_mux_mii_mng()
50  * 'ucc_num' is the UCC number, from 0 - 7.
62 	case 0: guemr = &qe_immr->ucc1.slow.guemr;  in ucc_set_type()
64 	case 1: guemr = &qe_immr->ucc2.slow.guemr;  in ucc_set_type()
66 	case 2: guemr = &qe_immr->ucc3.slow.guemr;  in ucc_set_type()
68 	case 3: guemr = &qe_immr->ucc4.slow.guemr;  in ucc_set_type()
70 	case 4: guemr = &qe_immr->ucc5.slow.guemr;  in ucc_set_type()
72 	case 5: guemr = &qe_immr->ucc6.slow.guemr;  in ucc_set_type()
74 	case 6: guemr = &qe_immr->ucc7.slow.guemr;  in ucc_set_type()
76 	case 7: guemr = &qe_immr->ucc8.slow.guemr;  in ucc_set_type()
78 	default:  in ucc_set_type()
79 		return -EINVAL;  in ucc_set_type()
94 	*cmxucr = &qe_immr->qmx.cmxucr[cmx];  in get_cmxucr_reg()
95 	*shift = 16 - 8 * (ucc_num & 2);  in get_cmxucr_reg()
105 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_mux_set_grant_tsa_bkpt()
106 		return -EINVAL;  in ucc_mux_set_grant_tsa_bkpt()
120 	enum comm_dir mode)  in ucc_set_qe_mux_rxtx()  argument
128 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_rxtx()
129 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
132 	if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))  in ucc_set_qe_mux_rxtx()
133 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
150 		default: break;  in ucc_set_qe_mux_rxtx()
165 		default: break;  in ucc_set_qe_mux_rxtx()
181 		default: break;  in ucc_set_qe_mux_rxtx()
197 		default: break;  in ucc_set_qe_mux_rxtx()
200 	default: break;  in ucc_set_qe_mux_rxtx()
205 		return -ENOENT;  in ucc_set_qe_mux_rxtx()
207 	if (mode == COMM_DIR_RX)  in ucc_set_qe_mux_rxtx()
218 	int clock_bits = -EINVAL;  in ucc_get_tdm_common_clk()
244 		default:  in ucc_get_tdm_common_clk()
265 		default:  in ucc_get_tdm_common_clk()
269 	default:  in ucc_get_tdm_common_clk()
278 	int clock_bits = -EINVAL;  in ucc_get_tdm_rx_clk()
289 		default:  in ucc_get_tdm_rx_clk()
301 		default:  in ucc_get_tdm_rx_clk()
313 		default:  in ucc_get_tdm_rx_clk()
325 		default:  in ucc_get_tdm_rx_clk()
337 		default:  in ucc_get_tdm_rx_clk()
349 		default:  in ucc_get_tdm_rx_clk()
361 		default:  in ucc_get_tdm_rx_clk()
373 		default:  in ucc_get_tdm_rx_clk()
384 	int clock_bits = -EINVAL;  in ucc_get_tdm_tx_clk()
395 		default:  in ucc_get_tdm_tx_clk()
407 		default:  in ucc_get_tdm_tx_clk()
419 		default:  in ucc_get_tdm_tx_clk()
431 		default:  in ucc_get_tdm_tx_clk()
443 		default:  in ucc_get_tdm_tx_clk()
455 		default:  in ucc_get_tdm_tx_clk()
467 		default:  in ucc_get_tdm_tx_clk()
479 		default:  in ucc_get_tdm_tx_clk()
488 /* tdm_num: TDM A-H port num is 0-7 */
489 static int ucc_get_tdm_rxtx_clk(enum comm_dir mode, u32 tdm_num,  in ucc_get_tdm_rxtx_clk()  argument
497 	if (mode == COMM_DIR_RX)  in ucc_get_tdm_rxtx_clk()
499 	if (mode == COMM_DIR_TX)  in ucc_get_tdm_rxtx_clk()
504 static u32 ucc_get_tdm_clk_shift(enum comm_dir mode, u32 tdm_num)  in ucc_get_tdm_clk_shift()  argument
508 	shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE;  in ucc_get_tdm_clk_shift()
510 		shift -= tdm_num * 4;  in ucc_get_tdm_clk_shift()
512 		shift -= (tdm_num - 4) * 4;  in ucc_get_tdm_clk_shift()
518 			 enum comm_dir mode)  in ucc_set_tdm_rxtx_clk()  argument
525 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_clk()
528 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
531 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)  in ucc_set_tdm_rxtx_clk()
532 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
534 	clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock);  in ucc_set_tdm_rxtx_clk()
536 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
538 	shift = ucc_get_tdm_clk_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_clk()
540 	cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :  in ucc_set_tdm_rxtx_clk()
541 				  &qe_mux_reg->cmxsi1cr_h;  in ucc_set_tdm_rxtx_clk()
550 				   enum comm_dir mode)  in ucc_get_tdm_sync_source()  argument
552 	int source = -EINVAL;  in ucc_get_tdm_sync_source()
554 	if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {  in ucc_get_tdm_sync_source()
558 	if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {  in ucc_get_tdm_sync_source()
573 		default:  in ucc_get_tdm_sync_source()
586 		default:  in ucc_get_tdm_sync_source()
599 		default:  in ucc_get_tdm_sync_source()
612 		default:  in ucc_get_tdm_sync_source()
621 static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num)  in ucc_get_tdm_sync_shift()  argument
625 	shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : TX_SYNC_SHIFT_BASE;  in ucc_get_tdm_sync_shift()
626 	shift -= tdm_num * 2;  in ucc_get_tdm_sync_shift()
632 			  enum comm_dir mode)  in ucc_set_tdm_rxtx_sync()  argument
638 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_sync()
641 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
644 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)  in ucc_set_tdm_rxtx_sync()
645 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
647 	source = ucc_get_tdm_sync_source(tdm_num, clock, mode);  in ucc_set_tdm_rxtx_sync()
649 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
651 	shift = ucc_get_tdm_sync_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_sync()
653 	qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,  in ucc_set_tdm_rxtx_sync()