29 #define SCC_GSMRL	0x00
32 #define SCC_GSMRL_MODE_MASK	GENMASK(3, 0)
33 #define SCC_CPM1_GSMRL_MODE_QMC	FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x0A)
34 #define SCC_QE_GSMRL_MODE_QMC	FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x02)
37 #define SCC_GSMRH	0x04
46 #define SCC_SCCE	0x10
50 #define   SCC_SCCE_GOV		BIT(0)
53 #define SCC_SCCM	0x14
56 #define SCC_QE_UCC_GUEMR	0x90
59 #define QMC_GBL_MCBASE		0x00
61 #define QMC_GBL_QMCSTATE	0x04
63 #define QMC_GBL_MRBLR		0x06
65 #define QMC_GBL_TX_S_PTR	0x08
67 #define QMC_GBL_RXPTR		0x0A
69 #define QMC_GBL_GRFTHR		0x0C
71 #define QMC_GBL_GRFCNT		0x0E
73 #define QMC_GBL_INTBASE		0x10
75 #define QMC_GBL_INTPTR		0x14
77 #define QMC_GBL_RX_S_PTR	0x18
79 #define QMC_GBL_TXPTR		0x1A
81 #define QMC_GBL_C_MASK32	0x1C
83 #define QMC_GBL_TSATRX		0x20
85 #define QMC_GBL_TSATTX		0x60
87 #define QMC_GBL_C_MASK16	0xA0
89 #define QMC_QE_GBL_RX_FRM_BASE	0xAC
91 #define QMC_QE_GBL_TX_FRM_BASE	0xAE
92 /* A reserved area (0xB0 -> 0xC3) that must be initialized to 0 (QE only) */
93 #define QMC_QE_GBL_RSV_B0_START	0xB0
94 #define QMC_QE_GBL_RSV_B0_SIZE	0x14
96 #define QMC_QE_GBL_GCSBASE	0xC4
102 #define QMC_TSA_MASK_MASKL	GENMASK(5, 0)
103 #define QMC_TSA_MASK_8BIT	(FIELD_PREP_CONST(QMC_TSA_MASK_MASKH, 0x3) | \
104 				 FIELD_PREP_CONST(QMC_TSA_MASK_MASKL, 0x3F))
109 #define QMC_SPE_TBASE	0x00
112 #define QMC_SPE_CHAMR	0x02
115 #define   QMC_SPE_CHAMR_MODE_TRANSP	(FIELD_PREP_CONST(QMC_SPE_CHAMR_MODE_MASK, 0) | BIT(13))
120 #define   QMC_SPE_CHAMR_HDLC_NOF_MASK	GENMASK(3, 0)
126 #define QMC_SPE_TSTATE	0x04
128 #define QMC_SPE_TBPTR	0x0C
130 #define QMC_SPE_ZISTATE	0x14
132 #define QMC_SPE_INTMSK	0x1C
134 #define QMC_SPE_RBASE	0x20
136 #define QMC_SPE_MFLR	0x22
138 #define QMC_SPE_TMRBLR	0x22
140 #define QMC_SPE_RSTATE	0x24
142 #define QMC_SPE_RBPTR	0x2C
144 #define QMC_SPE_RPACK	0x30
146 #define QMC_SPE_ZDSTATE	0x34
149 #define QMC_SPE_TRNSYNC 0x3C
152 #define   QMC_SPE_TRNSYNC_TX_MASK	GENMASK(7, 0)
167 #define QMC_INT_RXB		BIT(0)
189 #define QMC_BD_TX_PAD_MASK	GENMASK(3, 0)
350 	return 0;  in qmc_chan_get_info()
367 	return 0;  in qmc_chan_get_ts_info()
397 		ret = 0;  in qmc_chan_set_ts_info()
438 	return 0;  in qmc_chan_set_param()
453 	 *   0       0  : The BD is free  in qmc_chan_write_submit()
455 	 *   0       1  : The BD is in used, waiting for completion  in qmc_chan_write_submit()
456 	 *   1       0  : Should not append  in qmc_chan_write_submit()
489 	ret = 0;  in qmc_chan_write_submit()
508 	 *   0       0  : The BD is free  in qmc_chan_write_done()
510 	 *   0       1  : The BD is in used, waiting for completion  in qmc_chan_write_done()
511 	 *   1       0  : Should not append  in qmc_chan_write_done()
561 	 *   0       0  : The BD is free  in qmc_chan_read_submit()
563 	 *   0       1  : The BD is in used, waiting for completion  in qmc_chan_read_submit()
564 	 *   1       0  : Should not append  in qmc_chan_read_submit()
577 	qmc_write16(&bd->cbd_datlen, 0); /* data length is updated by the QMC */  in qmc_chan_read_submit()
611 	ret = 0;  in qmc_chan_read_submit()
630 	 *   0       0  : The BD is free  in qmc_chan_read_done()
632 	 *   0       1  : The BD is in used, waiting for completion  in qmc_chan_read_done()
633 	 *   1       0  : Should not append  in qmc_chan_read_done()
709 	for (i = 0; i < info->nb_rx_ts; i++) {  in qmc_chan_setup_tsa_64rxtx()
722 	for (i = 0; i < info->nb_rx_ts; i++) {  in qmc_chan_setup_tsa_64rxtx()
727 				 (u16)~QMC_TSA_WRAP, enable ? val : 0x0000);  in qmc_chan_setup_tsa_64rxtx()
730 	return 0;  in qmc_chan_setup_tsa_64rxtx()
745 	for (i = 0; i < info->nb_rx_ts; i++) {  in qmc_chan_setup_tsa_32rx()
758 	for (i = 0; i < info->nb_rx_ts; i++) {  in qmc_chan_setup_tsa_32rx()
763 				 (u16)~QMC_TSA_WRAP, enable ? val : 0x0000);  in qmc_chan_setup_tsa_32rx()
766 	return 0;  in qmc_chan_setup_tsa_32rx()
781 	for (i = 0; i < info->nb_tx_ts; i++) {  in qmc_chan_setup_tsa_32tx()
794 	for (i = 0; i < info->nb_tx_ts; i++) {  in qmc_chan_setup_tsa_32tx()
799 				 (u16)~QMC_TSA_WRAP, enable ? val : 0x0000);  in qmc_chan_setup_tsa_32tx()
802 	return 0;  in qmc_chan_setup_tsa_32tx()
841 	return cpm_command(chan->id << 2, (qmc_opcode << 4) | 0x0E);  in qmc_chan_cpm1_command()
846 	if (!qe_issue_cmd(cmd, chan->qmc->qe_subblock, chan->id, 0))  in qmc_chan_qe_command()
848 	return 0;  in qmc_chan_qe_command()
860 		ret = 0;  in qmc_chan_stop_rx()
867 		qmc_chan_cpm1_command(chan, 0x0);  in qmc_chan_stop_rx()
899 		ret = 0;  in qmc_chan_stop_tx()
906 		qmc_chan_cpm1_command(chan, 0x1);  in qmc_chan_stop_tx()
935 	int ret = 0;  in qmc_chan_stop()
980 		return 0;  in qmc_setup_chan_trnsync()
984 	first_rx = chan->rx_ts_mask ? __ffs64(chan->rx_ts_mask) + 1 : 0;  in qmc_setup_chan_trnsync()
989 	trnsync = 0;  in qmc_setup_chan_trnsync()
998 	dev_dbg(qmc->dev, "chan %u: trnsync=0x%04x, rx %u/%u 0x%llx, tx %u/%u 0x%llx\n",  in qmc_setup_chan_trnsync()
1003 	return 0;  in qmc_setup_chan_trnsync()
1015 		ret = 0;  in qmc_chan_start_rx()
1060 		ret = 0;  in qmc_chan_start_tx()
1100 	int ret = 0;  in qmc_chan_start()
1152 	chan->rx_pending = 0;  in qmc_chan_reset_rx()
1201 	return 0;  in qmc_chan_reset()
1249 	return 0;  in qmc_check_chans()
1254 	unsigned int count = 0;  in qmc_nb_chans()
1358 	for (i = 0; i < 64; i++)  in qmc_init_tsa_64rxtx()
1359 		qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000);  in qmc_init_tsa_64rxtx()
1372 	return 0;  in qmc_init_tsa_64rxtx()
1387 	for (i = 0; i < 32; i++) {  in qmc_init_tsa_32rx_32tx()
1388 		qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000);  in qmc_init_tsa_32rx_32tx()
1389 		qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), 0x0000);  in qmc_init_tsa_32rx_32tx()
1408 	return 0;  in qmc_init_tsa_32rx_32tx()
1481 	qmc_write16(chan->s_param + QMC_SPE_INTMSK, 0x0000);  in qmc_setup_chan()
1484 	BUILD_BUG_ON(QMC_NB_RXBDS == 0);  in qmc_setup_chan()
1486 	for (i = 0; i < QMC_NB_RXBDS; i++) {  in qmc_setup_chan()
1494 	BUILD_BUG_ON(QMC_NB_TXBDS == 0);  in qmc_setup_chan()
1498 	for (i = 0; i < QMC_NB_TXBDS; i++) {  in qmc_setup_chan()
1505 	return 0;  in qmc_setup_chan()
1519 	return 0;  in qmc_setup_chans()
1546 	return 0;  in qmc_finalize_chans()
1555 	for (i = 0; i < (qmc->int_size / sizeof(u16)); i++)  in qmc_setup_ints()
1556 		qmc_write16(qmc->int_table + i, 0x0000);  in qmc_setup_ints()
1564 	return 0;  in qmc_setup_ints()
1590 			dev_info(qmc->dev, "intr chan %u, 0x%04x (UN)\n", chan_id,  in qmc_irq_gint()
1596 			dev_info(qmc->dev, "intr chan %u, 0x%04x (BSY)\n", chan_id,  in qmc_irq_gint()
1663 	case 0:  in qmc_qe_soft_qmc_init()
1667 		return 0;  in qmc_qe_soft_qmc_init()
1681 		return 0;  in qmc_qe_soft_qmc_init()
1707 	ret = 0;  in qmc_qe_soft_qmc_init()
1733 	return 0;  in qmc_cpm1_init_resources()
1747 	if (ucc_num < 0)  in qmc_qe_init_resources()
1764 	if (info < 0)  in qmc_qe_init_resources()
1778 	qmc->dpram_offset = res->start - qe_muram_dma(qe_muram_addr(0));  in qmc_qe_init_resources()
1783 	return 0;  in qmc_qe_init_resources()
1811 	qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);  in qmc_cpm1_init_scc()
1812 	qmc_write16(qmc->scc_regs + SCC_SCCE, 0x000F);  in qmc_cpm1_init_scc()
1814 	return 0;  in qmc_cpm1_init_scc()
1833 			  QE_CR_PROTOCOL_UNSPECIFIED, 0x80)) {  in qmc_qe_init_ucc()
1840 	if (!qe_issue_cmd(QE_PUSHSCHED, qmc->qe_subblock | 0x00020000,  in qmc_qe_init_ucc()
1841 			  QE_CR_PROTOCOL_UNSPECIFIED, 0x82)) {  in qmc_qe_init_ucc()
1865 	qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);  in qmc_qe_init_ucc()
1866 	qmc_write16(qmc->scc_regs + SCC_SCCE, 0x000F);  in qmc_qe_init_ucc()
1868 	return 0;  in qmc_qe_init_ucc()
1942 	memset(qmc->bd_table, 0, qmc->bd_size);  in qmc_probe()
1954 	memset(qmc->int_table, 0, qmc->int_size);  in qmc_probe()
1966 	qmc_write32(qmc->scc_pram + QMC_GBL_C_MASK32, 0xDEBB20E3);  in qmc_probe()
1967 	qmc_write16(qmc->scc_pram + QMC_GBL_C_MASK16, 0xF0B8);  in qmc_probe()
1971 		memset_io(qmc->scc_pram + QMC_QE_GBL_RSV_B0_START, 0,  in qmc_probe()
1977 		memset_io(qmc->scc_pram + UCC_SLOW_PRAM_SIZE, 0x01, 64);  in qmc_probe()
1978 		memset_io(qmc->scc_pram + UCC_SLOW_PRAM_SIZE + 64, 0x01, 64);  in qmc_probe()
1989 	qmc_write16(qmc->scc_pram + QMC_GBL_QMCSTATE, 0x8000);  in qmc_probe()
2006 	irq = platform_get_irq(pdev, 0);  in qmc_probe()
2007 	if (irq < 0)  in qmc_probe()
2009 	ret = devm_request_irq(qmc->dev, irq, qmc_irq_handler, 0, "qmc", qmc);  in qmc_probe()
2010 	if (ret < 0)  in qmc_probe()
2018 	if (ret < 0)  in qmc_probe()
2031 	return 0;  in qmc_probe()
2034 	qmc_setbits32(qmc->scc_regs + SCC_GSMRL, 0);  in qmc_probe()
2037 	qmc_write16(qmc->scc_regs + SCC_SCCM, 0);  in qmc_probe()
2049 	qmc_setbits32(qmc->scc_regs + SCC_GSMRL, 0);  in qmc_remove()
2052 	qmc_write16(qmc->scc_regs + SCC_SCCM, 0);  in qmc_remove()
2060 	.tstate = 0x30000000,
2061 	.rstate = 0x31000000,
2062 	.zistate = 0x00000100,
2063 	.zdstate_hdlc = 0x00000080,
2064 	.zdstate_transp = 0x18000080,
2065 	.rpack = 0x00000000,
2070 	.tstate = 0x30000000,
2071 	.rstate = 0x30000000,
2072 	.zistate = 0x00000200,
2073 	.zdstate_hdlc = 0x80FFFFE0,
2074 	.zdstate_transp = 0x003FFFE2,
2075 	.rpack = 0x80000000,
2138 	if (count < 0)  in qmc_chan_count_phandles()
2155 	if (ret < 0)  in qmc_chan_get_byphandles_index()
2163 	qmc_chan = qmc_chan_get_from_qmc(out_args.np, out_args.args[0]);  in qmc_chan_get_byphandles_index()