Lines Matching +full:0 +full:x10100
13 #define PHAN_INITIALIZE_FAILED 0xffff
14 #define PHAN_INITIALIZE_COMPLETE 0xff01
17 #define PHAN_INITIALIZE_ACK 0xf00f
18 #define PHAN_PEG_RCV_INITIALIZED 0xff01
21 #define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))
23 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
24 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
25 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
26 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
31 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
38 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
43 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
44 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
46 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
47 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
48 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
49 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
50 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
51 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
52 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
54 /* Hub 0 */
55 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
56 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
59 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
60 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
61 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
62 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
63 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
64 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
65 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
66 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
67 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
68 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
69 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
70 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
71 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
72 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
73 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
76 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
77 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
78 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
80 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
81 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
82 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
83 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
84 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
85 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
86 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
87 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
88 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
89 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
90 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
91 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
92 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
95 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
96 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
97 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
98 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
101 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
102 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
103 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
104 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
105 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
106 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
107 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
108 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
109 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
110 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
111 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
112 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
115 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
116 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
117 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
118 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
120 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
121 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
122 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
125 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
126 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
127 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
128 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
129 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
130 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
131 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
132 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
133 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
137 #define QLA82XX_HW_PX_MAP_CRB_PH 0
343 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
344 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
345 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
346 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
347 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
348 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
349 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
350 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
351 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
353 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
354 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
355 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
358 #define ROM_LOCK_DRIVER 0x0d417340
360 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
494 #define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)
495 #define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
501 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
502 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
503 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
504 #define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)
505 #define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)
506 #define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)
507 #define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)
508 #define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)
510 #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
511 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
512 #define QLA8XXX_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
514 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
515 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
516 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
517 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
518 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
519 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
520 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
529 #define MIU_CONTROL (0x000)
530 #define MIU_TAG (0x004)
531 #define MIU_TEST_AGT_CTRL (0x090)
532 #define MIU_TEST_AGT_ADDR_LO (0x094)
533 #define MIU_TEST_AGT_ADDR_HI (0x098)
534 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
535 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
536 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
537 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
538 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
539 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
540 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
541 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
555 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
558 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
559 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
560 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
561 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
562 #define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))
563 #define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))
565 #define HALT_STATUS_UNRECOVERABLE 0x80000000
566 #define HALT_STATUS_RECOVERABLE 0x40000000
569 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
570 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
571 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
572 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
573 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
577 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
578 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
579 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
580 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
581 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
582 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
585 QLA8XXX_PEG_HALT_STATUS1 = 0,
611 #define QLA82XX_IDC_VERSION 0x1
615 #define PCIE_SETUP_FUNCTION (0x12040)
616 #define PCIE_SETUP_FUNCTION2 (0x12048)
621 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
622 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
623 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
624 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
625 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
626 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
632 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
633 #define QLA82XX_PCI_MSIX_CONTROL 0x40
651 #define ADDR_ERROR ((unsigned long) 0xffffffff)
653 #define QLA82XX_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)
662 #define PCIX_TARGET_STATUS (0x10118)
663 #define PCIX_TARGET_STATUS_F1 (0x10160)
664 #define PCIX_TARGET_STATUS_F2 (0x10164)
665 #define PCIX_TARGET_STATUS_F3 (0x10168)
666 #define PCIX_TARGET_STATUS_F4 (0x10360)
667 #define PCIX_TARGET_STATUS_F5 (0x10364)
668 #define PCIX_TARGET_STATUS_F6 (0x10368)
669 #define PCIX_TARGET_STATUS_F7 (0x1036c)
671 #define PCIX_TARGET_MASK (0x10128)
672 #define PCIX_TARGET_MASK_F1 (0x10170)
673 #define PCIX_TARGET_MASK_F2 (0x10174)
674 #define PCIX_TARGET_MASK_F3 (0x10178)
675 #define PCIX_TARGET_MASK_F4 (0x10370)
676 #define PCIX_TARGET_MASK_F5 (0x10374)
677 #define PCIX_TARGET_MASK_F6 (0x10378)
678 #define PCIX_TARGET_MASK_F7 (0x1037c)
683 #define PCIX_MSI_F0 (0x13000)
684 #define PCIX_MSI_F1 (0x13004)
685 #define PCIX_MSI_F2 (0x13008)
686 #define PCIX_MSI_F3 (0x1300c)
687 #define PCIX_MSI_F4 (0x13010)
688 #define PCIX_MSI_F5 (0x13014)
689 #define PCIX_MSI_F6 (0x13018)
690 #define PCIX_MSI_F7 (0x1301c)
691 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
696 #define PCIX_INT_VECTOR (0x10100)
697 #define PCIX_INT_MASK (0x10104)
702 #define PCIE_MISCCFG_RC (0x1206c)
746 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
747 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
752 #define PCIX_INT_VECTOR_BIT_F0 0x0080
753 #define PCIX_INT_VECTOR_BIT_F1 0x0100
754 #define PCIX_INT_VECTOR_BIT_F2 0x0200
755 #define PCIX_INT_VECTOR_BIT_F3 0x0400
756 #define PCIX_INT_VECTOR_BIT_F4 0x0800
757 #define PCIX_INT_VECTOR_BIT_F5 0x1000
758 #define PCIX_INT_VECTOR_BIT_F6 0x2000
759 #define PCIX_INT_VECTOR_BIT_F7 0x4000
769 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
815 #define QLA82XX_BDINFO_MAGIC 0x12345678
816 #define FW_SIZE_OFFSET (0x3e840c)
819 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
820 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
825 #define QLA8XXX_RDNOP 0
855 #define QLA8XXX_DBG_OPCODE_WR 0x01
856 #define QLA8XXX_DBG_OPCODE_RW 0x02
857 #define QLA8XXX_DBG_OPCODE_AND 0x04
858 #define QLA8XXX_DBG_OPCODE_OR 0x08
859 #define QLA8XXX_DBG_OPCODE_POLL 0x10
860 #define QLA8XXX_DBG_OPCODE_RDSTATE 0x20
861 #define QLA8XXX_DBG_OPCODE_WRSTATE 0x40
862 #define QLA8XXX_DBG_OPCODE_MDSTATE 0x80
865 #define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
866 #define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
993 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
994 #define RQST_TMPLT_SIZE 0x0
995 #define RQST_TMPLT 0x1
996 #define MD_DIRECT_ROM_WINDOW 0x42110030
997 #define MD_DIRECT_ROM_READ_BASE 0x42150000
998 #define MD_MIU_TEST_AGT_CTRL 0x41000090
999 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1000 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1002 #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
1003 #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
1004 #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
1005 #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4