Lines Matching +full:hw +full:- +full:timeout +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
36 return readl((void __iomem *) (ha->nx_pcibase + addr)); in qla8044_rd_reg()
42 writel(val, (void __iomem *)((ha)->nx_pcibase + addr)); in qla8044_wr_reg()
49 struct qla_hw_data *ha = vha->hw; in qla8044_rd_direct()
62 struct qla_hw_data *ha = vha->hw; in qla8044_wr_direct()
73 struct qla_hw_data *ha = vha->hw; in qla8044_set_win_base()
75 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr); in qla8044_set_win_base()
76 val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum)); in qla8044_set_win_base()
92 struct qla_hw_data *ha = vha->hw; in qla8044_rd_reg_indirect()
107 struct qla_hw_data *ha = vha->hw; in qla8044_wr_reg_indirect()
120 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
141 unsigned long timeout; in qla8044_poll_wait_for_ready() local
144 /* jiffies after 100ms */ in qla8044_poll_wait_for_ready()
145 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); in qla8044_poll_wait_for_ready()
150 if (time_after_eq(jiffies, timeout)) { in qla8044_poll_wait_for_ready()
153 return -1; in qla8044_poll_wait_for_ready()
168 if (ret == -1) in qla8044_ipmdio_rd_reg()
169 return -1; in qla8044_ipmdio_rd_reg()
175 if (ret == -1) in qla8044_ipmdio_rd_reg()
188 unsigned long timeout; in qla8044_poll_wait_ipmdio_bus_idle() local
192 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); in qla8044_poll_wait_ipmdio_bus_idle()
197 if (time_after_eq(jiffies, timeout)) { in qla8044_poll_wait_ipmdio_bus_idle()
200 return -1; in qla8044_poll_wait_ipmdio_bus_idle()
214 if (ret == -1) in qla8044_ipmdio_wr_reg()
215 return -1; in qla8044_ipmdio_wr_reg()
221 if (ret == -1) in qla8044_ipmdio_wr_reg()
222 return -1; in qla8044_ipmdio_wr_reg()
227 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
242 if (p_rmw_hdr->index_a) in qla8044_rmw_crb_reg()
243 value = vha->reset_tmplt.array[p_rmw_hdr->index_a]; in qla8044_rmw_crb_reg()
246 value &= p_rmw_hdr->test_mask; in qla8044_rmw_crb_reg()
247 value <<= p_rmw_hdr->shl; in qla8044_rmw_crb_reg()
248 value >>= p_rmw_hdr->shr; in qla8044_rmw_crb_reg()
249 value |= p_rmw_hdr->or_value; in qla8044_rmw_crb_reg()
250 value ^= p_rmw_hdr->xor_value; in qla8044_rmw_crb_reg()
259 struct qla_hw_data *ha = vha->hw; in qla8044_set_qsnt_ready()
262 qsnt_state |= (1 << ha->portnum); in qla8044_set_qsnt_ready()
265 __func__, vha->host_no, qsnt_state); in qla8044_set_qsnt_ready()
272 struct qla_hw_data *ha = vha->hw; in qla8044_clear_qsnt_ready()
275 qsnt_state &= ~(1 << ha->portnum); in qla8044_clear_qsnt_ready()
278 __func__, vha->host_no, qsnt_state); in qla8044_clear_qsnt_ready()
282 * qla8044_lock_recovery - Recovers the idc_lock.
286 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
288 * 1-0 1 - Driver intends to force unlock the IDC lock.
289 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
296 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
298 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
310 struct qla_hw_data *ha = vha->hw; in qla8044_lock_recovery()
320 (ha->portnum << in qla8044_lock_recovery()
326 if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum << in qla8044_lock_recovery()
331 , __func__, ha->portnum); in qla8044_lock_recovery()
335 (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | in qla8044_lock_recovery()
342 /* Clear bits 0-5 in IDC_RECOVERY register*/ in qla8044_lock_recovery()
349 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum; in qla8044_lock_recovery()
359 uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0; in qla8044_idc_lock() local
361 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla8044_idc_lock()
364 /* acquire semaphore5 from PCI HW block */ in qla8044_idc_lock()
368 /* Increment Counter (8-31) and update func_num (0-7) on in qla8044_idc_lock()
371 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum; in qla8044_idc_lock()
376 if (timeout == 0) in qla8044_idc_lock()
379 if (++timeout >= in qla8044_idc_lock()
387 __func__, ha->portnum, func_num, lock_cnt, in qla8044_idc_lock()
396 __func__, ha->portnum); in qla8044_idc_lock()
397 timeout = 0; in qla8044_idc_lock()
407 ha->portnum); in qla8044_idc_lock()
415 "failed, Retrying timeout\n", __func__, in qla8044_idc_lock()
416 ha->portnum); in qla8044_idc_lock()
417 timeout = 0; in qla8044_idc_lock()
429 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla8044_idc_unlock()
433 if ((id & 0xFF) != ha->portnum) { in qla8044_idc_unlock()
436 __func__, ha->portnum, (id & 0xFF)); in qla8044_idc_unlock()
440 /* Keep lock counter value, update the ha->func_num to 0xFF */ in qla8044_idc_unlock()
450 int timeout = 0; in qla8044_flash_lock() local
453 struct qla_hw_data *ha = vha->hw; in qla8044_flash_lock()
460 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) { in qla8044_flash_lock()
465 __func__, ha->portnum, lock_owner); in qla8044_flash_lock()
471 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum); in qla8044_flash_lock()
478 struct qla_hw_data *ha = vha->hw; in qla8044_flash_unlock()
565 scsi_block_requests(vha->host); in qla8044_read_optrom_data()
572 scsi_unblock_requests(vha->host); in qla8044_read_optrom_data()
581 struct qla_hw_data *ha = vha->hw; in qla8044_need_reset()
586 rval = drv_state & (1 << ha->portnum); in qla8044_need_reset()
588 if (ha->flags.eeh_busy && drv_active) in qla8044_need_reset()
594 * qla8044_write_list - Write the value (p_entry->arg2) to address specified
595 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
612 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla8044_write_list()
613 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2); in qla8044_write_list()
614 if (p_hdr->delay) in qla8044_write_list()
615 udelay((uint32_t)(p_hdr->delay)); in qla8044_write_list()
620 * qla8044_read_write_list - Read from address specified by p_entry->arg1,
621 * write value read to address specified by p_entry->arg2, for all entries in
622 * header with delay of p_hdr->delay between entries.
638 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla8044_read_write_list()
639 qla8044_read_write_crb_reg(vha, p_entry->arg1, in qla8044_read_write_list()
640 p_entry->arg2); in qla8044_read_write_list()
641 if (p_hdr->delay) in qla8044_read_write_list()
642 udelay((uint32_t)(p_hdr->delay)); in qla8044_read_write_list()
647 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
656 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
689 } while (retries--); in qla8044_poll_reg()
693 vha->reset_tmplt.seq_error++; in qla8044_poll_reg()
703 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
704 * register specified by p_entry->arg1 and compare (value AND test_mask) with
705 * test_result to validate it. Wait for p_hdr->delay between processing entries.
730 delay = (long)p_hdr->delay; in qla8044_poll_list()
733 for (i = 0; i < p_hdr->count; i++, p_entry++) in qla8044_poll_list()
734 qla8044_poll_reg(vha, p_entry->arg1, in qla8044_poll_list()
735 delay, p_poll->test_mask, p_poll->test_value); in qla8044_poll_list()
737 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla8044_poll_list()
740 p_entry->arg1, delay, in qla8044_poll_list()
741 p_poll->test_mask, in qla8044_poll_list()
742 p_poll->test_value)) { in qla8044_poll_list()
749 p_entry->arg1, &value); in qla8044_poll_list()
751 p_entry->arg2, &value); in qla8044_poll_list()
759 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
760 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
782 delay = (long)p_hdr->delay; in qla8044_poll_write_list()
784 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla8044_poll_write_list()
786 p_entry->dr_addr, p_entry->dr_value); in qla8044_poll_write_list()
788 p_entry->ar_addr, p_entry->ar_value); in qla8044_poll_write_list()
791 p_entry->ar_addr, delay, in qla8044_poll_write_list()
792 p_poll->test_mask, in qla8044_poll_write_list()
793 p_poll->test_value)) { in qla8044_poll_write_list()
795 "%s: Timeout Error: poll list, ", in qla8044_poll_write_list()
799 vha->reset_tmplt.seq_index); in qla8044_poll_write_list()
806 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
807 * value, write value to p_entry->arg2. Process entries with p_hdr->delay
828 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla8044_read_modify_write()
829 qla8044_rmw_crb_reg(vha, p_entry->arg1, in qla8044_read_modify_write()
830 p_entry->arg2, p_rmw_hdr); in qla8044_read_modify_write()
831 if (p_hdr->delay) in qla8044_read_modify_write()
832 udelay((uint32_t)(p_hdr->delay)); in qla8044_read_modify_write()
837 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
848 if (p_hdr->delay) in qla8044_pause()
849 mdelay((uint32_t)((long)p_hdr->delay)); in qla8044_pause()
853 * qla8044_template_end - Indicates end of reset sequence processing.
863 vha->reset_tmplt.template_end = 1; in qla8044_template_end()
865 if (vha->reset_tmplt.seq_error == 0) { in qla8044_template_end()
870 "%s: Reset sequence completed with some timeout " in qla8044_template_end()
876 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
877 * if (value & test_mask != test_value) re-read till timeout value expires,
901 delay = (long)p_hdr->delay; in qla8044_poll_read_list()
903 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla8044_poll_read_list()
904 qla8044_wr_reg_indirect(vha, p_entry->ar_addr, in qla8044_poll_read_list()
905 p_entry->ar_value); in qla8044_poll_read_list()
907 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay, in qla8044_poll_read_list()
908 p_poll->test_mask, p_poll->test_value)) { in qla8044_poll_read_list()
910 "%s: Timeout Error: poll " in qla8044_poll_read_list()
915 vha->reset_tmplt.seq_index); in qla8044_poll_read_list()
917 index = vha->reset_tmplt.array_index; in qla8044_poll_read_list()
919 p_entry->dr_addr, &value); in qla8044_poll_read_list()
920 vha->reset_tmplt.array[index++] = value; in qla8044_poll_read_list()
922 vha->reset_tmplt.array_index = 1; in qla8044_poll_read_list()
929 * qla8031_process_reset_template - Process all entries in reset template
932 * size of the entry, number of entries in sub-sequence and delay in microsecs
933 * or timeout in millisecs.
947 vha->reset_tmplt.seq_end = 0; in qla8044_process_reset_template()
948 vha->reset_tmplt.template_end = 0; in qla8044_process_reset_template()
949 entries = vha->reset_tmplt.hdr->entries; in qla8044_process_reset_template()
950 index = vha->reset_tmplt.seq_index; in qla8044_process_reset_template()
952 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) { in qla8044_process_reset_template()
954 switch (p_hdr->cmd) { in qla8044_process_reset_template()
976 vha->reset_tmplt.seq_end = 1; in qla8044_process_reset_template()
987 "entry = %d\n", __func__, p_hdr->cmd, index); in qla8044_process_reset_template()
993 p_entry += p_hdr->size; in qla8044_process_reset_template()
995 vha->reset_tmplt.seq_index = index; in qla8044_process_reset_template()
1002 vha->reset_tmplt.init_offset); in qla8044_process_init_seq()
1003 if (vha->reset_tmplt.seq_end != 1) in qla8044_process_init_seq()
1005 "%s: Abrupt INIT Sub-Sequence end.\n", in qla8044_process_init_seq()
1012 vha->reset_tmplt.seq_index = 0; in qla8044_process_stop_seq()
1013 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset); in qla8044_process_stop_seq()
1014 if (vha->reset_tmplt.seq_end != 1) in qla8044_process_stop_seq()
1016 "%s: Abrupt STOP Sub-Sequence end.\n", __func__); in qla8044_process_stop_seq()
1022 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset); in qla8044_process_start_seq()
1023 if (vha->reset_tmplt.template_end != 1) in qla8044_process_start_seq()
1025 "%s: Abrupt START Sub-Sequence end.\n", in qla8044_process_start_seq()
1039 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1); in qla8044_lockless_flash_read_u32()
1060 (QLA8044_FLASH_SECTOR_SIZE - 1)) { in qla8044_lockless_flash_read_u32()
1075 if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) { in qla8044_lockless_flash_read_u32()
1111 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1118 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1127 struct qla_hw_data *ha = vha->hw; in qla8044_ms_mem_write_128b()
1129 /* Only 128-bit aligned access */ in qla8044_ms_mem_write_128b()
1134 write_lock_irqsave(&ha->hw_lock, flags); in qla8044_ms_mem_write_128b()
1199 "%s: MS memory write failed!\n", in qla8044_ms_mem_write_128b()
1207 write_unlock_irqrestore(&ha->hw_lock, flags); in qla8044_ms_mem_write_128b()
1220 struct qla_hw_data *ha = vha->hw; in qla8044_copy_bootloader()
1252 /* 128 bit/16 byte write to MS memory */ in qla8044_copy_bootloader()
1257 "%s: Error writing F/W to MS !!!\n", __func__); in qla8044_copy_bootloader()
1261 "%s: Wrote F/W (size %d) to MS !!!\n", in qla8044_copy_bootloader()
1275 struct qla_hw_data *ha = vha->hw; in qla8044_restart()
1308 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1313 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1320 struct qla_hw_data *ha = vha->hw; in qla8044_check_cmd_peg_status()
1332 } while (--retries); in qla8044_check_cmd_peg_status()
1367 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev); in qla8044_clear_drv_active()
1370 drv_active &= ~(1 << (ha->portnum)); in qla8044_clear_drv_active()
1374 __func__, vha->host_no, drv_active); in qla8044_clear_drv_active()
1380 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1393 struct qla_hw_data *ha = vha->hw; in qla8044_device_bootstrap()
1414 if (ha->flags.isp82xx_fw_hung) in qla8044_device_bootstrap()
1420 "%s: HW State: INITIALIZING\n", __func__); in qla8044_device_bootstrap()
1430 "%s: HW State: FAILED\n", __func__); in qla8044_device_bootstrap()
1443 ha->fw_dumped = false; in qla8044_device_bootstrap()
1448 "%s: HW State: READY\n", __func__); in qla8044_device_bootstrap()
1454 /*-------------------------Reset Sequence Functions-----------------------*/
1460 if (!vha->reset_tmplt.buff) { in qla8044_dump_reset_seq_hdr()
1466 phdr = vha->reset_tmplt.buff; in qla8044_dump_reset_seq_hdr()
1478 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1482 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1488 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff; in qla8044_reset_seq_checksum_test()
1489 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t); in qla8044_reset_seq_checksum_test()
1491 while (u16_count-- > 0) in qla8044_reset_seq_checksum_test()
1508 * qla8044_read_reset_template - Read Reset Template from Flash, validate
1509 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1519 vha->reset_tmplt.seq_error = 0; in qla8044_read_reset_template()
1520 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE); in qla8044_read_reset_template()
1521 if (vha->reset_tmplt.buff == NULL) { in qla8044_read_reset_template()
1528 p_buff = vha->reset_tmplt.buff; in qla8044_read_reset_template()
1545 vha->reset_tmplt.hdr = in qla8044_read_reset_template()
1546 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff; in qla8044_read_reset_template()
1549 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); in qla8044_read_reset_template()
1551 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) { in qla8044_read_reset_template()
1559 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size; in qla8044_read_reset_template()
1560 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size; in qla8044_read_reset_template()
1561 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size - in qla8044_read_reset_template()
1562 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t); in qla8044_read_reset_template()
1566 __func__, vha->reset_tmplt.hdr->size); in qla8044_read_reset_template()
1587 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff + in qla8044_read_reset_template()
1588 vha->reset_tmplt.hdr->init_seq_offset; in qla8044_read_reset_template()
1590 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff + in qla8044_read_reset_template()
1591 vha->reset_tmplt.hdr->start_seq_offset; in qla8044_read_reset_template()
1593 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff + in qla8044_read_reset_template()
1594 vha->reset_tmplt.hdr->hdr_size; in qla8044_read_reset_template()
1601 vfree(vha->reset_tmplt.buff); in qla8044_read_reset_template()
1611 struct qla_hw_data *ha = vha->hw; in qla8044_set_idc_dontreset()
1624 struct qla_hw_data *ha = vha->hw; in qla8044_set_rst_ready()
1630 drv_state |= (1 << ha->portnum); in qla8044_set_rst_ready()
1634 __func__, vha->host_no, drv_state); in qla8044_set_rst_ready()
1639 * qla8044_need_reset_handler - Code to start reset sequence
1649 struct qla_hw_data *ha = vha->hw; in qla8044_need_reset_handler()
1654 if (vha->flags.online) { in qla8044_need_reset_handler()
1657 ha->isp_ops->get_flash_version(vha, vha->req->ring); in qla8044_need_reset_handler()
1658 ha->isp_ops->nvram_config(vha); in qla8044_need_reset_handler()
1671 __func__, vha->host_no, drv_state, drv_active, dev_state); in qla8044_need_reset_handler()
1676 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); in qla8044_need_reset_handler()
1681 "%s: Function %d: Reset Ack Timeout!, drv_state: 0x%08x, drv_active: 0x%08x\n", in qla8044_need_reset_handler()
1682 __func__, ha->portnum, drv_state, drv_active); in qla8044_need_reset_handler()
1702 "%s(%ld): Function %d turning off drv_active of non-acking function 0x%x\n", in qla8044_need_reset_handler()
1703 __func__, vha->host_no, ha->portnum, in qla8044_need_reset_handler()
1713 if ((ha->flags.nic_core_reset_owner) && in qla8044_need_reset_handler()
1715 ha->flags.nic_core_reset_owner = 0; in qla8044_need_reset_handler()
1722 if (!(drv_active & (1 << ha->portnum))) { in qla8044_need_reset_handler()
1723 ha->flags.nic_core_reset_owner = 0; in qla8044_need_reset_handler()
1731 if (ha->flags.nic_core_reset_owner || in qla8044_need_reset_handler()
1733 ha->flags.nic_core_reset_owner = 0; in qla8044_need_reset_handler()
1742 struct qla_hw_data *ha = vha->hw; in qla8044_set_drv_active()
1748 drv_active |= (1 << ha->portnum); in qla8044_set_drv_active()
1752 __func__, vha->host_no, drv_active); in qla8044_set_drv_active()
1760 struct qla_hw_data *ha = vha->hw; in qla8044_check_drv_active()
1763 if (drv_active & (1 << ha->portnum)) in qla8044_check_drv_active()
1773 struct qla_hw_data *ha = vha->hw; in qla8044_clear_idc_dontreset()
1789 struct qla_hw_data *ha = vha->hw; in qla8044_set_idc_ver()
1792 if (drv_active == (1 << ha->portnum)) { in qla8044_set_idc_ver()
1820 idc_ver &= ~(0x03 << (ha->portnum * 2)); in qla8044_set_idc_ver()
1821 idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2)); in qla8044_set_idc_ver()
1833 struct qla_hw_data *ha = vha->hw; in qla8044_update_idc_reg()
1835 if (vha->flags.init_done) in qla8044_update_idc_reg()
1846 if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba) in qla8044_update_idc_reg()
1859 * qla8044_need_qsnt_handler - Code to start qsnt
1867 struct qla_hw_data *ha = vha->hw; in qla8044_need_qsnt_handler()
1869 if (vha->flags.online) in qla8044_need_qsnt_handler()
1890 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); in qla8044_need_qsnt_handler()
1895 "Timeout waiting for quiescent ack!!!\n"); in qla8044_need_qsnt_handler()
1916 "%s: HW State: QUIESCENT\n", __func__); in qla8044_need_qsnt_handler()
1921 * qla8044_device_state_handler - Adapter state machine
1932 struct qla_hw_data *ha = vha->hw; in qla8044_device_state_handler()
1944 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); in qla8044_device_state_handler()
1969 ha->flags.nic_core_reset_owner = 0; in qla8044_device_state_handler()
1989 /* Reset the init timeout after qsnt handler */ in qla8044_device_state_handler()
1991 (ha->fcoe_reset_timeout * HZ); in qla8044_device_state_handler()
1995 "HW State: QUIESCENT\n"); in qla8044_device_state_handler()
2001 /* Reset the init timeout after qsnt handler */ in qla8044_device_state_handler()
2003 (ha->fcoe_reset_timeout * HZ); in qla8044_device_state_handler()
2006 ha->flags.nic_core_reset_owner = 0; in qla8044_device_state_handler()
2028 * qla8044_check_temp - Check the ISP82XX temperature.
2068 * qla8044_check_fw_alive - Check firmware health
2088 vha->host_no, __func__); in qla8044_check_fw_alive()
2092 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { in qla8044_check_fw_alive()
2093 vha->seconds_since_last_heartbeat++; in qla8044_check_fw_alive()
2095 if (vha->seconds_since_last_heartbeat == 2) { in qla8044_check_fw_alive()
2096 vha->seconds_since_last_heartbeat = 0; in qla8044_check_fw_alive()
2104 "Dumping hw/fw registers:\n" in qla8044_check_fw_alive()
2107 vha->host_no, __func__, halt_status1, in qla8044_check_fw_alive()
2112 vha->seconds_since_last_heartbeat = 0; in qla8044_check_fw_alive()
2114 vha->fw_heartbeat_counter = fw_heartbeat_counter; in qla8044_check_fw_alive()
2123 struct qla_hw_data *ha = vha->hw; in qla8044_watchdog()
2126 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || in qla8044_watchdog()
2127 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) { in qla8044_watchdog()
2131 ha->flags.isp82xx_fw_hung = 1; in qla8044_watchdog()
2138 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); in qla8044_watchdog()
2139 ha->flags.isp82xx_fw_hung = 1; in qla8044_watchdog()
2142 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { in qla8044_watchdog()
2144 "%s: HW State: NEED RESET!\n", in qla8044_watchdog()
2146 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); in qla8044_watchdog()
2149 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { in qla8044_watchdog()
2151 "%s: HW State: NEED QUIES detected!\n", in qla8044_watchdog()
2153 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); in qla8044_watchdog()
2157 if (ha->flags.isp82xx_fw_hung) { in qla8044_watchdog()
2177 &vha->dpc_flags); in qla8044_watchdog()
2182 &vha->dpc_flags); in qla8044_watchdog()
2192 &vha->dpc_flags); in qla8044_watchdog()
2212 struct qla_hw_data *ha = vha->hw; in qla8044_minidump_process_control()
2216 ha->md_tmplt_hdr; in qla8044_minidump_process_control()
2219 crb_addr = crb_entry->addr; in qla8044_minidump_process_control()
2220 for (i = 0; i < crb_entry->op_count; i++) { in qla8044_minidump_process_control()
2221 opcode = crb_entry->crb_ctrl.opcode; in qla8044_minidump_process_control()
2225 crb_entry->value_1); in qla8044_minidump_process_control()
2235 read_value &= crb_entry->value_2; in qla8044_minidump_process_control()
2237 read_value |= crb_entry->value_3; in qla8044_minidump_process_control()
2244 read_value |= crb_entry->value_3; in qla8044_minidump_process_control()
2248 poll_time = crb_entry->crb_strd.poll_timeout; in qla8044_minidump_process_control()
2253 if ((read_value & crb_entry->value_2) == in qla8044_minidump_process_control()
2254 crb_entry->value_1) { in qla8044_minidump_process_control()
2268 if (crb_entry->crb_strd.state_index_a) { in qla8044_minidump_process_control()
2269 index = crb_entry->crb_strd.state_index_a; in qla8044_minidump_process_control()
2270 addr = tmplt_hdr->saved_state_array[index]; in qla8044_minidump_process_control()
2276 index = crb_entry->crb_ctrl.state_index_v; in qla8044_minidump_process_control()
2277 tmplt_hdr->saved_state_array[index] = read_value; in qla8044_minidump_process_control()
2281 if (crb_entry->crb_strd.state_index_a) { in qla8044_minidump_process_control()
2282 index = crb_entry->crb_strd.state_index_a; in qla8044_minidump_process_control()
2283 addr = tmplt_hdr->saved_state_array[index]; in qla8044_minidump_process_control()
2288 if (crb_entry->crb_ctrl.state_index_v) { in qla8044_minidump_process_control()
2289 index = crb_entry->crb_ctrl.state_index_v; in qla8044_minidump_process_control()
2291 tmplt_hdr->saved_state_array[index]; in qla8044_minidump_process_control()
2293 read_value = crb_entry->value_1; in qla8044_minidump_process_control()
2300 index = crb_entry->crb_ctrl.state_index_v; in qla8044_minidump_process_control()
2301 read_value = tmplt_hdr->saved_state_array[index]; in qla8044_minidump_process_control()
2302 read_value <<= crb_entry->crb_ctrl.shl; in qla8044_minidump_process_control()
2303 read_value >>= crb_entry->crb_ctrl.shr; in qla8044_minidump_process_control()
2304 if (crb_entry->value_2) in qla8044_minidump_process_control()
2305 read_value &= crb_entry->value_2; in qla8044_minidump_process_control()
2306 read_value |= crb_entry->value_3; in qla8044_minidump_process_control()
2307 read_value += crb_entry->value_1; in qla8044_minidump_process_control()
2308 tmplt_hdr->saved_state_array[index] = read_value; in qla8044_minidump_process_control()
2310 crb_addr += crb_entry->crb_strd.addr_stride; in qla8044_minidump_process_control()
2325 r_addr = crb_hdr->addr; in qla8044_minidump_process_rdcrb()
2326 r_stride = crb_hdr->crb_strd.addr_stride; in qla8044_minidump_process_rdcrb()
2327 loop_cnt = crb_hdr->op_count; in qla8044_minidump_process_rdcrb()
2347 struct qla_hw_data *ha = vha->hw; in qla8044_minidump_process_rdmem()
2351 r_addr = m_hdr->read_addr; in qla8044_minidump_process_rdmem()
2352 loop_cnt = m_hdr->read_data_size/16; in qla8044_minidump_process_rdmem()
2356 __func__, r_addr, m_hdr->read_data_size); in qla8044_minidump_process_rdmem()
2365 if (m_hdr->read_data_size % 16) { in qla8044_minidump_process_rdmem()
2368 __func__, m_hdr->read_data_size); in qla8044_minidump_process_rdmem()
2374 __func__, r_addr, m_hdr->read_data_size, loop_cnt); in qla8044_minidump_process_rdmem()
2376 write_lock_irqsave(&ha->hw_lock, flags); in qla8044_minidump_process_rdmem()
2394 write_unlock_irqrestore(&ha->hw_lock, flags); in qla8044_minidump_process_rdmem()
2406 write_unlock_irqrestore(&ha->hw_lock, flags); in qla8044_minidump_process_rdmem()
2426 fl_addr = rom_hdr->read_addr; in qla8044_minidump_process_rdrom()
2427 u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t); in qla8044_minidump_process_rdrom()
2450 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; in qla8044_mark_entry_skipped()
2453 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla8044_mark_entry_skipped()
2454 vha->host_no, index, entry_hdr->entry_type, in qla8044_mark_entry_skipped()
2455 entry_hdr->d_ctrl.entry_capture_mask); in qla8044_mark_entry_skipped()
2474 loop_count = cache_hdr->op_count; in qla8044_minidump_process_l2tag()
2475 r_addr = cache_hdr->read_addr; in qla8044_minidump_process_l2tag()
2476 c_addr = cache_hdr->control_addr; in qla8044_minidump_process_l2tag()
2477 c_value_w = cache_hdr->cache_ctrl.write_value; in qla8044_minidump_process_l2tag()
2479 t_r_addr = cache_hdr->tag_reg_addr; in qla8044_minidump_process_l2tag()
2480 t_value = cache_hdr->addr_ctrl.init_tag_value; in qla8044_minidump_process_l2tag()
2481 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; in qla8044_minidump_process_l2tag()
2482 p_wait = cache_hdr->cache_ctrl.poll_wait; in qla8044_minidump_process_l2tag()
2483 p_mask = cache_hdr->cache_ctrl.poll_mask; in qla8044_minidump_process_l2tag()
2508 addr += cache_hdr->read_ctrl.read_addr_stride; in qla8044_minidump_process_l2tag()
2510 t_value += cache_hdr->addr_ctrl.tag_value_stride; in qla8044_minidump_process_l2tag()
2527 loop_count = cache_hdr->op_count; in qla8044_minidump_process_l1cache()
2528 r_addr = cache_hdr->read_addr; in qla8044_minidump_process_l1cache()
2529 c_addr = cache_hdr->control_addr; in qla8044_minidump_process_l1cache()
2530 c_value_w = cache_hdr->cache_ctrl.write_value; in qla8044_minidump_process_l1cache()
2532 t_r_addr = cache_hdr->tag_reg_addr; in qla8044_minidump_process_l1cache()
2533 t_value = cache_hdr->addr_ctrl.init_tag_value; in qla8044_minidump_process_l1cache()
2534 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; in qla8044_minidump_process_l1cache()
2543 addr += cache_hdr->read_ctrl.read_addr_stride; in qla8044_minidump_process_l1cache()
2545 t_value += cache_hdr->addr_ctrl.tag_value_stride; in qla8044_minidump_process_l1cache()
2557 struct qla_hw_data *ha = vha->hw; in qla8044_minidump_process_rdocm()
2562 r_addr = ocm_hdr->read_addr; in qla8044_minidump_process_rdocm()
2563 r_stride = ocm_hdr->read_addr_stride; in qla8044_minidump_process_rdocm()
2564 loop_cnt = ocm_hdr->op_count; in qla8044_minidump_process_rdocm()
2571 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); in qla8044_minidump_process_rdocm()
2593 r_addr = mux_hdr->read_addr; in qla8044_minidump_process_rdmux()
2594 s_addr = mux_hdr->select_addr; in qla8044_minidump_process_rdmux()
2595 s_stride = mux_hdr->select_value_stride; in qla8044_minidump_process_rdmux()
2596 s_value = mux_hdr->select_value; in qla8044_minidump_process_rdmux()
2597 loop_cnt = mux_hdr->op_count; in qla8044_minidump_process_rdmux()
2622 s_addr = q_hdr->select_addr; in qla8044_minidump_process_queue()
2623 r_cnt = q_hdr->rd_strd.read_addr_cnt; in qla8044_minidump_process_queue()
2624 r_stride = q_hdr->rd_strd.read_addr_stride; in qla8044_minidump_process_queue()
2625 loop_cnt = q_hdr->op_count; in qla8044_minidump_process_queue()
2629 r_addr = q_hdr->read_addr; in qla8044_minidump_process_queue()
2635 qid += q_hdr->q_strd.queue_id_stride; in qla8044_minidump_process_queue()
2652 s_addr = pollrd_hdr->select_addr; in qla8044_minidump_process_pollrd()
2653 r_addr = pollrd_hdr->read_addr; in qla8044_minidump_process_pollrd()
2654 s_value = pollrd_hdr->select_value; in qla8044_minidump_process_pollrd()
2655 s_stride = pollrd_hdr->select_value_stride; in qla8044_minidump_process_pollrd()
2657 poll_wait = pollrd_hdr->poll_wait; in qla8044_minidump_process_pollrd()
2658 poll_mask = pollrd_hdr->poll_mask; in qla8044_minidump_process_pollrd()
2660 for (i = 0; i < pollrd_hdr->op_count; i++) { in qla8044_minidump_process_pollrd()
2662 poll_wait = pollrd_hdr->poll_wait; in qla8044_minidump_process_pollrd()
2669 if (--poll_wait == 0) { in qla8044_minidump_process_pollrd()
2671 "%s: TIMEOUT\n", __func__); in qla8044_minidump_process_pollrd()
2699 sel_val1 = rdmux2_hdr->select_value_1; in qla8044_minidump_process_rdmux2()
2700 sel_val2 = rdmux2_hdr->select_value_2; in qla8044_minidump_process_rdmux2()
2701 sel_addr1 = rdmux2_hdr->select_addr_1; in qla8044_minidump_process_rdmux2()
2702 sel_addr2 = rdmux2_hdr->select_addr_2; in qla8044_minidump_process_rdmux2()
2703 sel_val_mask = rdmux2_hdr->select_value_mask; in qla8044_minidump_process_rdmux2()
2704 read_addr = rdmux2_hdr->read_addr; in qla8044_minidump_process_rdmux2()
2706 for (i = 0; i < rdmux2_hdr->op_count; i++) { in qla8044_minidump_process_rdmux2()
2725 sel_val1 += rdmux2_hdr->select_value_stride; in qla8044_minidump_process_rdmux2()
2726 sel_val2 += rdmux2_hdr->select_value_stride; in qla8044_minidump_process_rdmux2()
2743 addr_1 = poll_hdr->addr_1; in qla8044_minidump_process_pollrdmwr()
2744 addr_2 = poll_hdr->addr_2; in qla8044_minidump_process_pollrdmwr()
2745 value_1 = poll_hdr->value_1; in qla8044_minidump_process_pollrdmwr()
2746 value_2 = poll_hdr->value_2; in qla8044_minidump_process_pollrdmwr()
2747 poll_mask = poll_hdr->poll_mask; in qla8044_minidump_process_pollrdmwr()
2751 poll_wait = poll_hdr->poll_wait; in qla8044_minidump_process_pollrdmwr()
2759 if (--poll_wait == 0) { in qla8044_minidump_process_pollrdmwr()
2761 "%s: TIMEOUT\n", __func__); in qla8044_minidump_process_pollrdmwr()
2768 data &= poll_hdr->modify_mask; in qla8044_minidump_process_pollrdmwr()
2772 poll_wait = poll_hdr->poll_wait; in qla8044_minidump_process_pollrdmwr()
2780 if (--poll_wait == 0) { in qla8044_minidump_process_pollrdmwr()
2812 struct qla_hw_data *ha = vha->hw; in qla8044_check_dma_engine_state()
2818 tmplt_hdr = ha->md_tmplt_hdr; in qla8044_check_dma_engine_state()
2820 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; in qla8044_check_dma_engine_state()
2824 /* Read the pex-dma's command-status-and-control register. */ in qla8044_check_dma_engine_state()
2831 /* Check if requested pex-dma engine is available. */ in qla8044_check_dma_engine_state()
2842 struct qla_hw_data *ha = vha->hw; in qla8044_start_pex_dma()
2848 tmplt_hdr = ha->md_tmplt_hdr; in qla8044_start_pex_dma()
2850 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; in qla8044_start_pex_dma()
2856 m_hdr->desc_card_addr); in qla8044_start_pex_dma()
2867 m_hdr->start_dma_cmd); in qla8044_start_pex_dma()
2885 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ in qla8044_start_pex_dma()
2899 struct qla_hw_data *ha = vha->hw; in qla8044_minidump_pex_dma_read()
2911 "DMA engine not available. Fallback to rdmem-read.\n"); in qla8044_minidump_pex_dma_read()
2917 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, in qla8044_minidump_pex_dma_read()
2925 /* Prepare pex-dma descriptor to be written to MS memory. */ in qla8044_minidump_pex_dma_read()
2926 /* dma-desc-cmd layout: in qla8044_minidump_pex_dma_read()
2927 * 0-3: dma-desc-cmd 0-3 in qla8044_minidump_pex_dma_read()
2928 * 4-7: pcid function number in qla8044_minidump_pex_dma_read()
2929 * 8-15: dma-desc-cmd 8-15 in qla8044_minidump_pex_dma_read()
2931 * cmd.read_data_size: amount of data-chunk to be read. in qla8044_minidump_pex_dma_read()
2933 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); in qla8044_minidump_pex_dma_read()
2935 ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); in qla8044_minidump_pex_dma_read()
2942 * Perform rdmem operation using pex-dma. in qla8044_minidump_pex_dma_read()
2945 while (read_size < m_hdr->read_data_size) { in qla8044_minidump_pex_dma_read()
2946 if (m_hdr->read_data_size - read_size < in qla8044_minidump_pex_dma_read()
2948 chunk_size = (m_hdr->read_data_size - read_size); in qla8044_minidump_pex_dma_read()
2952 dma_desc.src_addr = m_hdr->read_addr + read_size; in qla8044_minidump_pex_dma_read()
2954 /* Prepare: Write pex-dma descriptor to MS memory. */ in qla8044_minidump_pex_dma_read()
2956 m_hdr->desc_card_addr, (uint32_t *)&dma_desc, in qla8044_minidump_pex_dma_read()
2960 "%s: Error writing rdmem-dma-init to MS !!!\n", in qla8044_minidump_pex_dma_read()
2965 "%s: Dma-descriptor: Instruct for rdmem dma " in qla8044_minidump_pex_dma_read()
2968 /* Execute: Start pex-dma operation. */ in qla8044_minidump_pex_dma_read()
2982 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE, in qla8044_minidump_pex_dma_read()
3003 addr1 = rddfe->addr_1; in qla8044_minidump_process_rddfe()
3004 value = rddfe->value; in qla8044_minidump_process_rddfe()
3005 stride = rddfe->stride; in qla8044_minidump_process_rddfe()
3006 stride2 = rddfe->stride2; in qla8044_minidump_process_rddfe()
3007 count = rddfe->count; in qla8044_minidump_process_rddfe()
3009 poll = rddfe->poll; in qla8044_minidump_process_rddfe()
3010 mask = rddfe->mask; in qla8044_minidump_process_rddfe()
3011 modify_mask = rddfe->modify_mask; in qla8044_minidump_process_rddfe()
3028 "%s: TIMEOUT\n", __func__); in qla8044_minidump_process_rddfe()
3048 "%s: TIMEOUT\n", __func__); in qla8044_minidump_process_rddfe()
3064 "%s: TIMEOUT\n", __func__); in qla8044_minidump_process_rddfe()
3080 return -1; in qla8044_minidump_process_rddfe()
3100 addr1 = rdmdio->addr_1; in qla8044_minidump_process_rdmdio()
3101 addr2 = rdmdio->addr_2; in qla8044_minidump_process_rdmdio()
3102 value1 = rdmdio->value_1; in qla8044_minidump_process_rdmdio()
3103 stride1 = rdmdio->stride_1; in qla8044_minidump_process_rdmdio()
3104 stride2 = rdmdio->stride_2; in qla8044_minidump_process_rdmdio()
3105 count = rdmdio->count; in qla8044_minidump_process_rdmdio()
3107 mask = rdmdio->mask; in qla8044_minidump_process_rdmdio()
3108 value2 = rdmdio->value_2; in qla8044_minidump_process_rdmdio()
3115 if (ret == -1) in qla8044_minidump_process_rdmdio()
3118 addr4 = addr2 - stride1; in qla8044_minidump_process_rdmdio()
3121 if (ret == -1) in qla8044_minidump_process_rdmdio()
3124 addr5 = addr2 - (2 * stride1); in qla8044_minidump_process_rdmdio()
3127 if (ret == -1) in qla8044_minidump_process_rdmdio()
3130 addr6 = addr2 - (3 * stride1); in qla8044_minidump_process_rdmdio()
3133 if (ret == -1) in qla8044_minidump_process_rdmdio()
3138 if (ret == -1) in qla8044_minidump_process_rdmdio()
3141 addr7 = addr2 - (4 * stride1); in qla8044_minidump_process_rdmdio()
3143 if (data == -1) in qla8044_minidump_process_rdmdio()
3148 stride2 = rdmdio->stride_2; in qla8044_minidump_process_rdmdio()
3159 return -1; in qla8044_minidump_process_rdmdio()
3170 addr1 = pollwr_hdr->addr_1; in qla8044_minidump_process_pollwr()
3171 addr2 = pollwr_hdr->addr_2; in qla8044_minidump_process_pollwr()
3172 value1 = pollwr_hdr->value_1; in qla8044_minidump_process_pollwr()
3173 value2 = pollwr_hdr->value_2; in qla8044_minidump_process_pollwr()
3175 poll = pollwr_hdr->poll; in qla8044_minidump_process_pollwr()
3186 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__); in qla8044_minidump_process_pollwr()
3205 return -1; in qla8044_minidump_process_pollwr()
3210 * qla8044_collect_md_data - Retrieve firmware minidump data.
3224 struct qla_hw_data *ha = vha->hw; in qla8044_collect_md_data()
3226 if (!ha->md_dump) { in qla8044_collect_md_data()
3229 __func__, vha->host_no); in qla8044_collect_md_data()
3233 if (ha->fw_dumped) { in qla8044_collect_md_data()
3236 "-- ignoring request.\n", ha->fw_dump); in qla8044_collect_md_data()
3240 ha->fw_dumped = false; in qla8044_collect_md_data()
3242 if (!ha->md_tmplt_hdr || !ha->md_dump) { in qla8044_collect_md_data()
3269 ha->md_tmplt_hdr; in qla8044_collect_md_data()
3270 data_ptr = (uint32_t *)((uint8_t *)ha->md_dump); in qla8044_collect_md_data()
3271 num_entry_hdr = tmplt_hdr->num_of_entries; in qla8044_collect_md_data()
3274 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); in qla8044_collect_md_data()
3276 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; in qla8044_collect_md_data()
3285 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; in qla8044_collect_md_data()
3294 __func__, ha->md_dump_size, ha->md_dump_size); in qla8044_collect_md_data()
3299 tmplt_hdr->driver_timestamp = timestamp; in qla8044_collect_md_data()
3302 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); in qla8044_collect_md_data()
3303 tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] = in qla8044_collect_md_data()
3304 tmplt_hdr->ocm_window_reg[ha->portnum]; in qla8044_collect_md_data()
3306 /* Walk through the entry headers - validate/perform required action */ in qla8044_collect_md_data()
3308 if (data_collected > ha->md_dump_size) { in qla8044_collect_md_data()
3312 data_collected, ha->md_dump_size); in qla8044_collect_md_data()
3316 if (!(entry_hdr->d_ctrl.entry_capture_mask & in qla8044_collect_md_data()
3318 entry_hdr->d_ctrl.driver_flags |= in qla8044_collect_md_data()
3326 (ha->md_dump_size - data_collected)); in qla8044_collect_md_data()
3331 switch (entry_hdr->entry_type) { in qla8044_collect_md_data()
3439 data_collected = (uint8_t *)data_ptr - in qla8044_collect_md_data()
3440 (uint8_t *)((uint8_t *)ha->md_dump); in qla8044_collect_md_data()
3446 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); in qla8044_collect_md_data()
3449 if (data_collected != ha->md_dump_size) { in qla8044_collect_md_data()
3453 data_collected, ha->md_dump_size); in qla8044_collect_md_data()
3460 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); in qla8044_collect_md_data()
3461 ha->fw_dumped = true; in qla8044_collect_md_data()
3475 struct qla_hw_data *ha = vha->hw; in qla8044_get_minidump()
3478 ha->fw_dumped = true; in qla8044_get_minidump()
3479 ha->prev_minidump_failed = 0; in qla8044_get_minidump()
3484 ha->prev_minidump_failed = 1; in qla8044_get_minidump()
3495 while (retries--) { in qla8044_poll_flash_status_reg()
3523 cmd = vha->hw->fdt_wrt_sts_reg_cmd; in qla8044_write_flash_status_reg()
3564 struct qla_hw_data *ha = vha->hw; in qla8044_unprotect_flash()
3566 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable); in qla8044_unprotect_flash()
3581 struct qla_hw_data *ha = vha->hw; in qla8044_protect_flash()
3583 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable); in qla8044_protect_flash()
3616 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd); in qla8044_erase_flash_sector()
3638 * qla8044_flash_write_u32 - Write data to flash
3644 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3717 dwords--; in qla8044_write_flash_buffer_mode()
3723 /* Second to N-1 DWORDS writes */ in qla8044_write_flash_buffer_mode()
3734 dwords--; in qla8044_write_flash_buffer_mode()
3811 scsi_block_requests(vha->host); in qla8044_write_optrom_data()
3843 "Reverting to slow-write.\n"); in qla8044_write_optrom_data()
3857 scsi_unblock_requests(vha->host); in qla8044_write_optrom_data()
3867 * qla8044_intr_handler() - Process interrupts for the ISP8044
3895 ha = rsp->hw; in qla8044_intr_handler()
3896 vha = pci_get_drvdata(ha->pdev); in qla8044_intr_handler()
3898 if (unlikely(pci_channel_offline(ha->pdev))) in qla8044_intr_handler()
3911 pf_bit = ha->portnum << 16; in qla8044_intr_handler()
3917 "ha->pf_bit = 0x%x\n", __func__, in qla8044_intr_handler()
3922 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger in qla8044_intr_handler()
3933 reg = &ha->iobase->isp82; in qla8044_intr_handler()
3934 spin_lock_irqsave(&ha->hardware_lock, flags); in qla8044_intr_handler()
3935 for (iter = 1; iter--; ) { in qla8044_intr_handler()
3937 if (rd_reg_dword(®->host_int)) { in qla8044_intr_handler()
3938 stat = rd_reg_dword(®->host_status); in qla8044_intr_handler()
3952 mb[1] = rd_reg_word(®->mailbox_out[1]); in qla8044_intr_handler()
3953 mb[2] = rd_reg_word(®->mailbox_out[2]); in qla8044_intr_handler()
3954 mb[3] = rd_reg_word(®->mailbox_out[3]); in qla8044_intr_handler()
3967 wrt_reg_dword(®->host_int, 0); in qla8044_intr_handler()
3971 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla8044_intr_handler()
3997 drv_state &= ~(1 << vha->hw->portnum); in qla8044_clear_rst_ready()
4009 struct qla_hw_data *ha = vha->hw; in qla8044_abort_isp()
4019 * non-reset-owner to force a reset. Non-reset-owner sets in qla8044_abort_isp()
4020 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset in qla8044_abort_isp()
4034 "HW State: NEED RESET\n"); in qla8044_abort_isp()
4052 ha->flags.isp82xx_fw_hung = 0; in qla8044_abort_isp()
4053 ha->flags.nic_core_reset_hdlr_active = 0; in qla8044_abort_isp()
4063 struct qla_hw_data *ha = vha->hw; in qla8044_fw_dump()
4065 if (!ha->allow_cna_fw_dump) in qla8044_fw_dump()
4068 scsi_block_requests(vha->host); in qla8044_fw_dump()
4069 ha->flags.isp82xx_no_md_cap = 1; in qla8044_fw_dump()
4074 scsi_unblock_requests(vha->host); in qla8044_fw_dump()