Lines Matching +full:0 +full:x000000
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define BLOCK_PROTECT_BITS 0x0F
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
33 ((off) & 0xf0000))
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
46 0x410000A8, 0x410000AC,
47 0x410000B8, 0x410000BC
111 {{{0, 0, 0, 0} } },
112 {{{1, 0x0100000, 0x0102000, 0x120000},
113 {1, 0x0110000, 0x0120000, 0x130000},
114 {1, 0x0120000, 0x0122000, 0x124000},
115 {1, 0x0130000, 0x0132000, 0x126000},
116 {1, 0x0140000, 0x0142000, 0x128000},
117 {1, 0x0150000, 0x0152000, 0x12a000},
118 {1, 0x0160000, 0x0170000, 0x110000},
119 {1, 0x0170000, 0x0172000, 0x12e000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x01e0000, 0x01e0800, 0x122000},
127 {0, 0x0000000, 0x0000000, 0x000000} } } ,
128 {{{1, 0x0200000, 0x0210000, 0x180000} } },
129 {{{0, 0, 0, 0} } },
130 {{{1, 0x0400000, 0x0401000, 0x169000} } },
131 {{{1, 0x0500000, 0x0510000, 0x140000} } },
132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
134 {{{1, 0x0800000, 0x0802000, 0x170000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {1, 0x08f0000, 0x08f2000, 0x172000} } },
150 {{{1, 0x0900000, 0x0902000, 0x174000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {1, 0x09f0000, 0x09f2000, 0x176000} } },
166 {{{0, 0x0a00000, 0x0a02000, 0x178000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
182 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
203 {{{1, 0x1100000, 0x1101000, 0x160000} } },
204 {{{1, 0x1200000, 0x1201000, 0x161000} } },
205 {{{1, 0x1300000, 0x1301000, 0x162000} } },
206 {{{1, 0x1400000, 0x1401000, 0x163000} } },
207 {{{1, 0x1500000, 0x1501000, 0x165000} } },
208 {{{1, 0x1600000, 0x1601000, 0x166000} } },
209 {{{0, 0, 0, 0} } },
210 {{{0, 0, 0, 0} } },
211 {{{0, 0, 0, 0} } },
212 {{{0, 0, 0, 0} } },
213 {{{0, 0, 0, 0} } },
214 {{{0, 0, 0, 0} } },
215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
218 {{{0} } },
219 {{{1, 0x2100000, 0x2102000, 0x120000},
220 {1, 0x2110000, 0x2120000, 0x130000},
221 {1, 0x2120000, 0x2122000, 0x124000},
222 {1, 0x2130000, 0x2132000, 0x126000},
223 {1, 0x2140000, 0x2142000, 0x128000},
224 {1, 0x2150000, 0x2152000, 0x12a000},
225 {1, 0x2160000, 0x2170000, 0x110000},
226 {1, 0x2170000, 0x2172000, 0x12e000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000} } },
235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{0} } },
237 {{{0} } },
238 {{{0} } },
239 {{{0} } },
240 {{{0} } },
241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
253 {{{0} } },
254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
260 {{{0} } },
261 {{{0} } },
262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
271 0,
275 0,
298 0,
301 0,
303 0,
306 0,
307 0,
308 0,
309 0,
310 0,
312 0,
323 0,
328 0,
332 0,
334 0,
374 ql_dbg(ql_dbg_p3p, vha, 0xb000, in qla82xx_pci_set_crbwindow_2M()
375 "%s: Written crbwin (0x%x) " in qla82xx_pci_set_crbwindow_2M()
376 "!= Read crbwin (0x%x), off=0x%lx.\n", in qla82xx_pci_set_crbwindow_2M()
394 return 0; in qla82xx_pci_get_crb_addr_2M()
407 return 0; in qla82xx_pci_get_crb_addr_2M()
417 int done = 0, timeout = 0; in qla82xx_crb_win_lock()
429 return 0; in qla82xx_crb_win_lock()
436 unsigned long flags = 0; in qla82xx_wr_32()
459 return 0; in qla82xx_wr_32()
466 unsigned long flags = 0; in qla82xx_rd_32()
498 int done, total = 0; in qla82xx_idc_lock()
514 return 0; in qla82xx_idc_lock()
535 return 0; in qla82xx_pci_mem_bound_check()
559 ql_dbg(ql_dbg_p3p, vha, 0xb003, in qla82xx_pci_set_window()
560 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", in qla82xx_pci_set_window()
568 if ((addr & 0x00ff800) == 0xff800) { in qla82xx_pci_set_window()
569 ql_log(ql_log_warn, vha, 0xb004, in qla82xx_pci_set_window()
579 temp1 = ((window & 0x1FF) << 7) | in qla82xx_pci_set_window()
580 ((window & 0x0FFFE0000) >> 17); in qla82xx_pci_set_window()
582 ql_log(ql_log_warn, vha, 0xb005, in qla82xx_pci_set_window()
583 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", in qla82xx_pci_set_window()
598 ql_log(ql_log_warn, vha, 0xb006, in qla82xx_pci_set_window()
599 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", in qla82xx_pci_set_window()
609 (qla82xx_pci_set_window_warning_count%64 == 0)) { in qla82xx_pci_set_window()
610 ql_log(ql_log_warn, vha, 0xb007, in qla82xx_pci_set_window()
640 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; in qla82xx_pci_is_same_window()
644 return 0; in qla82xx_pci_is_same_window()
652 int ret = 0; in qla82xx_pci_mem_read_direct()
667 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_read_direct()
669 ql_log(ql_log_fatal, vha, 0xb008, in qla82xx_pci_mem_read_direct()
671 "access, offset is 0x%llx.\n", in qla82xx_pci_mem_read_direct()
677 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_read_direct()
687 *(u8 *)data = 0; in qla82xx_pci_mem_read_direct()
724 int ret = 0; in qla82xx_pci_mem_write_direct()
739 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_write_direct()
741 ql_log(ql_log_fatal, vha, 0xb009, in qla82xx_pci_mem_write_direct()
743 "access, offset is 0x%llx.\n", in qla82xx_pci_mem_write_direct()
749 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_write_direct()
799 base_addr = addr & 0xfff00000; in qla82xx_decode_crb_addr()
800 offset = addr & 0x000fffff; in qla82xx_decode_crb_addr()
802 for (i = 0; i < MAX_CRB_XFORM; i++) { in qla82xx_decode_crb_addr()
819 int done = 0, timeout = 0; in qla82xx_rom_lock()
820 uint32_t lock_owner = 0; in qla82xx_rom_lock()
830 ql_dbg(ql_dbg_p3p, vha, 0xb157, in qla82xx_rom_lock()
838 return 0; in qla82xx_rom_lock()
844 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); in qla82xx_rom_unlock()
851 long timeout = 0; in qla82xx_wait_rom_busy()
852 long done = 0 ; in qla82xx_wait_rom_busy()
855 while (done == 0) { in qla82xx_wait_rom_busy()
860 ql_dbg(ql_dbg_p3p, vha, 0xb00a, in qla82xx_wait_rom_busy()
866 return 0; in qla82xx_wait_rom_busy()
872 long timeout = 0; in qla82xx_wait_rom_done()
873 long done = 0 ; in qla82xx_wait_rom_done()
876 while (done == 0) { in qla82xx_wait_rom_done()
881 ql_dbg(ql_dbg_p3p, vha, 0xb00b, in qla82xx_wait_rom_done()
887 return 0; in qla82xx_wait_rom_done()
893 uint32_t off_value, rval = 0; in qla82xx_md_rw_32()
895 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); in qla82xx_md_rw_32()
899 off_value = (off & 0x0000FFFF); in qla82xx_md_rw_32()
915 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); in qla82xx_do_rom_fast_read()
917 (addr & 0x0000FFFF), 0, 0); in qla82xx_do_rom_fast_read()
919 return 0; in qla82xx_do_rom_fast_read()
925 int ret, loops = 0; in qla82xx_rom_fast_read()
926 uint32_t lock_owner = 0; in qla82xx_rom_fast_read()
929 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in qla82xx_rom_fast_read()
936 ql_log(ql_log_fatal, vha, 0x00b9, in qla82xx_rom_fast_read()
954 ql_log(ql_log_warn, vha, 0xb00c, in qla82xx_read_status_reg()
959 return 0; in qla82xx_read_status_reg()
965 uint32_t val = 0; in qla82xx_flash_wait_write_finish()
969 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_wait_write_finish()
970 for (i = 0; i < 50000; i++) { in qla82xx_flash_wait_write_finish()
972 if (ret < 0 || (val & 1) == 0) in qla82xx_flash_wait_write_finish()
977 ql_log(ql_log_warn, vha, 0xb00d, in qla82xx_flash_wait_write_finish()
988 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_set_write_enable()
993 if (qla82xx_read_status_reg(ha, &val) != 0) in qla82xx_flash_set_write_enable()
997 return 0; in qla82xx_flash_set_write_enable()
1008 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); in qla82xx_write_status_reg()
1010 ql_log(ql_log_warn, vha, 0xb00e, in qla82xx_write_status_reg()
1024 ql_log(ql_log_warn, vha, 0xb00f, in qla82xx_write_disable_flash()
1028 return 0; in qla82xx_write_disable_flash()
1034 int loops = 0; in ql82xx_rom_lock_d()
1035 uint32_t lock_owner = 0; in ql82xx_rom_lock_d()
1038 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in ql82xx_rom_lock_d()
1045 ql_log(ql_log_warn, vha, 0xb010, in ql82xx_rom_lock_d()
1049 return 0; in ql82xx_rom_lock_d()
1056 int ret = 0; in qla82xx_write_flash_dword()
1060 if (ret < 0) { in qla82xx_write_flash_dword()
1061 ql_log(ql_log_warn, vha, 0xb011, in qla82xx_write_flash_dword()
1067 if (ret < 0) in qla82xx_write_flash_dword()
1076 ql_log(ql_log_warn, vha, 0xb012, in qla82xx_write_flash_dword()
1106 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); in qla82xx_pinit_from_rom()
1107 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); in qla82xx_pinit_from_rom()
1108 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); in qla82xx_pinit_from_rom()
1109 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); in qla82xx_pinit_from_rom()
1110 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); in qla82xx_pinit_from_rom()
1111 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); in qla82xx_pinit_from_rom()
1114 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); in qla82xx_pinit_from_rom()
1116 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); in qla82xx_pinit_from_rom()
1118 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); in qla82xx_pinit_from_rom()
1120 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); in qla82xx_pinit_from_rom()
1122 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); in qla82xx_pinit_from_rom()
1124 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); in qla82xx_pinit_from_rom()
1127 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); in qla82xx_pinit_from_rom()
1128 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); in qla82xx_pinit_from_rom()
1131 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); in qla82xx_pinit_from_rom()
1134 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); in qla82xx_pinit_from_rom()
1135 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); in qla82xx_pinit_from_rom()
1136 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); in qla82xx_pinit_from_rom()
1137 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); in qla82xx_pinit_from_rom()
1138 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); in qla82xx_pinit_from_rom()
1139 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); in qla82xx_pinit_from_rom()
1142 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); in qla82xx_pinit_from_rom()
1143 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); in qla82xx_pinit_from_rom()
1144 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); in qla82xx_pinit_from_rom()
1145 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); in qla82xx_pinit_from_rom()
1146 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); in qla82xx_pinit_from_rom()
1152 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); in qla82xx_pinit_from_rom()
1154 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); in qla82xx_pinit_from_rom()
1158 * Offset 0: Contain signature (0xcafecafe) in qla82xx_pinit_from_rom()
1162 n = 0; in qla82xx_pinit_from_rom()
1163 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || in qla82xx_pinit_from_rom()
1164 qla82xx_rom_fast_read(ha, 4, &n) != 0) { in qla82xx_pinit_from_rom()
1165 ql_log(ql_log_fatal, vha, 0x006e, in qla82xx_pinit_from_rom()
1173 offset = n & 0xffffU; in qla82xx_pinit_from_rom()
1174 n = (n >> 16) & 0xffffU; in qla82xx_pinit_from_rom()
1178 ql_log(ql_log_fatal, vha, 0x0071, in qla82xx_pinit_from_rom()
1179 "Card flash not initialized:n=0x%x.\n", n); in qla82xx_pinit_from_rom()
1183 ql_log(ql_log_info, vha, 0x0072, in qla82xx_pinit_from_rom()
1188 ql_log(ql_log_fatal, vha, 0x010c, in qla82xx_pinit_from_rom()
1193 for (i = 0; i < n; i++) { in qla82xx_pinit_from_rom()
1194 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || in qla82xx_pinit_from_rom()
1195 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { in qla82xx_pinit_from_rom()
1204 for (i = 0; i < n; i++) { in qla82xx_pinit_from_rom()
1215 if (off == QLA82XX_CAM_RAM(0x1fc)) in qla82xx_pinit_from_rom()
1219 if (off == (ROMUSB_GLB + 0xbc)) in qla82xx_pinit_from_rom()
1223 if (off == (ROMUSB_GLB + 0xc8)) in qla82xx_pinit_from_rom()
1233 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) in qla82xx_pinit_from_rom()
1236 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) in qla82xx_pinit_from_rom()
1240 ql_log(ql_log_fatal, vha, 0x0116, in qla82xx_pinit_from_rom()
1241 "Unknown addr: 0x%08lx.\n", buf[i].addr); in qla82xx_pinit_from_rom()
1248 * else crb_window returns 0xffffffff in qla82xx_pinit_from_rom()
1262 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); in qla82xx_pinit_from_rom()
1263 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); in qla82xx_pinit_from_rom()
1264 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); in qla82xx_pinit_from_rom()
1267 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); in qla82xx_pinit_from_rom()
1268 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); in qla82xx_pinit_from_rom()
1269 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); in qla82xx_pinit_from_rom()
1270 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); in qla82xx_pinit_from_rom()
1271 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); in qla82xx_pinit_from_rom()
1272 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); in qla82xx_pinit_from_rom()
1273 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); in qla82xx_pinit_from_rom()
1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); in qla82xx_pinit_from_rom()
1275 return 0; in qla82xx_pinit_from_rom()
1282 int i, j, ret = 0, loop, sz[2], off0; in qla82xx_pci_mem_write_2M()
1285 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; in qla82xx_pci_mem_write_2M()
1294 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_write_2M()
1299 off0 = off & 0x7; in qla82xx_pci_mem_write_2M()
1300 sz[0] = (size < (8 - off0)) ? size : (8 - off0); in qla82xx_pci_mem_write_2M()
1301 sz[1] = size - sz[0]; in qla82xx_pci_mem_write_2M()
1303 off8 = off & 0xfffffff0; in qla82xx_pci_mem_write_2M()
1304 loop = (((off & 0xf) + size - 1) >> 4) + 1; in qla82xx_pci_mem_write_2M()
1307 startword = (off & 0xf)/8; in qla82xx_pci_mem_write_2M()
1309 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_write_2M()
1331 if (sz[0] == 8) { in qla82xx_pci_mem_write_2M()
1335 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); in qla82xx_pci_mem_write_2M()
1338 if (sz[1] != 0) { in qla82xx_pci_mem_write_2M()
1339 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); in qla82xx_pci_mem_write_2M()
1340 word[startword+1] |= tmpw >> (sz[0] * 8); in qla82xx_pci_mem_write_2M()
1343 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_write_2M()
1346 temp = 0; in qla82xx_pci_mem_write_2M()
1348 temp = word[i * scale] & 0xffffffff; in qla82xx_pci_mem_write_2M()
1350 temp = (word[i * scale] >> 32) & 0xffffffff; in qla82xx_pci_mem_write_2M()
1352 temp = word[i*scale + 1] & 0xffffffff; in qla82xx_pci_mem_write_2M()
1355 temp = (word[i*scale + 1] >> 32) & 0xffffffff; in qla82xx_pci_mem_write_2M()
1364 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_pci_mem_write_2M()
1366 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla82xx_pci_mem_write_2M()
1386 long size = 0; in qla82xx_fw_load_from_flash()
1394 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_flash()
1404 if (i % 0x1000 == 0) in qla82xx_fw_load_from_flash()
1409 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_flash()
1410 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_flash()
1412 return 0; in qla82xx_fw_load_from_flash()
1419 int i, j = 0, k, start, end, loop, sz[2], off0[2]; in qla82xx_pci_mem_read_2M()
1422 uint64_t off8, val, mem_crb, word[2] = {0, 0}; in qla82xx_pci_mem_read_2M()
1432 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_read_2M()
1437 off8 = off & 0xfffffff0; in qla82xx_pci_mem_read_2M()
1438 off0[0] = off & 0xf; in qla82xx_pci_mem_read_2M()
1439 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); in qla82xx_pci_mem_read_2M()
1441 loop = ((off0[0] + size - 1) >> shift_amount) + 1; in qla82xx_pci_mem_read_2M()
1442 off0[1] = 0; in qla82xx_pci_mem_read_2M()
1443 sz[1] = size - sz[0]; in qla82xx_pci_mem_read_2M()
1445 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_read_2M()
1448 temp = 0; in qla82xx_pci_mem_read_2M()
1455 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_pci_mem_read_2M()
1457 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla82xx_pci_mem_read_2M()
1480 if ((off0[0] & 7) == 0) { in qla82xx_pci_mem_read_2M()
1481 val = word[0]; in qla82xx_pci_mem_read_2M()
1483 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | in qla82xx_pci_mem_read_2M()
1484 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); in qla82xx_pci_mem_read_2M()
1501 return 0; in qla82xx_pci_mem_read_2M()
1510 (struct qla82xx_uri_table_desc *)&unirom[0]; in qla82xx_get_table_desc()
1515 for (i = 0; i < entries; i++) { in qla82xx_get_table_desc()
1596 uint32_t len = 0; in qla82xx_iospace_config()
1599 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, in qla82xx_iospace_config()
1605 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { in qla82xx_iospace_config()
1606 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, in qla82xx_iospace_config()
1607 "Region #0 not an MMIO resource, aborting.\n"); in qla82xx_iospace_config()
1611 len = pci_resource_len(ha->pdev, 0); in qla82xx_iospace_config()
1612 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); in qla82xx_iospace_config()
1614 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, in qla82xx_iospace_config()
1623 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); in qla82xx_iospace_config()
1630 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, in qla82xx_iospace_config()
1648 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, in qla82xx_iospace_config()
1653 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, in qla82xx_iospace_config()
1658 return 0; in qla82xx_iospace_config()
1672 * Returns 0 on success.
1683 ql_dbg(ql_dbg_init, vha, 0x0043, in qla82xx_pci_config()
1686 return 0; in qla82xx_pci_config()
1693 * Returns 0 on success.
1710 struct req_que *req = ha->req_q_map[0]; in qla82xx_config_rings()
1711 struct rsp_que *rsp = ha->rsp_q_map[0]; in qla82xx_config_rings()
1715 icb->request_q_outpointer = cpu_to_le16(0); in qla82xx_config_rings()
1716 icb->response_q_inpointer = cpu_to_le16(0); in qla82xx_config_rings()
1722 wrt_reg_dword(®->req_q_out[0], 0); in qla82xx_config_rings()
1723 wrt_reg_dword(®->rsp_q_in[0], 0); in qla82xx_config_rings()
1724 wrt_reg_dword(®->rsp_q_out[0], 0); in qla82xx_config_rings()
1739 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_blob()
1750 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_blob()
1764 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); in qla82xx_fw_load_from_blob()
1767 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_blob()
1768 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_blob()
1770 return 0; in qla82xx_fw_load_from_blob()
1783 int mn_present = 0; in qla82xx_set_product_offset()
1793 for (i = 0; i < entries; i++) { in qla82xx_set_product_offset()
1805 return 0; in qla82xx_set_product_offset()
1836 return 0; in qla82xx_validate_firmware_blob()
1842 u32 val = 0; in qla82xx_check_cmdpeg_state()
1860 ql_log(ql_log_info, vha, 0x00a8, in qla82xx_check_cmdpeg_state()
1861 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", in qla82xx_check_cmdpeg_state()
1868 ql_log(ql_log_fatal, vha, 0x00a9, in qla82xx_check_cmdpeg_state()
1869 "Cmd Peg initialization failed: 0x%x.\n", val); in qla82xx_check_cmdpeg_state()
1881 u32 val = 0; in qla82xx_check_rcvpeg_state()
1899 ql_log(ql_log_info, vha, 0x00ab, in qla82xx_check_rcvpeg_state()
1900 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", in qla82xx_check_rcvpeg_state()
1907 ql_log(ql_log_fatal, vha, 0x00ac, in qla82xx_check_rcvpeg_state()
1908 "Rcv Peg initialization failed: 0x%x.\n", val); in qla82xx_check_rcvpeg_state()
1936 ha->mailbox_out[0] = mb0; in qla82xx_mbx_completion()
1944 ql_dbg(ql_dbg_async, vha, 0x5053, in qla82xx_mbx_completion()
1964 int status = 0, status1 = 0; in qla82xx_intr_handler()
1967 uint32_t stat = 0; in qla82xx_intr_handler()
1972 ql_log(ql_log_info, NULL, 0xb053, in qla82xx_intr_handler()
1989 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); in qla82xx_intr_handler()
2004 switch (stat & 0xff) { in qla82xx_intr_handler()
2005 case 0x1: in qla82xx_intr_handler()
2006 case 0x2: in qla82xx_intr_handler()
2007 case 0x10: in qla82xx_intr_handler()
2008 case 0x11: in qla82xx_intr_handler()
2012 case 0x12: in qla82xx_intr_handler()
2013 mb[0] = MSW(stat); in qla82xx_intr_handler()
2019 case 0x13: in qla82xx_intr_handler()
2023 ql_dbg(ql_dbg_async, vha, 0x5054, in qla82xx_intr_handler()
2025 stat & 0xff); in qla82xx_intr_handler()
2029 wrt_reg_dword(®->host_int, 0); in qla82xx_intr_handler()
2036 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_intr_handler()
2048 int status = 0; in qla82xx_msix_default()
2050 uint32_t stat = 0; in qla82xx_msix_default()
2051 uint32_t host_int = 0; in qla82xx_msix_default()
2073 switch (stat & 0xff) { in qla82xx_msix_default()
2074 case 0x1: in qla82xx_msix_default()
2075 case 0x2: in qla82xx_msix_default()
2076 case 0x10: in qla82xx_msix_default()
2077 case 0x11: in qla82xx_msix_default()
2081 case 0x12: in qla82xx_msix_default()
2082 mb[0] = MSW(stat); in qla82xx_msix_default()
2088 case 0x13: in qla82xx_msix_default()
2092 ql_dbg(ql_dbg_async, vha, 0x5041, in qla82xx_msix_default()
2094 stat & 0xff); in qla82xx_msix_default()
2098 wrt_reg_dword(®->host_int, 0); in qla82xx_msix_default()
2099 } while (0); in qla82xx_msix_default()
2115 uint32_t host_int = 0; in qla82xx_msix_rsp_q()
2132 wrt_reg_dword(®->host_int, 0); in qla82xx_msix_rsp_q()
2146 uint32_t host_int = 0; in qla82xx_poll()
2167 switch (stat & 0xff) { in qla82xx_poll()
2168 case 0x1: in qla82xx_poll()
2169 case 0x2: in qla82xx_poll()
2170 case 0x10: in qla82xx_poll()
2171 case 0x11: in qla82xx_poll()
2174 case 0x12: in qla82xx_poll()
2175 mb[0] = MSW(stat); in qla82xx_poll()
2181 case 0x13: in qla82xx_poll()
2185 ql_dbg(ql_dbg_p3p, vha, 0xb013, in qla82xx_poll()
2187 stat * 0xff); in qla82xx_poll()
2190 wrt_reg_dword(®->host_int, 0); in qla82xx_poll()
2204 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); in qla82xx_enable_intrs()
2206 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_enable_intrs()
2223 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); in qla82xx_disable_intrs()
2225 ha->interrupts_on = 0; in qla82xx_disable_intrs()
2256 ql_log(ql_log_info, vha, 0xb082, in qla82xx_set_idc_version()
2261 ql_log(ql_log_info, vha, 0xb083, in qla82xx_set_idc_version()
2277 if (drv_active == 0xffffffff) { in qla82xx_set_drv_active()
2320 if (drv_state == 0xffffffff) { in qla82xx_set_rst_ready()
2325 ql_dbg(ql_dbg_init, vha, 0x00bb, in qla82xx_set_rst_ready()
2326 "drv_state = 0x%08x.\n", drv_state); in qla82xx_set_rst_ready()
2369 ql_log(ql_log_fatal, vha, 0x009f, in qla82xx_load_fw()
2388 ql_log(ql_log_info, vha, 0x00a0, in qla82xx_load_fw()
2392 ql_log(ql_log_info, vha, 0x00a1, in qla82xx_load_fw()
2396 ql_log(ql_log_warn, vha, 0x0108, in qla82xx_load_fw()
2401 ql_log(ql_log_info, vha, 0x00a2, in qla82xx_load_fw()
2407 ql_log(ql_log_fatal, vha, 0x00a3, in qla82xx_load_fw()
2418 ql_log(ql_log_fatal, vha, 0x00a4, in qla82xx_load_fw()
2425 ql_log(ql_log_info, vha, 0x00a5, in qla82xx_load_fw()
2430 ql_log(ql_log_fatal, vha, 0x00a6, in qla82xx_load_fw()
2449 * of 0 before resetting the hardware in qla82xx_start_firmware()
2451 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); in qla82xx_start_firmware()
2452 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); in qla82xx_start_firmware()
2455 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); in qla82xx_start_firmware()
2456 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); in qla82xx_start_firmware()
2459 ql_log(ql_log_fatal, vha, 0x00a7, in qla82xx_start_firmware()
2466 ql_log(ql_log_fatal, vha, 0x00aa, in qla82xx_start_firmware()
2473 ha->link_width = (lnk >> 4) & 0x3f; in qla82xx_start_firmware()
2488 for (i = 0; i < length/4; i++, faddr += 4) { in qla82xx_read_flash_data()
2490 ql_log(ql_log_warn, vha, 0x0106, in qla82xx_read_flash_data()
2508 if (ret < 0) { in qla82xx_unprotect_flash()
2509 ql_log(ql_log_warn, vha, 0xb014, in qla82xx_unprotect_flash()
2515 if (ret < 0) in qla82xx_unprotect_flash()
2520 if (ret < 0) { in qla82xx_unprotect_flash()
2525 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_unprotect_flash()
2526 ql_log(ql_log_warn, vha, 0xb015, in qla82xx_unprotect_flash()
2542 if (ret < 0) { in qla82xx_protect_flash()
2543 ql_log(ql_log_warn, vha, 0xb016, in qla82xx_protect_flash()
2549 if (ret < 0) in qla82xx_protect_flash()
2555 if (ret < 0) in qla82xx_protect_flash()
2556 ql_log(ql_log_warn, vha, 0xb017, in qla82xx_protect_flash()
2559 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_protect_flash()
2560 ql_log(ql_log_warn, vha, 0xb018, in qla82xx_protect_flash()
2570 int ret = 0; in qla82xx_erase_sector()
2574 if (ret < 0) { in qla82xx_erase_sector()
2575 ql_log(ql_log_warn, vha, 0xb019, in qla82xx_erase_sector()
2586 ql_log(ql_log_warn, vha, 0xb01a, in qla82xx_erase_sector()
2619 int page_mode = 0; in qla82xx_write_flash_data()
2625 if (page_mode && !(faddr & 0xfff) && in qla82xx_write_flash_data()
2630 ql_log(ql_log_warn, vha, 0xb01b, in qla82xx_write_flash_data()
2641 ql_log(ql_log_warn, vha, 0xb01c, in qla82xx_write_flash_data()
2646 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { in qla82xx_write_flash_data()
2648 if ((faddr & rest_addr) == 0) { in qla82xx_write_flash_data()
2652 ql_log(ql_log_warn, vha, 0xb01d, in qla82xx_write_flash_data()
2668 ql_log(ql_log_warn, vha, 0xb01e, in qla82xx_write_flash_data()
2673 ql_log(ql_log_warn, vha, 0xb01f, in qla82xx_write_flash_data()
2690 ql_dbg(ql_dbg_p3p, vha, 0xb020, in qla82xx_write_flash_data()
2699 ql_log(ql_log_warn, vha, 0xb021, in qla82xx_write_flash_data()
2731 struct req_que *req = ha->req_q_map[0]; in qla82xx_start_iocbs()
2737 req->ring_index = 0; in qla82xx_start_iocbs()
2742 dbval = 0x04 | (ha->portnum << 5); in qla82xx_start_iocbs()
2761 uint32_t lock_owner = 0; in qla82xx_rom_lock_recovery()
2766 ql_log(ql_log_info, vha, 0xb022, in qla82xx_rom_lock_recovery()
2785 * Success : 0
2795 int need_reset = 0; in qla82xx_device_bootstrap()
2805 for (i = 0; i < 10; i++) { in qla82xx_device_bootstrap()
2817 ql_log(ql_log_info, vha, 0x009e, in qla82xx_device_bootstrap()
2826 ql_log(ql_log_fatal, vha, 0x00ad, in qla82xx_device_bootstrap()
2834 ql_log(ql_log_info, vha, 0x00ae, in qla82xx_device_bootstrap()
2872 drv_active = drv_active << 0x01; in qla82xx_need_qsnt_handler()
2880 ql_log(ql_log_info, vha, 0xb023, in qla82xx_need_qsnt_handler()
2886 ql_log(ql_log_info, vha, 0xb025, in qla82xx_need_qsnt_handler()
2902 drv_active = drv_active << 0x01; in qla82xx_need_qsnt_handler()
2907 ql_log(ql_log_info, vha, 0xb026, in qla82xx_need_qsnt_handler()
2919 ql_log(ql_log_fatal, vha, 0x00b8, in qla8xxx_dev_failed_handler()
2934 vha->flags.online = 0; in qla8xxx_dev_failed_handler()
2935 vha->flags.init_done = 0; in qla8xxx_dev_failed_handler()
2946 * Success : 0
2953 uint32_t active_mask = 0; in qla82xx_need_reset_handler()
2956 struct req_que *req = ha->req_q_map[0]; in qla82xx_need_reset_handler()
2968 ql_dbg(ql_dbg_p3p, vha, 0xb028, in qla82xx_need_reset_handler()
2969 "reset_acknowledged by 0x%x\n", ha->portnum); in qla82xx_need_reset_handler()
2974 ql_dbg(ql_dbg_p3p, vha, 0xb029, in qla82xx_need_reset_handler()
2975 "active_mask: 0x%08x\n", active_mask); in qla82xx_need_reset_handler()
2985 ql_dbg(ql_dbg_p3p, vha, 0xb02a, in qla82xx_need_reset_handler()
2986 "drv_state: 0x%08x, drv_active: 0x%08x, " in qla82xx_need_reset_handler()
2987 "dev_state: 0x%08x, active_mask: 0x%08x\n", in qla82xx_need_reset_handler()
2993 ql_log(ql_log_warn, vha, 0x00b5, in qla82xx_need_reset_handler()
3007 ql_dbg(ql_dbg_p3p, vha, 0xb02b, in qla82xx_need_reset_handler()
3008 "drv_state: 0x%08x, drv_active: 0x%08x, " in qla82xx_need_reset_handler()
3009 "dev_state: 0x%08x, active_mask: 0x%08x\n", in qla82xx_need_reset_handler()
3012 ql_log(ql_log_info, vha, 0x00b6, in qla82xx_need_reset_handler()
3013 "Device state is 0x%x = %s.\n", in qla82xx_need_reset_handler()
3019 ql_log(ql_log_info, vha, 0x00b7, in qla82xx_need_reset_handler()
3025 ql_log(ql_log_warn, vha, 0xb02c, in qla82xx_need_reset_handler()
3028 ql_log(ql_log_warn, vha, 0xb04f, in qla82xx_need_reset_handler()
3054 ql_dbg(ql_dbg_p3p, vha, 0xb02d, in qla82xx_check_md_needed()
3068 ql_log(ql_log_info, vha, 0xb02e, in qla82xx_check_md_needed()
3079 int status = 0; in qla82xx_check_fw_alive()
3083 /* all 0xff, assume AER/EEH in progress, ignore */ in qla82xx_check_fw_alive()
3084 if (fw_heartbeat_counter == 0xffffffff) { in qla82xx_check_fw_alive()
3085 ql_dbg(ql_dbg_timer, vha, 0x6003, in qla82xx_check_fw_alive()
3086 "FW heartbeat counter is 0xffffffff, " in qla82xx_check_fw_alive()
3094 vha->seconds_since_last_heartbeat = 0; in qla82xx_check_fw_alive()
3098 vha->seconds_since_last_heartbeat = 0; in qla82xx_check_fw_alive()
3101 ql_dbg(ql_dbg_timer, vha, 0x6004, in qla82xx_check_fw_alive()
3114 * Success : 0
3125 int loopcount = 0; in qla82xx_device_state_handler()
3135 ql_log(ql_log_info, vha, 0x009b, in qla82xx_device_state_handler()
3136 "Device state is 0x%x = %s.\n", in qla82xx_device_state_handler()
3145 ql_log(ql_log_fatal, vha, 0x009c, in qla82xx_device_state_handler()
3152 loopcount = 0; in qla82xx_device_state_handler()
3156 ql_log(ql_log_info, vha, 0x009d, in qla82xx_device_state_handler()
3157 "Device state is 0x%x = %s.\n", in qla82xx_device_state_handler()
3163 ha->flags.nic_core_reset_owner = 0; in qla82xx_device_state_handler()
3232 ql_log(ql_log_warn, vha, 0x600e, in qla82xx_check_temp()
3238 ql_log(ql_log_warn, vha, 0x600f, in qla82xx_check_temp()
3243 return 0; in qla82xx_check_temp()
3260 ha->flags.mbox_busy = 0; in qla82xx_clear_pending_mbx()
3261 ql_log(ql_log_warn, vha, 0x6010, in qla82xx_clear_pending_mbx()
3282 ql_log(ql_log_warn, vha, 0x6001, in qla82xx_watchdog()
3287 ql_log(ql_log_warn, vha, 0x6002, in qla82xx_watchdog()
3293 ql_log(ql_log_warn, vha, 0xb055, in qla82xx_watchdog()
3300 ql_dbg(ql_dbg_timer, vha, 0x6011, in qla82xx_watchdog()
3301 "disabling pause transmit on port 0 & 1.\n"); in qla82xx_watchdog()
3302 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, in qla82xx_watchdog()
3306 ql_log(ql_log_info, vha, 0x6005, in qla82xx_watchdog()
3308 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " in qla82xx_watchdog()
3309 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " in qla82xx_watchdog()
3310 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " in qla82xx_watchdog()
3311 " PEG_NET_4_PC: 0x%x.\n", halt_status, in qla82xx_watchdog()
3314 QLA82XX_CRB_PEG_NET_0 + 0x3c), in qla82xx_watchdog()
3316 QLA82XX_CRB_PEG_NET_1 + 0x3c), in qla82xx_watchdog()
3318 QLA82XX_CRB_PEG_NET_2 + 0x3c), in qla82xx_watchdog()
3320 QLA82XX_CRB_PEG_NET_3 + 0x3c), in qla82xx_watchdog()
3322 QLA82XX_CRB_PEG_NET_4 + 0x3c)); in qla82xx_watchdog()
3323 if (((halt_status & 0x1fffff00) >> 8) == 0x67) in qla82xx_watchdog()
3324 ql_log(ql_log_warn, vha, 0xb052, in qla82xx_watchdog()
3326 "error code 0x00006700. Device is " in qla82xx_watchdog()
3332 ql_log(ql_log_info, vha, 0x6006, in qla82xx_watchdog()
3338 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); in qla82xx_watchdog()
3366 uint32_t dev_state = 0; in qla82xx_set_reset_owner()
3374 ql_log(ql_log_info, vha, 0xb02f, in qla82xx_set_reset_owner()
3380 ql_dbg(ql_dbg_p3p, vha, 0xb030, in qla82xx_set_reset_owner()
3381 "reset_owner is 0x%x\n", ha->portnum); in qla82xx_set_reset_owner()
3386 ql_log(ql_log_info, vha, 0xb031, in qla82xx_set_reset_owner()
3387 "Device state is 0x%x = %s.\n", in qla82xx_set_reset_owner()
3399 * 0 = success
3408 ql_log(ql_log_warn, vha, 0x8024, in qla82xx_abort_isp()
3433 ha->flags.isp82xx_fw_hung = 0; in qla82xx_abort_isp()
3434 ha->flags.nic_core_reset_hdlr_active = 0; in qla82xx_abort_isp()
3441 if (ha->isp_abort_cnt == 0) { in qla82xx_abort_isp()
3442 ql_log(ql_log_warn, vha, 0x8027, in qla82xx_abort_isp()
3450 vha->flags.online = 0; in qla82xx_abort_isp()
3456 ql_log(ql_log_warn, vha, 0x8036, in qla82xx_abort_isp()
3463 ql_dbg(ql_dbg_taskm, vha, 0x8029, in qla82xx_abort_isp()
3484 * 0 = success
3515 * Success (fcoe_ctx reset is done) : 0
3537 ql_dbg(ql_dbg_p3p, vha, 0xb027, in qla2x00_wait_for_fcoe_ctx_reset()
3546 int i, fw_state = 0; in qla82xx_chip_reset_cleanup()
3555 for (i = 0; i < 2; i++) { in qla82xx_chip_reset_cleanup()
3568 ql_dbg(ql_dbg_init, vha, 0x00b0, in qla82xx_chip_reset_cleanup()
3579 for (que = 0; que < ha->max_req_queues; que++) { in qla82xx_chip_reset_cleanup()
3594 0x00b1, in qla82xx_chip_reset_cleanup()
3598 0x00b2, in qla82xx_chip_reset_cleanup()
3609 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, in qla82xx_chip_reset_cleanup()
3611 ql_dbg(ql_dbg_init, vha, 0x00b3, in qla82xx_chip_reset_cleanup()
3638 for (i = 0; i < crb_entry->op_count; i++) { in qla82xx_minidump_process_control()
3647 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3653 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3664 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3673 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3685 crb_addr, 0, 0); in qla82xx_minidump_process_control()
3697 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_control()
3752 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdocm()
3776 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdmux()
3778 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdmux()
3800 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdcrb()
3801 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdcrb()
3834 for (i = 0; i < loop_count; i++) { in qla82xx_minidump_process_l2tag()
3842 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); in qla82xx_minidump_process_l2tag()
3843 if ((c_value_r & p_mask) == 0) in qla82xx_minidump_process_l2tag()
3847 ql_dbg(ql_dbg_p3p, vha, 0xb032, in qla82xx_minidump_process_l2tag()
3848 "c_value_r: 0x%x, poll_mask: 0x%lx, " in qla82xx_minidump_process_l2tag()
3849 "w_time: 0x%lx\n", in qla82xx_minidump_process_l2tag()
3857 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_l2tag()
3858 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l2tag()
3889 for (i = 0; i < loop_count; i++) { in qla82xx_minidump_process_l1cache()
3893 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_l1cache()
3894 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l1cache()
3909 uint32_t r_stride, r_value, r_cnt, qid = 0; in qla82xx_minidump_process_queue()
3920 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_queue()
3923 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_queue()
3924 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_queue()
3947 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdrom()
3949 (r_addr & 0xFFFF0000), 1); in qla82xx_minidump_process_rdrom()
3952 (r_addr & 0x0000FFFF), 0, 0); in qla82xx_minidump_process_rdrom()
3975 if (r_addr & 0xf) { in qla82xx_minidump_process_rdmem()
3976 ql_log(ql_log_warn, vha, 0xb033, in qla82xx_minidump_process_rdmem()
3977 "Read addr 0x%x not 16 bytes aligned\n", r_addr); in qla82xx_minidump_process_rdmem()
3982 ql_log(ql_log_warn, vha, 0xb034, in qla82xx_minidump_process_rdmem()
3983 "Read data[0x%x] not multiple of 16 bytes\n", in qla82xx_minidump_process_rdmem()
3988 ql_dbg(ql_dbg_p3p, vha, 0xb035, in qla82xx_minidump_process_rdmem()
3989 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", in qla82xx_minidump_process_rdmem()
3993 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdmem()
3995 r_value = 0; in qla82xx_minidump_process_rdmem()
4002 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_minidump_process_rdmem()
4004 MD_MIU_TEST_AGT_CTRL, 0, 0); in qla82xx_minidump_process_rdmem()
4005 if ((r_value & MIU_TA_CTL_BUSY) == 0) in qla82xx_minidump_process_rdmem()
4016 for (j = 0; j < 4; j++) { in qla82xx_minidump_process_rdmem()
4018 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); in qla82xx_minidump_process_rdmem()
4032 uint64_t chksum = 0; in qla82xx_validate_template_chksum()
4036 while (count-- > 0) in qla82xx_validate_template_chksum()
4039 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); in qla82xx_validate_template_chksum()
4048 ql_dbg(ql_dbg_p3p, vha, 0xb036, in qla82xx_mark_entry_skipped()
4050 "ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla82xx_mark_entry_skipped()
4059 int no_entry_hdr = 0; in qla82xx_md_collect()
4063 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; in qla82xx_md_collect()
4064 int i = 0, rval = QLA_FUNCTION_FAILED; in qla82xx_md_collect()
4070 ql_log(ql_log_warn, vha, 0xb037, in qla82xx_md_collect()
4079 ql_log(ql_log_warn, vha, 0xb038, in qla82xx_md_collect()
4085 ql_log(ql_log_warn, vha, 0xb054, in qla82xx_md_collect()
4088 ha->flags.isp82xx_no_md_cap = 0; in qla82xx_md_collect()
4093 ql_log(ql_log_info, vha, 0xb039, in qla82xx_md_collect()
4099 ql_dbg(ql_dbg_p3p, vha, 0xb03a, in qla82xx_md_collect()
4100 "No of entry headers in Template: 0x%x\n", no_entry_hdr); in qla82xx_md_collect()
4102 ql_dbg(ql_dbg_p3p, vha, 0xb03b, in qla82xx_md_collect()
4103 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); in qla82xx_md_collect()
4105 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; in qla82xx_md_collect()
4108 if ((f_capture_mask & 0x3) != 0x3) { in qla82xx_md_collect()
4109 ql_log(ql_log_warn, vha, 0xb03c, in qla82xx_md_collect()
4110 "Minimum required capture mask[0x%x] level not set\n", in qla82xx_md_collect()
4116 tmplt_hdr->driver_info[0] = vha->host_no; in qla82xx_md_collect()
4123 ql_dbg(ql_dbg_p3p, vha, 0xb03d, in qla82xx_md_collect()
4124 "Total minidump data_size 0x%x to be captured\n", total_data_size); in qla82xx_md_collect()
4128 ql_log(ql_log_warn, vha, 0xb04e, in qla82xx_md_collect()
4129 "Bad template header entry type: 0x%x obtained\n", in qla82xx_md_collect()
4138 for (i = 0; i < no_entry_hdr; i++) { in qla82xx_md_collect()
4141 ql_log(ql_log_warn, vha, 0xb03e, in qla82xx_md_collect()
4142 "More MiniDump data collected: [0x%x]\n", in qla82xx_md_collect()
4151 ql_dbg(ql_dbg_p3p, vha, 0xb03f, in qla82xx_md_collect()
4153 "ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla82xx_md_collect()
4159 ql_dbg(ql_dbg_p3p, vha, 0xb040, in qla82xx_md_collect()
4161 "entry_type: 0x%x, capture_mask: 0x%x\n", in qla82xx_md_collect()
4166 ql_dbg(ql_dbg_p3p, vha, 0xb041, in qla82xx_md_collect()
4167 "Data collected: [0x%x], Dump size left:[0x%x]\n", in qla82xx_md_collect()
4235 ql_dbg(ql_dbg_p3p, vha, 0xb042, in qla82xx_md_collect()
4246 ql_dbg(ql_dbg_p3p, vha, 0xb043, in qla82xx_md_collect()
4247 "MiniDump data mismatch: Data collected: [0x%x]," in qla82xx_md_collect()
4248 "total_data_size:[0x%x]\n", in qla82xx_md_collect()
4253 ql_log(ql_log_info, vha, 0xb044, in qla82xx_md_collect()
4272 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { in qla82xx_md_alloc()
4273 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; in qla82xx_md_alloc()
4274 ql_log(ql_log_info, vha, 0xb045, in qla82xx_md_alloc()
4275 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", in qla82xx_md_alloc()
4279 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { in qla82xx_md_alloc()
4285 ql_log(ql_log_warn, vha, 0xb046, in qla82xx_md_alloc()
4292 ql_log(ql_log_warn, vha, 0xb047, in qla82xx_md_alloc()
4294 "(0x%x).\n", ha->md_dump_size); in qla82xx_md_alloc()
4297 return 0; in qla82xx_md_alloc()
4307 ql_log(ql_log_info, vha, 0xb048, in qla82xx_md_free()
4317 ql_log(ql_log_info, vha, 0xb049, in qla82xx_md_free()
4321 ha->md_dump_size = 0; in qla82xx_md_free()
4335 ql_log(ql_log_info, vha, 0xb04a, in qla82xx_md_prep()
4346 ql_dbg(ql_dbg_p3p, vha, 0xb04b, in qla82xx_md_prep()
4352 ql_log(ql_log_info, vha, 0xb04c, in qla82xx_md_prep()
4356 ql_log(ql_log_info, vha, 0xb04d, in qla82xx_md_prep()
4381 ql_log(ql_log_warn, vha, 0xb050, in qla82xx_beacon_on()
4399 rval = qla82xx_mbx_beacon_ctl(vha, 0); in qla82xx_beacon_off()
4402 ql_log(ql_log_warn, vha, 0xb051, in qla82xx_beacon_off()
4406 ha->beacon_blink_led = 0; in qla82xx_beacon_off()