2771 		if (rd_reg_word(&reg->mailbox12) & BIT_0)  in qla2x00_initialize_adapter()
2909 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2100_pci_config()
2953 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)  in qla2300_pci_config()
2961 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2971 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2976 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0)  in qla2300_pci_config()
2991 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
3142 				if ((rd_reg_word(&reg->hccr) &  in qla2x00_reset_chip()
3148 			rd_reg_word(&reg->hccr);	/* PCI Posting. */  in qla2x00_reset_chip()
3154 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
3158 		rd_reg_word(&reg->fpm_diag_config);	/* PCI Posting. */  in qla2x00_reset_chip()
3163 			rd_reg_word(&reg->fpm_diag_config); /* PCI Posting. */  in qla2x00_reset_chip()
3168 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
3187 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
3191 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3195 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3213 			if ((rd_reg_word(&reg->ctrl_status) &  in qla2x00_reset_chip()
3228 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_chip()
3247 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3286 	mb[0] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
3292 			mb[i] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
3360 	rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3361 	for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&  in qla24xx_reset_risc()
3376 	    rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3423 	wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3431 			wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3446 	     rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3603 		data = rd_reg_word(&reg->ctrl_status);  in qla2x00_chip_diag()
4305 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4414 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4675 	rd_reg_word(ISP_RSP_Q_OUT(ha, reg));		/* PCI Posting. */  in qla2x00_config_rings()
4759 	rd_reg_word(&ioreg->hccr);  in qla24xx_config_rings()
5246 		if ((rd_reg_word(&reg->ctrl_status) >> 14) == 1)  in qla2x00_nvram_config()
7816 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
7818 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()