Lines Matching +full:0 +full:xf007
15 #define PCI_VENDOR_ID_IODATA 0x10fc
16 #define PCI_VENDOR_ID_WORKBIT 0x1145
18 #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
19 #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
20 #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
21 #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
22 #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
23 #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
24 #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
25 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
26 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
32 MODEL_IODATA = 0,
55 #define EXTENDED_SDTR_LEN 0x03
68 # define FALSE 0
71 #define NEGATE 0
79 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
81 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
82 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
83 # define IRQSTATUS_LATCHED_MSG BIT(0)
112 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
113 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
114 # define CB_MMIO_MODE BIT(0)
130 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
132 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
133 # define TIMER_CNT_MASK (0xff)
136 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
137 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
139 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
140 # define FIFO_REST_MASK 0x1ff
144 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
145 # define SREQSMPLRATE_RATE0 BIT(0)
148 # define SMPL_40M (0) /* 40MHz: 0-100ns/period */
152 #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
153 # define BUSCTL_SEL BIT(0)
162 #define CLR_COUNTER 0x12 /* BASE+12, B, W */
163 # define ACK_COUNTER_CLR BIT(0)
176 #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
177 # define BUSMON_MSG BIT(0)
186 #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
188 #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
189 # define PARITY_CHECK_ENABLE BIT(0)
191 #define PARITY_STATUS 0x16 /* BASE+16, B, R */
192 //# define PARITY_CHECK_ENABLE BIT(0)
197 #define RESELECT_ID 0x18 /* BASE+18, B, R */
199 #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
200 # define CLEAR_CDB_FIFO_POINTER BIT(0)
210 #define SET_ARBIT 0x1a /* BASE+1a, B, W */
211 # define ARBIT_GO BIT(0)
214 #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
215 //# define ARBIT_GO BIT(0)
221 #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
223 #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
225 #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
226 #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
227 #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
229 #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
230 #define SCAM_STATUS 0x24 /* BASE+24, B, R */
231 # define SCAM_MSG BIT(0)
238 #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
239 # define SD0 BIT(0)
248 #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
249 #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
251 #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
252 #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
253 #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
255 #define BM_CNT 0x38 /* BASE+38, DW, R/W */
256 # define BM_COUNT_MASK 0x0001ffffUL
259 #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
260 #define WAIT_REG 0x40 /* Bi only */
262 #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
263 # define COMMAND_PHASE BIT(0)
279 #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
281 #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
282 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
285 #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
286 #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
288 #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
289 #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
290 #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
291 #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
298 #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
299 # define CLOCK_2 BIT(0) /* MCLK/2 */
303 #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
304 # define BPWR BIT(0)
307 #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
308 #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
309 # define LED_ON (0)
310 # define LED_OFF BIT(0)
312 #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
313 # define IRQSELECT_RESELECT_IRQ BIT(0)
325 #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
326 # define OLD_MSG BIT(0)
331 #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
332 #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
334 #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
335 # define ROM_WRITE_ENB BIT(0)
339 #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
341 #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
343 #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
352 #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
353 #define MISC_RD 0x0c
354 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
364 #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
365 # define BM_CYCLE0 BIT(0)
375 #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
376 # define SREQ_EDGH_SELECT BIT(0)
378 #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
379 # define REQCNT_UP BIT(0)
385 #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
386 #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
387 #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
388 #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
389 #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
391 #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
392 # define SCL BIT(0)
396 #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
397 #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
398 #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
399 #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
400 #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
401 #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
402 #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
403 #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
404 #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
405 #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
406 #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
407 #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
408 #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
409 #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
415 #define BUSMON_BUS_FREE 0
453 u8 cdb[4 * 0x10]; /* SCSI Command */
473 #define NSP32_TRANSFER_BUSMASTER BIT(0)
484 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
519 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
524 #define FAST5M 0x32
525 #define FAST10M 0x19
526 #define ULTRA20M 0x0c
529 #define ASYNC_OFFSET 0 /* asynchronous transfer */
530 #define SYNC_OFFSET 0xf /* synchronous transfer max offset */
535 #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
549 unsigned char period; /* sync period (0-255) */
550 unsigned char offset; /* sync offset (0-15) */
551 int sync_flag; /* SDTR_*, 0 */
562 #define NSP32_MMIO_OFFSET 0x0800