299 #define NSP32_DEBUG_INTR		BIT(3)  macro
435 	nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
438 		nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
1174 	nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1178 		nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1201 		nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");  in do_nsp32_isr()
1237 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1262 			nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");  in do_nsp32_isr()
1274 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1278 			nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",  in do_nsp32_isr()
1280 			nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",  in do_nsp32_isr()
1282 			nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",  in do_nsp32_isr()
1284 			nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",  in do_nsp32_isr()
1343 			nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");  in do_nsp32_isr()
1355 		nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");  in do_nsp32_isr()
1359 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");  in do_nsp32_isr()
1366 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");  in do_nsp32_isr()
1373 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");  in do_nsp32_isr()
1379 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");  in do_nsp32_isr()
1380 			nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x",  in do_nsp32_isr()
1391 		nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");  in do_nsp32_isr()
1395 			nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");  in do_nsp32_isr()
1410 		nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");  in do_nsp32_isr()
1425 	nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1437 	nsp32_dbg(NSP32_DEBUG_INTR, "exit");  in do_nsp32_isr()