Lines Matching +full:3 +full:- +full:byte
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
109 } __packed mem_type:5; /* Byte 0 Bits 0-4 */
110 unsigned rsvd:1; /* Byte 0 Bit 5 */
111 unsigned mem_parity:1; /* Byte 0 Bit 6 */
112 unsigned mem_ecc:1; /* Byte 0 Bit 7 */
132 unsigned char rsvd1; /* Byte 0 */
137 } __packed bus; /* Byte 1 */
170 } __packed ctlr_type; /* Byte 2 */
171 unsigned char rsvd2; /* Byte 3 */
172 unsigned short bus_speed_mhz; /* Bytes 4-5 */
173 unsigned char bus_width; /* Byte 6 */
174 unsigned char flash_code; /* Byte 7 */
175 unsigned char ports_present; /* Byte 8 */
176 unsigned char rsvd3[7]; /* Bytes 9-15 */
177 unsigned char bus_name[16]; /* Bytes 16-31 */
178 unsigned char ctlr_name[16]; /* Bytes 32-47 */
179 unsigned char rsvd4[16]; /* Bytes 48-63 */
181 unsigned char fw_major_version; /* Byte 64 */
182 unsigned char fw_minor_version; /* Byte 65 */
183 unsigned char fw_turn_number; /* Byte 66 */
184 unsigned char fw_build_number; /* Byte 67 */
185 unsigned char fw_release_day; /* Byte 68 */
186 unsigned char fw_release_month; /* Byte 69 */
187 unsigned char fw_release_year_hi; /* Byte 70 */
188 unsigned char fw_release_year_lo; /* Byte 71 */
190 unsigned char hw_rev; /* Byte 72 */
191 unsigned char rsvd5[3]; /* Bytes 73-75 */
192 unsigned char hw_release_day; /* Byte 76 */
193 unsigned char hw_release_month; /* Byte 77 */
194 unsigned char hw_release_year_hi; /* Byte 78 */
195 unsigned char hw_release_year_lo; /* Byte 79 */
197 unsigned char manuf_batch_num; /* Byte 80 */
198 unsigned char rsvd6; /* Byte 81 */
199 unsigned char manuf_plant_num; /* Byte 82 */
200 unsigned char rsvd7; /* Byte 83 */
201 unsigned char hw_manuf_day; /* Byte 84 */
202 unsigned char hw_manuf_month; /* Byte 85 */
203 unsigned char hw_manuf_year_hi; /* Byte 86 */
204 unsigned char hw_manuf_year_lo; /* Byte 87 */
205 unsigned char max_pd_per_xld; /* Byte 88 */
206 unsigned char max_ild_per_xld; /* Byte 89 */
207 unsigned short nvram_size_kb; /* Bytes 90-91 */
208 unsigned char max_xld; /* Byte 92 */
209 unsigned char rsvd8[3]; /* Bytes 93-95 */
211 unsigned char serial_number[16]; /* Bytes 96-111 */
212 unsigned char rsvd9[16]; /* Bytes 112-127 */
214 unsigned char rsvd10[3]; /* Bytes 128-130 */
215 unsigned char oem_code; /* Byte 131 */
216 unsigned char vendor[16]; /* Bytes 132-147 */
218 unsigned char bbu_present:1; /* Byte 148 Bit 0 */
219 unsigned char cluster_mode:1; /* Byte 148 Bit 1 */
220 unsigned char rsvd11:6; /* Byte 148 Bits 2-7 */
221 unsigned char rsvd12[3]; /* Bytes 149-151 */
223 unsigned char pscan_active:1; /* Byte 152 Bit 0 */
224 unsigned char rsvd13:7; /* Byte 152 Bits 1-7 */
225 unsigned char pscan_chan; /* Byte 153 */
226 unsigned char pscan_target; /* Byte 154 */
227 unsigned char pscan_lun; /* Byte 155 */
229 unsigned short max_transfer_size; /* Bytes 156-157 */
230 unsigned short max_sge; /* Bytes 158-159 */
232 unsigned short ldev_present; /* Bytes 160-161 */
233 unsigned short ldev_critical; /* Bytes 162-163 */
234 unsigned short ldev_offline; /* Bytes 164-165 */
235 unsigned short pdev_present; /* Bytes 166-167 */
236 unsigned short pdisk_present; /* Bytes 168-169 */
237 unsigned short pdisk_critical; /* Bytes 170-171 */
238 unsigned short pdisk_offline; /* Bytes 172-173 */
239 unsigned short max_tcq; /* Bytes 174-175 */
241 unsigned char physchan_present; /* Byte 176 */
242 unsigned char virtchan_present; /* Byte 177 */
243 unsigned char physchan_max; /* Byte 178 */
244 unsigned char virtchan_max; /* Byte 179 */
245 unsigned char max_targets[16]; /* Bytes 180-195 */
246 unsigned char rsvd14[12]; /* Bytes 196-207 */
248 unsigned short mem_size_mb; /* Bytes 208-209 */
249 unsigned short cache_size_mb; /* Bytes 210-211 */
250 unsigned int valid_cache_bytes; /* Bytes 212-215 */
251 unsigned int dirty_cache_bytes; /* Bytes 216-219 */
252 unsigned short mem_speed_mhz; /* Bytes 220-221 */
253 unsigned char mem_data_width; /* Byte 222 */
254 struct myrs_mem_type mem_type; /* Byte 223 */
255 unsigned char cache_mem_type_name[16]; /* Bytes 224-239 */
257 unsigned short exec_mem_size_mb; /* Bytes 240-241 */
258 unsigned short exec_l2_cache_size_mb; /* Bytes 242-243 */
259 unsigned char rsvd15[8]; /* Bytes 244-251 */
260 unsigned short exec_mem_speed_mhz; /* Bytes 252-253 */
261 unsigned char exec_mem_data_width; /* Byte 254 */
262 struct myrs_mem_type exec_mem_type; /* Byte 255 */
263 unsigned char exec_mem_type_name[16]; /* Bytes 256-271 */
265 struct { /* Bytes 272-335 */
273 unsigned short cur_prof_page_num; /* Bytes 336-337 */
274 unsigned short num_prof_waiters; /* Bytes 338-339 */
275 unsigned short cur_trace_page_num; /* Bytes 340-341 */
276 unsigned short num_trace_waiters; /* Bytes 342-343 */
277 unsigned char rsvd18[8]; /* Bytes 344-351 */
279 unsigned short pdev_bus_resets; /* Bytes 352-353 */
280 unsigned short pdev_parity_errors; /* Bytes 355-355 */
281 unsigned short pdev_soft_errors; /* Bytes 356-357 */
282 unsigned short pdev_cmds_failed; /* Bytes 358-359 */
283 unsigned short pdev_misc_errors; /* Bytes 360-361 */
284 unsigned short pdev_cmd_timeouts; /* Bytes 362-363 */
285 unsigned short pdev_sel_timeouts; /* Bytes 364-365 */
286 unsigned short pdev_retries_done; /* Bytes 366-367 */
287 unsigned short pdev_aborts_done; /* Bytes 368-369 */
288 unsigned short pdev_host_aborts_done; /* Bytes 370-371 */
289 unsigned short pdev_predicted_failures; /* Bytes 372-373 */
290 unsigned short pdev_host_cmds_failed; /* Bytes 374-375 */
291 unsigned short pdev_hard_errors; /* Bytes 376-377 */
292 unsigned char rsvd19[6]; /* Bytes 378-383 */
294 unsigned short ldev_soft_errors; /* Bytes 384-385 */
295 unsigned short ldev_cmds_failed; /* Bytes 386-387 */
296 unsigned short ldev_host_aborts_done; /* Bytes 388-389 */
297 unsigned char rsvd20[2]; /* Bytes 390-391 */
299 unsigned short ctlr_mem_errors; /* Bytes 392-393 */
300 unsigned short ctlr_host_aborts_done; /* Bytes 394-395 */
301 unsigned char rsvd21[4]; /* Bytes 396-399 */
303 unsigned short bg_init_active; /* Bytes 400-401 */
304 unsigned short ldev_init_active; /* Bytes 402-403 */
305 unsigned short pdev_init_active; /* Bytes 404-405 */
306 unsigned short cc_active; /* Bytes 406-407 */
307 unsigned short rbld_active; /* Bytes 408-409 */
308 unsigned short exp_active; /* Bytes 410-411 */
309 unsigned short patrol_active; /* Bytes 412-413 */
310 unsigned char rsvd22[2]; /* Bytes 414-415 */
312 unsigned char flash_type; /* Byte 416 */
313 unsigned char rsvd23; /* Byte 417 */
314 unsigned short flash_size_MB; /* Bytes 418-419 */
315 unsigned int flash_limit; /* Bytes 420-423 */
316 unsigned int flash_count; /* Bytes 424-427 */
317 unsigned char rsvd24[4]; /* Bytes 428-431 */
318 unsigned char flash_type_name[16]; /* Bytes 432-447 */
320 unsigned char rbld_rate; /* Byte 448 */
321 unsigned char bg_init_rate; /* Byte 449 */
322 unsigned char fg_init_rate; /* Byte 450 */
323 unsigned char cc_rate; /* Byte 451 */
324 unsigned char rsvd25[4]; /* Bytes 452-455 */
325 unsigned int max_dp; /* Bytes 456-459 */
326 unsigned int free_dp; /* Bytes 460-463 */
327 unsigned int max_iop; /* Bytes 464-467 */
328 unsigned int free_iop; /* Bytes 468-471 */
329 unsigned short max_combined_len; /* Bytes 472-473 */
330 unsigned short num_cfg_groups; /* Bytes 474-475 */
331 unsigned installation_abort_status:1; /* Byte 476 Bit 0 */
332 unsigned maint_mode_status:1; /* Byte 476 Bit 1 */
333 unsigned rsvd26:6; /* Byte 476 Bits 2-7 */
334 unsigned char rsvd27[6]; /* Bytes 477-511 */
335 unsigned char rsvd28[512]; /* Bytes 512-1023 */
361 MYRS_RAID_LEVEL3 = 0x3, /* RAID 3 right asymmetric parity */
366 MYRS_RAID_LEVEL3F = 0x9, /* RAID 3 fixed parity */
367 MYRS_RAID_LEVEL3L = 0xb, /* RAID 3 left symmetric parity */
406 unsigned char ctlr; /* Byte 0 */
407 unsigned char channel; /* Byte 1 */
408 unsigned char target; /* Byte 2 */
409 unsigned char lun; /* Byte 3 */
410 enum myrs_devstate dev_state; /* Byte 4 */
411 unsigned char raid_level; /* Byte 5 */
412 enum myrs_stripe_size stripe_size; /* Byte 6 */
413 enum myrs_cacheline_size cacheline_size; /* Byte 7 */
421 } __packed rce:3; /* Byte 8 Bits 0-2 */
428 } __packed wce:3; /* Byte 8 Bits 3-5 */
429 unsigned rsvd1:1; /* Byte 8 Bit 6 */
430 unsigned ldev_init_done:1; /* Byte 8 Bit 7 */
431 } ldev_control; /* Byte 8 */
433 unsigned char cc_active:1; /* Byte 9 Bit 0 */
434 unsigned char rbld_active:1; /* Byte 9 Bit 1 */
435 unsigned char bg_init_active:1; /* Byte 9 Bit 2 */
436 unsigned char fg_init_active:1; /* Byte 9 Bit 3 */
437 unsigned char migration_active:1; /* Byte 9 Bit 4 */
438 unsigned char patrol_active:1; /* Byte 9 Bit 5 */
439 unsigned char rsvd2:2; /* Byte 9 Bits 6-7 */
440 unsigned char raid5_writeupdate; /* Byte 10 */
441 unsigned char raid5_algo; /* Byte 11 */
442 unsigned short ldev_num; /* Bytes 12-13 */
444 unsigned char bios_disabled:1; /* Byte 14 Bit 0 */
445 unsigned char cdrom_boot:1; /* Byte 14 Bit 1 */
446 unsigned char drv_coercion:1; /* Byte 14 Bit 2 */
447 unsigned char write_same_disabled:1; /* Byte 14 Bit 3 */
448 unsigned char hba_mode:1; /* Byte 14 Bit 4 */
454 } __packed drv_geom:2; /* Byte 14 Bits 5-6 */
455 unsigned char super_ra_enabled:1; /* Byte 14 Bit 7 */
456 unsigned char rsvd3; /* Byte 15 */
458 unsigned short soft_errs; /* Bytes 16-17 */
459 unsigned short cmds_failed; /* Bytes 18-19 */
460 unsigned short cmds_aborted; /* Bytes 20-21 */
461 unsigned short deferred_write_errs; /* Bytes 22-23 */
462 unsigned int rsvd4; /* Bytes 24-27 */
463 unsigned int rsvd5; /* Bytes 28-31 */
465 unsigned short rsvd6; /* Bytes 32-33 */
466 unsigned short devsize_bytes; /* Bytes 34-35 */
467 unsigned int orig_devsize; /* Bytes 36-39 */
468 unsigned int cfg_devsize; /* Bytes 40-43 */
469 unsigned int rsvd7; /* Bytes 44-47 */
470 unsigned char ldev_name[32]; /* Bytes 48-79 */
471 unsigned char inquiry[36]; /* Bytes 80-115 */
472 unsigned char rsvd8[12]; /* Bytes 116-127 */
473 u64 last_read_lba; /* Bytes 128-135 */
474 u64 last_write_lba; /* Bytes 136-143 */
475 u64 cc_lba; /* Bytes 144-151 */
476 u64 rbld_lba; /* Bytes 152-159 */
477 u64 bg_init_lba; /* Bytes 160-167 */
478 u64 fg_init_lba; /* Bytes 168-175 */
479 u64 migration_lba; /* Bytes 176-183 */
480 u64 patrol_lba; /* Bytes 184-191 */
481 unsigned char rsvd9[64]; /* Bytes 192-255 */
488 unsigned char rsvd1; /* Byte 0 */
489 unsigned char channel; /* Byte 1 */
490 unsigned char target; /* Byte 2 */
491 unsigned char lun; /* Byte 3 */
493 unsigned char pdev_fault_tolerant:1; /* Byte 4 Bit 0 */
494 unsigned char pdev_connected:1; /* Byte 4 Bit 1 */
495 unsigned char pdev_local_to_ctlr:1; /* Byte 4 Bit 2 */
496 unsigned char rsvd2:5; /* Byte 4 Bits 3-7 */
498 unsigned char remote_host_dead:1; /* Byte 5 Bit 0 */
499 unsigned char remove_ctlr_dead:1; /* Byte 5 Bit 1 */
500 unsigned char rsvd3:6; /* Byte 5 Bits 2-7 */
501 enum myrs_devstate dev_state; /* Byte 6 */
502 unsigned char nego_data_width; /* Byte 7 */
503 unsigned short nego_sync_rate; /* Bytes 8-9 */
505 unsigned char num_ports; /* Byte 10 */
506 unsigned char drv_access_bitmap; /* Byte 11 */
507 unsigned int rsvd4; /* Bytes 12-15 */
508 unsigned char ip_address[16]; /* Bytes 16-31 */
509 unsigned short max_tags; /* Bytes 32-33 */
511 unsigned char cc_in_progress:1; /* Byte 34 Bit 0 */
512 unsigned char rbld_in_progress:1; /* Byte 34 Bit 1 */
513 unsigned char makecc_in_progress:1; /* Byte 34 Bit 2 */
514 unsigned char pdevinit_in_progress:1; /* Byte 34 Bit 3 */
515 unsigned char migration_in_progress:1; /* Byte 34 Bit 4 */
516 unsigned char patrol_in_progress:1; /* Byte 34 Bit 5 */
517 unsigned char rsvd5:2; /* Byte 34 Bits 6-7 */
518 unsigned char long_op_status; /* Byte 35 */
519 unsigned char parity_errs; /* Byte 36 */
520 unsigned char soft_errs; /* Byte 37 */
521 unsigned char hard_errs; /* Byte 38 */
522 unsigned char misc_errs; /* Byte 39 */
523 unsigned char cmd_timeouts; /* Byte 40 */
524 unsigned char retries; /* Byte 41 */
525 unsigned char aborts; /* Byte 42 */
526 unsigned char pred_failures; /* Byte 43 */
527 unsigned int rsvd6; /* Bytes 44-47 */
528 unsigned short rsvd7; /* Bytes 48-49 */
529 unsigned short devsize_bytes; /* Bytes 50-51 */
530 unsigned int orig_devsize; /* Bytes 52-55 */
531 unsigned int cfg_devsize; /* Bytes 56-59 */
532 unsigned int rsvd8; /* Bytes 60-63 */
533 unsigned char pdev_name[16]; /* Bytes 64-79 */
534 unsigned char rsvd9[16]; /* Bytes 80-95 */
535 unsigned char rsvd10[32]; /* Bytes 96-127 */
536 unsigned char inquiry[36]; /* Bytes 128-163 */
537 unsigned char rsvd11[20]; /* Bytes 164-183 */
538 unsigned char rsvd12[8]; /* Bytes 184-191 */
539 u64 last_read_lba; /* Bytes 192-199 */
540 u64 last_write_lba; /* Bytes 200-207 */
541 u64 cc_lba; /* Bytes 208-215 */
542 u64 rbld_lba; /* Bytes 216-223 */
543 u64 makecc_lba; /* Bytes 224-231 */
544 u64 devinit_lba; /* Bytes 232-239 */
545 u64 migration_lba; /* Bytes 240-247 */
546 u64 patrol_lba; /* Bytes 248-255 */
547 unsigned char rsvd13[256]; /* Bytes 256-511 */
554 unsigned int uptime_usecs; /* Bytes 0-3 */
555 unsigned int uptime_msecs; /* Bytes 4-7 */
556 unsigned int seconds; /* Bytes 8-11 */
557 unsigned char rsvd1[4]; /* Bytes 12-15 */
558 unsigned int epoch; /* Bytes 16-19 */
559 unsigned char rsvd2[4]; /* Bytes 20-23 */
560 unsigned int dbg_msgbuf_idx; /* Bytes 24-27 */
561 unsigned int coded_msgbuf_idx; /* Bytes 28-31 */
562 unsigned int cur_timetrace_page; /* Bytes 32-35 */
563 unsigned int cur_prof_page; /* Bytes 36-39 */
564 unsigned int next_evseq; /* Bytes 40-43 */
565 unsigned char rsvd3[4]; /* Bytes 44-47 */
566 unsigned char rsvd4[16]; /* Bytes 48-63 */
567 unsigned char rsvd5[64]; /* Bytes 64-127 */
574 unsigned int ev_seq; /* Bytes 0-3 */
575 unsigned int ev_time; /* Bytes 4-7 */
576 unsigned int ev_code; /* Bytes 8-11 */
577 unsigned char rsvd1; /* Byte 12 */
578 unsigned char channel; /* Byte 13 */
579 unsigned char target; /* Byte 14 */
580 unsigned char lun; /* Byte 15 */
581 unsigned int rsvd2; /* Bytes 16-19 */
582 unsigned int ev_parm; /* Bytes 20-23 */
583 unsigned char sense_data[40]; /* Bytes 24-63 */
590 unsigned char fua:1; /* Byte 0 Bit 0 */
591 unsigned char disable_pgout:1; /* Byte 0 Bit 1 */
592 unsigned char rsvd1:1; /* Byte 0 Bit 2 */
593 unsigned char add_sge_mem:1; /* Byte 0 Bit 3 */
594 unsigned char dma_ctrl_to_host:1; /* Byte 0 Bit 4 */
595 unsigned char rsvd2:1; /* Byte 0 Bit 5 */
596 unsigned char no_autosense:1; /* Byte 0 Bit 6 */
597 unsigned char disc_prohibited:1; /* Byte 0 Bit 7 */
604 unsigned char tmo_val:6; /* Byte 0 Bits 0-5 */
609 MYRS_TMO_SCALE_RESERVED = 3
610 } __packed tmo_scale:2; /* Byte 0 Bits 6-7 */
617 unsigned char lun; /* Byte 0 */
618 unsigned char target; /* Byte 1 */
619 unsigned char channel:3; /* Byte 2 Bits 0-2 */
620 unsigned char ctlr:5; /* Byte 2 Bits 3-7 */
627 unsigned short ldev_num; /* Bytes 0-1 */
628 unsigned char rsvd:3; /* Byte 2 Bits 0-2 */
629 unsigned char ctlr:5; /* Byte 2 Bits 3-7 */
650 unsigned short ldev_num; /* Bytes 0-1 */
651 unsigned short rsvd; /* Bytes 2-3 */
652 unsigned char prev_boot_ctlr; /* Byte 4 */
653 unsigned char prev_boot_channel; /* Byte 5 */
654 unsigned char prev_boot_target; /* Byte 6 */
655 unsigned char prev_boot_lun; /* Byte 7 */
662 u64 sge_addr; /* Bytes 0-7 */
663 u64 sge_count; /* Bytes 8-15 */
670 struct myrs_sge sge[2]; /* Bytes 0-31 */
672 unsigned short sge0_len; /* Bytes 0-1 */
673 unsigned short sge1_len; /* Bytes 2-3 */
674 unsigned short sge2_len; /* Bytes 4-5 */
675 unsigned short rsvd; /* Bytes 6-7 */
676 u64 sge0_addr; /* Bytes 8-15 */
677 u64 sge1_addr; /* Bytes 16-23 */
678 u64 sge2_addr; /* Bytes 24-31 */
683 * 64 Byte DAC960 V2 Firmware Command Mailbox structure.
686 unsigned int words[16]; /* Words 0-15 */
688 unsigned short id; /* Bytes 0-1 */
689 enum myrs_cmd_opcode opcode; /* Byte 2 */
690 struct myrs_cmd_ctrl control; /* Byte 3 */
691 u32 dma_size:24; /* Bytes 4-6 */
692 unsigned char dma_num; /* Byte 7 */
693 u64 sense_addr; /* Bytes 8-15 */
694 unsigned int rsvd1:24; /* Bytes 16-18 */
695 struct myrs_cmd_tmo tmo; /* Byte 19 */
696 unsigned char sense_len; /* Byte 20 */
697 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
698 unsigned char rsvd2[10]; /* Bytes 22-31 */
699 union myrs_sgl dma_addr; /* Bytes 32-63 */
702 unsigned short id; /* Bytes 0-1 */
703 enum myrs_cmd_opcode opcode; /* Byte 2 */
704 struct myrs_cmd_ctrl control; /* Byte 3 */
705 u32 dma_size; /* Bytes 4-7 */
706 u64 sense_addr; /* Bytes 8-15 */
707 struct myrs_pdev pdev; /* Bytes 16-18 */
708 struct myrs_cmd_tmo tmo; /* Byte 19 */
709 unsigned char sense_len; /* Byte 20 */
710 unsigned char cdb_len; /* Byte 21 */
711 unsigned char cdb[10]; /* Bytes 22-31 */
712 union myrs_sgl dma_addr; /* Bytes 32-63 */
715 unsigned short id; /* Bytes 0-1 */
716 enum myrs_cmd_opcode opcode; /* Byte 2 */
717 struct myrs_cmd_ctrl control; /* Byte 3 */
718 u32 dma_size; /* Bytes 4-7 */
719 u64 sense_addr; /* Bytes 8-15 */
720 struct myrs_pdev pdev; /* Bytes 16-18 */
721 struct myrs_cmd_tmo tmo; /* Byte 19 */
722 unsigned char sense_len; /* Byte 20 */
723 unsigned char cdb_len; /* Byte 21 */
724 unsigned short rsvd; /* Bytes 22-23 */
725 u64 cdb_addr; /* Bytes 24-31 */
726 union myrs_sgl dma_addr; /* Bytes 32-63 */
729 unsigned short id; /* Bytes 0-1 */
730 enum myrs_cmd_opcode opcode; /* Byte 2 */
731 struct myrs_cmd_ctrl control; /* Byte 3 */
732 u32 dma_size:24; /* Bytes 4-6 */
733 unsigned char dma_num; /* Byte 7 */
734 u64 sense_addr; /* Bytes 8-15 */
735 unsigned short rsvd1; /* Bytes 16-17 */
736 unsigned char ctlr_num; /* Byte 18 */
737 struct myrs_cmd_tmo tmo; /* Byte 19 */
738 unsigned char sense_len; /* Byte 20 */
739 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
740 unsigned char rsvd2[10]; /* Bytes 22-31 */
741 union myrs_sgl dma_addr; /* Bytes 32-63 */
744 unsigned short id; /* Bytes 0-1 */
745 enum myrs_cmd_opcode opcode; /* Byte 2 */
746 struct myrs_cmd_ctrl control; /* Byte 3 */
747 u32 dma_size:24; /* Bytes 4-6 */
748 unsigned char dma_num; /* Byte 7 */
749 u64 sense_addr; /* Bytes 8-15 */
750 struct myrs_ldev ldev; /* Bytes 16-18 */
751 struct myrs_cmd_tmo tmo; /* Byte 19 */
752 unsigned char sense_len; /* Byte 20 */
753 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
754 unsigned char rsvd[10]; /* Bytes 22-31 */
755 union myrs_sgl dma_addr; /* Bytes 32-63 */
758 unsigned short id; /* Bytes 0-1 */
759 enum myrs_cmd_opcode opcode; /* Byte 2 */
760 struct myrs_cmd_ctrl control; /* Byte 3 */
761 u32 dma_size:24; /* Bytes 4-6 */
762 unsigned char dma_num; /* Byte 7 */
763 u64 sense_addr; /* Bytes 8-15 */
764 struct myrs_pdev pdev; /* Bytes 16-18 */
765 struct myrs_cmd_tmo tmo; /* Byte 19 */
766 unsigned char sense_len; /* Byte 20 */
767 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
768 unsigned char rsvd[10]; /* Bytes 22-31 */
769 union myrs_sgl dma_addr; /* Bytes 32-63 */
772 unsigned short id; /* Bytes 0-1 */
773 enum myrs_cmd_opcode opcode; /* Byte 2 */
774 struct myrs_cmd_ctrl control; /* Byte 3 */
775 u32 dma_size:24; /* Bytes 4-6 */
776 unsigned char dma_num; /* Byte 7 */
777 u64 sense_addr; /* Bytes 8-15 */
778 unsigned short evnum_upper; /* Bytes 16-17 */
779 unsigned char ctlr_num; /* Byte 18 */
780 struct myrs_cmd_tmo tmo; /* Byte 19 */
781 unsigned char sense_len; /* Byte 20 */
782 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
783 unsigned short evnum_lower; /* Bytes 22-23 */
784 unsigned char rsvd[8]; /* Bytes 24-31 */
785 union myrs_sgl dma_addr; /* Bytes 32-63 */
788 unsigned short id; /* Bytes 0-1 */
789 enum myrs_cmd_opcode opcode; /* Byte 2 */
790 struct myrs_cmd_ctrl control; /* Byte 3 */
791 u32 dma_size:24; /* Bytes 4-6 */
792 unsigned char dma_num; /* Byte 7 */
793 u64 sense_addr; /* Bytes 8-15 */
795 struct myrs_ldev ldev; /* Bytes 16-18 */
796 struct myrs_pdev pdev; /* Bytes 16-18 */
798 struct myrs_cmd_tmo tmo; /* Byte 19 */
799 unsigned char sense_len; /* Byte 20 */
800 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
801 enum myrs_devstate state; /* Byte 22 */
802 unsigned char rsvd[9]; /* Bytes 23-31 */
803 union myrs_sgl dma_addr; /* Bytes 32-63 */
806 unsigned short id; /* Bytes 0-1 */
807 enum myrs_cmd_opcode opcode; /* Byte 2 */
808 struct myrs_cmd_ctrl control; /* Byte 3 */
809 u32 dma_size:24; /* Bytes 4-6 */
810 unsigned char dma_num; /* Byte 7 */
811 u64 sense_addr; /* Bytes 8-15 */
812 struct myrs_ldev ldev; /* Bytes 16-18 */
813 struct myrs_cmd_tmo tmo; /* Byte 19 */
814 unsigned char sense_len; /* Byte 20 */
815 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
816 unsigned char restore_consistency:1; /* Byte 22 Bit 0 */
817 unsigned char initialized_area_only:1; /* Byte 22 Bit 1 */
818 unsigned char rsvd1:6; /* Byte 22 Bits 2-7 */
819 unsigned char rsvd2[9]; /* Bytes 23-31 */
820 union myrs_sgl dma_addr; /* Bytes 32-63 */
823 unsigned short id; /* Bytes 0-1 */
824 enum myrs_cmd_opcode opcode; /* Byte 2 */
825 struct myrs_cmd_ctrl control; /* Byte 3 */
826 unsigned char first_cmd_mbox_size_kb; /* Byte 4 */
827 unsigned char first_stat_mbox_size_kb; /* Byte 5 */
828 unsigned char second_cmd_mbox_size_kb; /* Byte 6 */
829 unsigned char second_stat_mbox_size_kb; /* Byte 7 */
830 u64 sense_addr; /* Bytes 8-15 */
831 unsigned int rsvd1:24; /* Bytes 16-18 */
832 struct myrs_cmd_tmo tmo; /* Byte 19 */
833 unsigned char sense_len; /* Byte 20 */
834 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
835 unsigned char fwstat_buf_size_kb; /* Byte 22 */
836 unsigned char rsvd2; /* Byte 23 */
837 u64 fwstat_buf_addr; /* Bytes 24-31 */
838 u64 first_cmd_mbox_addr; /* Bytes 32-39 */
839 u64 first_stat_mbox_addr; /* Bytes 40-47 */
840 u64 second_cmd_mbox_addr; /* Bytes 48-55 */
841 u64 second_stat_mbox_addr; /* Bytes 56-63 */
844 unsigned short id; /* Bytes 0-1 */
845 enum myrs_cmd_opcode opcode; /* Byte 2 */
846 struct myrs_cmd_ctrl control; /* Byte 3 */
847 u32 dma_size:24; /* Bytes 4-6 */
848 unsigned char dma_num; /* Byte 7 */
849 u64 sense_addr; /* Bytes 8-15 */
850 struct myrs_pdev pdev; /* Bytes 16-18 */
851 struct myrs_cmd_tmo tmo; /* Byte 19 */
852 unsigned char sense_len; /* Byte 20 */
853 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
854 enum myrs_opdev opdev; /* Byte 22 */
855 unsigned char rsvd[9]; /* Bytes 23-31 */
856 union myrs_sgl dma_addr; /* Bytes 32-63 */
864 unsigned short id; /* Bytes 0-1 */
865 unsigned char status; /* Byte 2 */
866 unsigned char sense_len; /* Byte 3 */
867 int residual; /* Bytes 4-7 */
1013 * to a 64-bit pci address space register. The controller
1014 * will accept having the register written as two 32-bit
1017 * In HIGHMEM kernels, dma_addr_t is a 64-bit value.
1018 * without HIGHMEM, dma_addr_t is a 32-bit value.