Lines Matching +full:i2c +full:- +full:crc +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0-only */
7  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 	MVS_TX_RING_SZ		= 1024,	/* TX ring size (12-bit) */
31 	MVS_RX_RING_SZ		= 1024, /* RX ring size (12-bit) */
32 					/* software requires power-of-2
44 	MVS_SOC_CAN_QUEUE	= MVS_SOC_SLOTS - 2,
72 	INT_EN			= (1U << 1),	/* Global int enable */
79 	/* MVS_GBL_PORT_TYPE */			/* shl for ports 1-3 */
80 	SATA_TARGET		= (1U << 16),	/* port0 SATA target enable */
112 	TX_EN			= (1U << 16),	/* Enable TX */
116 	RX_EN			= (1U << 16),	/* Enable RX */
120 	COAL_EN			= (1U << 16),	/* Enable int coalescing */
123 	CINT_I2C		= (1U << 31),	/* I2C event */
129 	CINT_I2C_SLAVE		= (1U << 25),	/* slave I2C event */
135 						/* shl for ports 1-3 */
173 	MCH_PRD_LEN_SHIFT	= 16,		/* 16-bit PRD table len */
190 	MCH_PASSTHRU		= (1U << 12),	/* pass-through (SSP) */
209 	/* MVS_Px_SER_CTLSTAT (per-phy control) */
216 	/* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
219 	PHYEV_CRC_ERR		= (1U << 22),	/* STP CRC Error */
224 	PHYEV_POOF		= (1U << 12),	/* phy ready from 1 -> 0 */
239 	PCS_EN_SATA_REG_SHIFT	= (16),		/* Enable SATA Register Set */
240 	PCS_EN_PORT_XMT_SHIFT	= (12),		/* Enable Port Transmit */
245 	PCS_SELF_CLEAR		= (1U << 5),	/* self-clearing int mode */
246 	PCS_FIS_RX_EN		= (1U << 4),	/* FIS rx enable */
247 	PCS_CMD_STOP_ERR	= (1U << 3),	/* cmd stop-on-err enable */
249 	PCS_CMD_EN		= (1U << 0),	/* enable cmd issue */
275 	PHY_MODE6_MUCNT_EN	= (1U << 24),	/* u Count Enable */
282 	PHY_MODE6_INT_RXFOFFS	= (1U << 3),	/* Rx CDR Freq Loop Enable */
298 	PHYR_SATA_SIG0	= 0x20,	/*port SATA signature FIS(Byte 0-3) */
299 	PHYR_SATA_SIG1	= 0x24,	/*port SATA signature FIS(Byte 4-7) */
300 	PHYR_SATA_SIG2	= 0x28,	/*port SATA signature FIS(Byte 8-11) */
301 	PHYR_SATA_SIG3	= 0x2c,	/*port SATA signature FIS(Byte 12-15) */
303 	PHYR_CRC_ERR_COUNT	= 0x34, /* port CRC error count register */