Lines Matching +full:0 +full:x000000c8
16 * with MPI v2.0 products. Unless otherwise noted, names beginning with
17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
28 * Moved ReplyPostHostIndex register to offset 0x6C of the
39 * product specific codes up to 0xEFFF.
41 * and changed the flush value to 0x0.
69 * function codes, 0xF0 to 0xFF.
146 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
148 #define MPI2_VERSION_MINOR_MASK (0x00FF)
149 #define MPI2_VERSION_MINOR_SHIFT (0)
152 #define MPI2_VERSION_MAJOR (0x02)
154 /*minor version for MPI v2.0 compatible products */
155 #define MPI2_VERSION_MINOR (0x00)
158 #define MPI2_VERSION_02_00 (0x0200)
161 #define MPI25_VERSION_MINOR (0x05)
164 #define MPI2_VERSION_02_05 (0x0205)
167 #define MPI26_VERSION_MINOR (0x06)
170 #define MPI2_VERSION_02_06 (0x0206)
174 #define MPI2_HEADER_VERSION_UNIT (0x3E)
175 #define MPI2_HEADER_VERSION_DEV (0x00)
176 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
178 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
179 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
189 #define MPI2_IOC_STATE_RESET (0x00000000)
190 #define MPI2_IOC_STATE_READY (0x10000000)
191 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
192 #define MPI2_IOC_STATE_FAULT (0x40000000)
193 #define MPI2_IOC_STATE_COREDUMP (0x50000000)
195 #define MPI2_IOC_STATE_MASK (0xF0000000)
199 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
200 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
209 U32 Doorbell; /*0x00 */
210 U32 WriteSequence; /*0x04 */
211 U32 HostDiagnostic; /*0x08 */
212 U32 Reserved1; /*0x0C */
213 U32 DiagRWData; /*0x10 */
214 U32 DiagRWAddressLow; /*0x14 */
215 U32 DiagRWAddressHigh; /*0x18 */
216 U32 Reserved2[5]; /*0x1C */
217 U32 HostInterruptStatus; /*0x30 */
218 U32 HostInterruptMask; /*0x34 */
219 U32 DCRData; /*0x38 */
220 U32 DCRAddress; /*0x3C */
221 U32 Reserved3[2]; /*0x40 */
222 U32 ReplyFreeHostIndex; /*0x48 */
223 U32 Reserved4[8]; /*0x4C */
224 U32 ReplyPostHostIndex; /*0x6C */
225 U32 Reserved5; /*0x70 */
226 U32 HCBSize; /*0x74 */
227 U32 HCBAddressLow; /*0x78 */
228 U32 HCBAddressHigh; /*0x7C */
229 U32 Reserved6[12]; /*0x80 */
230 U32 Scratchpad[4]; /*0xB0 */
231 U32 RequestDescriptorPostLow; /*0xC0 */
232 U32 RequestDescriptorPostHigh; /*0xC4 */
233 U32 AtomicRequestDescriptorPost;/*0xC8 */
234 U32 Reserved7[13]; /*0xCC */
243 #define MPI2_DOORBELL_OFFSET (0x00000000)
246 #define MPI2_DOORBELL_USED (0x08000000)
247 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
249 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
250 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
253 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
255 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
261 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
262 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
263 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
264 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
265 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
266 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
267 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
268 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
269 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
274 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
276 #define MPI26_DIAG_SECURE_BOOT (0x80000000)
278 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
280 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
281 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
282 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
285 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
286 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
287 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
288 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
290 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
291 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
292 #define MPI2_DIAG_HCB_MODE (0x00000100)
293 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
294 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
295 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
296 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
297 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
298 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
303 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
304 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
305 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
310 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
311 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
313 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
314 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
315 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
321 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
322 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
323 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
325 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
331 #define MPI2_DCR_DATA_OFFSET (0x00000038)
332 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
337 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
342 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
343 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
344 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
346 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
352 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
353 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
354 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
356 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
357 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
362 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
363 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
364 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
365 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
370 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
371 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
372 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
389 U8 RequestFlags; /*0x00 */
390 U8 MSIxIndex; /*0x01 */
391 U16 SMID; /*0x02 */
392 U16 LMID; /*0x04 */
393 U16 DescriptorTypeDependent; /*0x06 */
400 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
402 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
403 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
404 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
405 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
406 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
407 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
408 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
410 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
414 U8 RequestFlags; /*0x00 */
415 U8 MSIxIndex; /*0x01 */
416 U16 SMID; /*0x02 */
417 U16 LMID; /*0x04 */
418 U16 Reserved1; /*0x06 */
426 U8 RequestFlags; /*0x00 */
427 U8 MSIxIndex; /*0x01 */
428 U16 SMID; /*0x02 */
429 U16 LMID; /*0x04 */
430 U16 DevHandle; /*0x06 */
438 U8 RequestFlags; /*0x00 */
439 U8 MSIxIndex; /*0x01 */
440 U16 SMID; /*0x02 */
441 U16 LMID; /*0x04 */
442 U16 IoIndex; /*0x06 */
450 U8 RequestFlags; /*0x00 */
451 U8 MSIxIndex; /*0x01 */
452 U16 SMID; /*0x02 */
453 U16 LMID; /*0x04 */
454 U16 Reserved; /*0x06 */
505 U8 RequestFlags; /* 0x00 */
506 U8 MSIxIndex; /* 0x01 */
507 U16 SMID; /* 0x02 */
521 U8 ReplyFlags; /*0x00 */
522 U8 MSIxIndex; /*0x01 */
523 U16 DescriptorTypeDependent1; /*0x02 */
524 U32 DescriptorTypeDependent2; /*0x04 */
531 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
532 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
533 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
534 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
535 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
536 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
537 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
538 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
539 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
542 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
543 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
547 U8 ReplyFlags; /*0x00 */
548 U8 MSIxIndex; /*0x01 */
549 U16 SMID; /*0x02 */
550 U32 ReplyFrameAddress; /*0x04 */
556 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
560 U8 ReplyFlags; /*0x00 */
561 U8 MSIxIndex; /*0x01 */
562 U16 SMID; /*0x02 */
563 U16 TaskTag; /*0x04 */
564 U16 Reserved1; /*0x06 */
572 U8 ReplyFlags; /*0x00 */
573 U8 MSIxIndex; /*0x01 */
574 U16 SMID; /*0x02 */
575 U8 SequenceNumber; /*0x04 */
576 U8 Reserved1; /*0x05 */
577 U16 IoIndex; /*0x06 */
585 U8 ReplyFlags; /*0x00 */
586 U8 MSIxIndex; /*0x01 */
587 U8 VP_ID; /*0x02 */
588 U8 Flags; /*0x03 */
589 U16 InitiatorDevHandle; /*0x04 */
590 U16 IoIndex; /*0x06 */
597 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
601 U8 ReplyFlags; /*0x00 */
602 U8 MSIxIndex; /*0x01 */
603 U16 SMID; /*0x02 */
604 U32 Reserved; /*0x04 */
647 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
648 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
649 #define MPI2_FUNCTION_IOC_INIT (0x02)
650 #define MPI2_FUNCTION_IOC_FACTS (0x03)
651 #define MPI2_FUNCTION_CONFIG (0x04)
652 #define MPI2_FUNCTION_PORT_FACTS (0x05)
653 #define MPI2_FUNCTION_PORT_ENABLE (0x06)
654 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
655 #define MPI2_FUNCTION_EVENT_ACK (0x08)
656 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
657 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
658 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
659 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
660 #define MPI2_FUNCTION_FW_UPLOAD (0x12)
661 #define MPI2_FUNCTION_RAID_ACTION (0x15)
662 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
663 #define MPI2_FUNCTION_TOOLBOX (0x17)
664 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
665 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
666 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
667 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
668 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
669 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
670 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
671 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
672 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
673 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
674 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
675 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
676 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
677 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33)
678 #define MPI2_FUNCTION_MCTP_PASSTHROUGH (0x34)
679 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
680 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
683 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
684 #define MPI2_FUNCTION_HANDSHAKE (0x42)
693 #define MPI2_IOCSTATUS_MASK (0x7FFF)
699 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
700 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
701 #define MPI2_IOCSTATUS_BUSY (0x0002)
702 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
703 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
704 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
705 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
706 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
707 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
708 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
710 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
711 #define MPI2_IOCSTATUS_FAILURE (0x000F)
717 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
718 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
719 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
720 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
721 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
722 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
728 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
729 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
730 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
731 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
732 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
733 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
734 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
735 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
736 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
737 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
738 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
739 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
745 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
746 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
747 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
753 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
754 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
755 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
756 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
757 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
758 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
759 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
760 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
761 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
762 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
768 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
769 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
775 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
781 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
787 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
793 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
795 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
796 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
797 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
798 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
799 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
800 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
813 U16 FunctionDependent1; /*0x00 */
814 U8 ChainOffset; /*0x02 */
815 U8 Function; /*0x03 */
816 U16 FunctionDependent2; /*0x04 */
817 U8 FunctionDependent3; /*0x06 */
818 U8 MsgFlags; /*0x07 */
819 U8 VP_ID; /*0x08 */
820 U8 VF_ID; /*0x09 */
821 U16 Reserved1; /*0x0A */
830 U16 FunctionDependent1; /*0x00 */
831 U8 MsgLength; /*0x02 */
832 U8 Function; /*0x03 */
833 U16 FunctionDependent2; /*0x04 */
834 U8 FunctionDependent3; /*0x06 */
835 U8 MsgFlags; /*0x07 */
836 U8 VP_ID; /*0x08 */
837 U8 VF_ID; /*0x09 */
838 U16 Reserved1; /*0x0A */
839 U16 FunctionDependent5; /*0x0C */
840 U16 IOCStatus; /*0x0E */
841 U32 IOCLogInfo; /*0x10 */
848 U8 Dev; /*0x00 */
849 U8 Unit; /*0x01 */
850 U8 Minor; /*0x02 */
851 U8 Major; /*0x03 */
860 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
861 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
862 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
863 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
864 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
865 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
901 * MPI Chain Element structures - for MPI v2.0 products only
934 * MPI Transaction Context Element structures - for MPI v2.0 products only
999 * MPI SGE union for IO SGL's - for MPI v2.0 products only
1011 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1043 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1044 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1045 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1046 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1047 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
1048 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1049 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1053 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1054 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1058 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
1059 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1060 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
1061 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1065 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1069 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1070 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1077 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1078 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1082 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1083 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1084 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1085 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1087 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1128 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1156 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1159 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1186 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1211 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1212 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1216 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1220 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1221 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1225 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1226 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1227 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1228 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1232 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1233 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1234 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1235 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1236 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1237 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1240 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
1295 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1296 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1297 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1298 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1299 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1300 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1302 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1303 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1304 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1305 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)