Lines Matching +full:0 +full:x02020000
34 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
35 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
36 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
37 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
38 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
39 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
40 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
41 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
42 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
43 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
44 #define PCI_DEVICE_ID_LSI_FURY 0x005f
45 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
46 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
47 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
48 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
49 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
50 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
51 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
52 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
53 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
54 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
55 #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1
56 #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2
57 #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5
58 #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6
59 #define PCI_DEVICE_ID_LSI_AERO_10E0 0x10e0
60 #define PCI_DEVICE_ID_LSI_AERO_10E3 0x10e3
61 #define PCI_DEVICE_ID_LSI_AERO_10E4 0x10e4
62 #define PCI_DEVICE_ID_LSI_AERO_10E7 0x10e7
67 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
68 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
69 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
70 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
71 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
72 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
73 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
78 #define MEGARAID_INTRUDER_SSDID1 0x9371
79 #define MEGARAID_INTRUDER_SSDID2 0x9390
80 #define MEGARAID_INTRUDER_SSDID3 0x9370
115 #define MFI_STATE_MASK 0xF0000000
116 #define MFI_STATE_UNDEFINED 0x00000000
117 #define MFI_STATE_BB_INIT 0x10000000
118 #define MFI_STATE_FW_INIT 0x40000000
119 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
120 #define MFI_STATE_FW_INIT_2 0x70000000
121 #define MFI_STATE_DEVICE_SCAN 0x80000000
122 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
123 #define MFI_STATE_FLUSH_CACHE 0xA0000000
124 #define MFI_STATE_READY 0xB0000000
125 #define MFI_STATE_OPERATIONAL 0xC0000000
126 #define MFI_STATE_FAULT 0xF0000000
127 #define MFI_STATE_FORCE_OCR 0x00000080
128 #define MFI_STATE_DMADONE 0x00000008
129 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
130 #define MFI_RESET_REQUIRED 0x00000001
131 #define MFI_RESET_ADAPTER 0x00000002
134 #define MFI_STATE_FAULT_CODE 0x0FFF0000
135 #define MFI_STATE_FAULT_SUBCODE 0x0000FF00
147 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
148 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
149 #define DIAG_WRITE_ENABLE (0x00000080)
150 #define DIAG_RESET_ADAPTER (0x00000004)
152 #define MFI_ADP_RESET 0x00000040
153 #define MFI_INIT_ABORT 0x00000001
154 #define MFI_INIT_READY 0x00000002
155 #define MFI_INIT_MFIMODE 0x00000004
156 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
157 #define MFI_INIT_HOTPLUG 0x00000010
158 #define MFI_STOP_ADP 0x00000020
162 #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100
163 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
168 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
169 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
170 #define MFI_FRAME_SGL32 0x0000
171 #define MFI_FRAME_SGL64 0x0002
172 #define MFI_FRAME_SENSE32 0x0000
173 #define MFI_FRAME_SENSE64 0x0004
174 #define MFI_FRAME_DIR_NONE 0x0000
175 #define MFI_FRAME_DIR_WRITE 0x0008
176 #define MFI_FRAME_DIR_READ 0x0010
177 #define MFI_FRAME_DIR_BOTH 0x0018
178 #define MFI_FRAME_IEEE 0x0020
181 #define DRV_DCMD_POLLED_MODE 0x1
182 #define DRV_DCMD_SKIP_REFIRE 0x2
187 #define MFI_CMD_STATUS_POLL_MODE 0xFF
193 MFI_CMD_INIT = 0x0,
194 MFI_CMD_LD_READ = 0x1,
195 MFI_CMD_LD_WRITE = 0x2,
196 MFI_CMD_LD_SCSI_IO = 0x3,
197 MFI_CMD_PD_SCSI_IO = 0x4,
198 MFI_CMD_DCMD = 0x5,
199 MFI_CMD_ABORT = 0x6,
200 MFI_CMD_SMP = 0x7,
201 MFI_CMD_STP = 0x8,
202 MFI_CMD_NVME = 0x9,
203 MFI_CMD_TOOLBOX = 0xa,
205 MFI_CMD_INVALID = 0xff
208 #define MR_DCMD_CTRL_GET_INFO 0x01010000
209 #define MR_DCMD_LD_GET_LIST 0x03010000
210 #define MR_DCMD_LD_LIST_QUERY 0x03010100
212 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
213 #define MR_FLUSH_CTRL_CACHE 0x01
214 #define MR_FLUSH_DISK_CACHE 0x02
216 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
217 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
218 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
220 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
221 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
222 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
223 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
225 #define MR_DCMD_CLUSTER 0x08000000
226 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
227 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
228 #define MR_DCMD_PD_LIST_QUERY 0x02010100
230 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
231 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
232 #define MR_DCMD_PD_GET_INFO 0x02020000
244 MFI_STAT_OK = 0x00,
245 MFI_STAT_INVALID_CMD = 0x01,
246 MFI_STAT_INVALID_DCMD = 0x02,
247 MFI_STAT_INVALID_PARAMETER = 0x03,
248 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
249 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
250 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
251 MFI_STAT_APP_IN_USE = 0x07,
252 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
253 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
254 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
255 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
256 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
257 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
258 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
259 MFI_STAT_FLASH_BUSY = 0x0f,
260 MFI_STAT_FLASH_ERROR = 0x10,
261 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
262 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
263 MFI_STAT_FLASH_NOT_OPEN = 0x13,
264 MFI_STAT_FLASH_NOT_STARTED = 0x14,
265 MFI_STAT_FLUSH_FAILED = 0x15,
266 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
267 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
268 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
269 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
270 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
271 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
272 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
273 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
274 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
275 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
276 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
277 MFI_STAT_MFC_HW_ERROR = 0x21,
278 MFI_STAT_NO_HW_PRESENT = 0x22,
279 MFI_STAT_NOT_FOUND = 0x23,
280 MFI_STAT_NOT_IN_ENCL = 0x24,
281 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
282 MFI_STAT_PD_TYPE_WRONG = 0x26,
283 MFI_STAT_PR_DISABLED = 0x27,
284 MFI_STAT_ROW_INDEX_INVALID = 0x28,
285 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
286 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
287 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
288 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
289 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
290 MFI_STAT_SCSI_IO_FAILED = 0x2e,
291 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
292 MFI_STAT_SHUTDOWN_FAILED = 0x30,
293 MFI_STAT_TIME_NOT_SET = 0x31,
294 MFI_STAT_WRONG_STATE = 0x32,
295 MFI_STAT_LD_OFFLINE = 0x33,
296 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
297 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
298 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
299 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
300 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
301 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
303 MFI_STAT_INVALID_STATUS = 0xFF
309 MFI_EVT_CLASS_INFO = 0,
323 UNAVAILABLE = 0,
331 MR_CRASH_BUF_TURN_OFF = 0,
344 MR_EVT_CLASS_INFO = 0,
354 MR_EVT_LOCALE_LD = 0x0001,
355 MR_EVT_LOCALE_PD = 0x0002,
356 MR_EVT_LOCALE_ENCL = 0x0004,
357 MR_EVT_LOCALE_BBU = 0x0008,
358 MR_EVT_LOCALE_SAS = 0x0010,
359 MR_EVT_LOCALE_CTRL = 0x0020,
360 MR_EVT_LOCALE_CONFIG = 0x0040,
361 MR_EVT_LOCALE_CLUSTER = 0x0080,
362 MR_EVT_LOCALE_ALL = 0xffff,
414 MR_PD_QUERY_TYPE_ALL = 0,
423 MR_LD_QUERY_TYPE_ALL = 0,
431 #define MR_EVT_CFG_CLEARED 0x0004
432 #define MR_EVT_LD_STATE_CHANGE 0x0051
433 #define MR_EVT_PD_INSERTED 0x005b
434 #define MR_EVT_PD_REMOVED 0x0070
435 #define MR_EVT_LD_CREATED 0x008a
436 #define MR_EVT_LD_DELETED 0x008b
437 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
438 #define MR_EVT_LD_OFFLINE 0x00fc
439 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
440 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
443 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
444 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
445 MR_PD_STATE_HOT_SPARE = 0x02,
446 MR_PD_STATE_OFFLINE = 0x10,
447 MR_PD_STATE_FAILED = 0x11,
448 MR_PD_STATE_REBUILD = 0x14,
449 MR_PD_STATE_ONLINE = 0x18,
450 MR_PD_STATE_COPYBACK = 0x20,
451 MR_PD_STATE_SYSTEM = 0x40,
1160 char package_version[0x60];
1299 u8 reserved5[2]; /*0x7CDh */
1326 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1328 u8 maxVFsSupported; /*0x7E4*/
1329 u8 numVFsEnabled; /*0x7E5*/
1330 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1331 u8 reserved; /*0x7E7*/
1456 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1531 #define OCR_DEBUG (1 << 0)
1535 #define SCAN_PD_CHANNEL 0x1
1536 #define SCAN_VD_CHANNEL 0x2
1543 READ_WRITE_LDIO = 0,
1550 INITIATE_OCR = 0,
1556 PROBE_CONTEXT = 0,
1561 #define IO_FRAME 0
1574 #define MEGASAS_IOCTL_CMD 0
1598 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1600 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1601 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1602 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1604 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1611 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1612 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1613 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1614 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1615 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1617 #define MFI_1068_PCSR_OFFSET 0x84
1618 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1619 #define MFI_1068_FW_READY 0xDDDD0000
1621 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1622 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1625 #define MR_RDPQ_MODE_OFFSET 0X00800000
1628 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1629 #define MR_MIN_MAP_SIZE 0x10000
1632 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1743 __le32 pad_0; /*0Ch */
1813 __le32 pad_0; /*0Ch */
1836 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1857 __le32 pad_0; /*0Ch */
1886 __le32 pad_0; /*0Ch */
1909 __le32 pad_0; /*0Ch */
1937 __le32 pad_0; /*0Ch */
1964 __le32 pad_0; /*0Ch */
1973 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1974 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1991 __le32 pad_0; /*0Ch */
2002 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
2003 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
2233 UNKNOWN_DRIVE = 0,
2250 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2258 MR_BALANCED_PERF_MODE = 0,
2489 #define IOV_111_OFFSET 0x7CE
2523 u32 driverCounter; /* Driver heart beat counter. 0x20 */
2526 u8 pad[0x400-0x40];
2530 MEGASAS_HBA_OPERATIONAL = 0,
2536 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
2563 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2566 (((sdev)->lun == 0) ? 1 : 0)
2668 FW_FAULT_OCR = 0,
2674 DCMD_SUCCESS = 0x00,
2675 DCMD_TIMEOUT = 0x01,
2676 DCMD_FAILED = 0x02,
2677 DCMD_BUSY = 0x03,
2678 DCMD_INIT = 0xff,