Lines Matching +full:0 +full:x00010007
23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define Fabric_Cntl_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
42 0 */
46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
96 #define FC4_FEATURE_TARGET 0x1
97 #define FC4_FEATURE_INIT 0x2
98 #define FC4_FEATURE_NVME_DISC 0x4
101 RFT_FCP_REG = (0x1 << 8),
105 RFT_NVME_REG = (0x1 << 8),
109 RFT_APP_SERV_REG = (0x1 << 0),
148 __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */
149 __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */
151 __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */
221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
222 #define SLI_CT_TIME_SERVICE 0xFB
223 #define SLI_CT_DIRECTORY_SERVICE 0xFC
224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
236 #define SLI_CT_RESPONSE_FS_RJT 0x8001
237 #define SLI_CT_RESPONSE_FS_ACC 0x8002
243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
244 #define SLI_CT_INVALID_COMMAND 0x01
245 #define SLI_CT_INVALID_VERSION 0x02
246 #define SLI_CT_LOGICAL_ERROR 0x03
247 #define SLI_CT_INVALID_IU_SIZE 0x04
248 #define SLI_CT_LOGICAL_BUSY 0x05
249 #define SLI_CT_PROTOCOL_ERROR 0x07
250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
259 #define SLI_CT_VENDOR_UNIQUE 0xff
265 #define SLI_CT_NO_PORT_ID 0x01
266 #define SLI_CT_NO_PORT_NAME 0x02
267 #define SLI_CT_NO_NODE_NAME 0x03
268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
269 #define SLI_CT_NO_IP_ADDRESS 0x05
270 #define SLI_CT_NO_IPA 0x06
271 #define SLI_CT_NO_FC4_TYPES 0x07
272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
274 #define SLI_CT_NO_PORT_TYPE 0x0A
275 #define SLI_CT_ACCESS_DENIED 0x10
276 #define SLI_CT_INVALID_PORT_ID 0x11
277 #define SLI_CT_DATABASE_EMPTY 0x12
278 #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40
284 #define SLI_CTNS_GA_NXT 0x0100
285 #define SLI_CTNS_GPN_ID 0x0112
286 #define SLI_CTNS_GNN_ID 0x0113
287 #define SLI_CTNS_GCS_ID 0x0114
288 #define SLI_CTNS_GFT_ID 0x0117
289 #define SLI_CTNS_GSPN_ID 0x0118
290 #define SLI_CTNS_GPT_ID 0x011A
291 #define SLI_CTNS_GFF_ID 0x011F
292 #define SLI_CTNS_GID_PN 0x0121
293 #define SLI_CTNS_GID_NN 0x0131
294 #define SLI_CTNS_GIP_NN 0x0135
295 #define SLI_CTNS_GIPA_NN 0x0136
296 #define SLI_CTNS_GSNN_NN 0x0139
297 #define SLI_CTNS_GNN_IP 0x0153
298 #define SLI_CTNS_GIPA_IP 0x0156
299 #define SLI_CTNS_GID_FT 0x0171
300 #define SLI_CTNS_GID_FF 0x01F1
301 #define SLI_CTNS_GID_PT 0x01A1
302 #define SLI_CTNS_RPN_ID 0x0212
303 #define SLI_CTNS_RNN_ID 0x0213
304 #define SLI_CTNS_RCS_ID 0x0214
305 #define SLI_CTNS_RFT_ID 0x0217
306 #define SLI_CTNS_RSPN_ID 0x0218
307 #define SLI_CTNS_RPT_ID 0x021A
308 #define SLI_CTNS_RFF_ID 0x021F
309 #define SLI_CTNS_RIP_NN 0x0235
310 #define SLI_CTNS_RIPA_NN 0x0236
311 #define SLI_CTNS_RSNN_NN 0x0239
312 #define SLI_CTNS_DA_ID 0x0300
318 #define SLI_CTPT_N_PORT 0x01
319 #define SLI_CTPT_NL_PORT 0x02
320 #define SLI_CTPT_FNL_PORT 0x03
321 #define SLI_CTPT_IP 0x04
322 #define SLI_CTPT_FCP 0x08
323 #define SLI_CTPT_NVME 0x28
324 #define SLI_CTPT_NX_PORT 0x7F
325 #define SLI_CTPT_F_PORT 0x81
326 #define SLI_CTPT_FL_PORT 0x82
327 #define SLI_CTPT_E_PORT 0x84
329 #define SLI_CT_LAST_ENTRY 0x80000000
340 #define FC_PH3 0x20 /* FC-PH-3 version */
348 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
349 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
352 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
354 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
357 #define NAME_IEEE 0x1 /* IEEE name - nameType */
358 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
359 #define NAME_FC_TYPE 0x3 /* FC native name type */
360 #define NAME_IP_TYPE 0x4 /* IP address */
361 #define NAME_CCITT_TYPE 0xC
362 #define NAME_CCITT_GR_TYPE 0xE
363 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
373 uint8_t fcphHigh; /* FC Word 0, byte 0 */
376 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
434 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
449 uint8_t classValid:1; /* FC Word 0, bit 31 */
450 uint8_t intermix:1; /* FC Word 0, bit 30 */
451 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
452 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
453 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
456 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
457 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
458 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
459 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
460 uint8_t intermix:1; /* FC Word 0, bit 30 */
461 uint8_t classValid:1; /* FC Word 0, bit 31 */
465 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
468 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
469 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
470 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
471 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
474 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
475 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
476 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
477 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
478 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
481 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
501 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
506 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
511 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
526 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
539 #define fc_vft_hdr_r_ctl_MASK 0xFF
542 #define fc_vft_hdr_ver_MASK 0x3
545 #define fc_vft_hdr_type_MASK 0xF
548 #define fc_vft_hdr_e_MASK 0x1
551 #define fc_vft_hdr_priority_MASK 0x7
554 #define fc_vft_hdr_vf_id_MASK 0xFFF
558 #define fc_vft_hdr_hopct_MASK 0xFF
570 #define LOOPBACK_SRC_APPID 0x4321
586 * Extended Link Service LS_COMMAND codes (Payload Word 0)
589 #define ELS_CMD_MASK 0xffff0000
590 #define ELS_RSP_MASK 0xff000000
591 #define ELS_CMD_LS_RJT 0x01000000
592 #define ELS_CMD_ACC 0x02000000
593 #define ELS_CMD_PLOGI 0x03000000
594 #define ELS_CMD_FLOGI 0x04000000
595 #define ELS_CMD_LOGO 0x05000000
596 #define ELS_CMD_ABTX 0x06000000
597 #define ELS_CMD_RCS 0x07000000
598 #define ELS_CMD_RES 0x08000000
599 #define ELS_CMD_RSS 0x09000000
600 #define ELS_CMD_RSI 0x0A000000
601 #define ELS_CMD_ESTS 0x0B000000
602 #define ELS_CMD_ESTC 0x0C000000
603 #define ELS_CMD_ADVC 0x0D000000
604 #define ELS_CMD_RTV 0x0E000000
605 #define ELS_CMD_RLS 0x0F000000
606 #define ELS_CMD_ECHO 0x10000000
607 #define ELS_CMD_TEST 0x11000000
608 #define ELS_CMD_RRQ 0x12000000
609 #define ELS_CMD_REC 0x13000000
610 #define ELS_CMD_RDP 0x18000000
611 #define ELS_CMD_RDF 0x19000000
612 #define ELS_CMD_PRLI 0x20100014
613 #define ELS_CMD_NVMEPRLI 0x20140018
614 #define ELS_CMD_PRLO 0x21100014
615 #define ELS_CMD_PRLO_ACC 0x02100014
616 #define ELS_CMD_PDISC 0x50000000
617 #define ELS_CMD_FDISC 0x51000000
618 #define ELS_CMD_ADISC 0x52000000
619 #define ELS_CMD_FARP 0x54000000
620 #define ELS_CMD_FARPR 0x55000000
621 #define ELS_CMD_RPL 0x57000000
622 #define ELS_CMD_FAN 0x60000000
623 #define ELS_CMD_RSCN 0x61040000
624 #define ELS_CMD_RSCN_XMT 0x61040008
625 #define ELS_CMD_SCR 0x62000000
626 #define ELS_CMD_RNID 0x78000000
627 #define ELS_CMD_LIRR 0x7A000000
628 #define ELS_CMD_LCB 0x81000000
629 #define ELS_CMD_FPIN 0x16000000
630 #define ELS_CMD_EDC 0x17000000
631 #define ELS_CMD_QFPA 0xB0000000
632 #define ELS_CMD_UVEM 0xB1000000
634 #define ELS_CMD_MASK 0xffff
635 #define ELS_RSP_MASK 0xff
636 #define ELS_CMD_LS_RJT 0x01
637 #define ELS_CMD_ACC 0x02
638 #define ELS_CMD_PLOGI 0x03
639 #define ELS_CMD_FLOGI 0x04
640 #define ELS_CMD_LOGO 0x05
641 #define ELS_CMD_ABTX 0x06
642 #define ELS_CMD_RCS 0x07
643 #define ELS_CMD_RES 0x08
644 #define ELS_CMD_RSS 0x09
645 #define ELS_CMD_RSI 0x0A
646 #define ELS_CMD_ESTS 0x0B
647 #define ELS_CMD_ESTC 0x0C
648 #define ELS_CMD_ADVC 0x0D
649 #define ELS_CMD_RTV 0x0E
650 #define ELS_CMD_RLS 0x0F
651 #define ELS_CMD_ECHO 0x10
652 #define ELS_CMD_TEST 0x11
653 #define ELS_CMD_RRQ 0x12
654 #define ELS_CMD_REC 0x13
655 #define ELS_CMD_RDP 0x18
656 #define ELS_CMD_RDF 0x19
657 #define ELS_CMD_PRLI 0x14001020
658 #define ELS_CMD_NVMEPRLI 0x18001420
659 #define ELS_CMD_PRLO 0x14001021
660 #define ELS_CMD_PRLO_ACC 0x14001002
661 #define ELS_CMD_PDISC 0x50
662 #define ELS_CMD_FDISC 0x51
663 #define ELS_CMD_ADISC 0x52
664 #define ELS_CMD_FARP 0x54
665 #define ELS_CMD_FARPR 0x55
666 #define ELS_CMD_RPL 0x57
667 #define ELS_CMD_FAN 0x60
668 #define ELS_CMD_RSCN 0x0461
669 #define ELS_CMD_RSCN_XMT 0x08000461
670 #define ELS_CMD_SCR 0x62
671 #define ELS_CMD_RNID 0x78
672 #define ELS_CMD_LIRR 0x7A
673 #define ELS_CMD_LCB 0x81
676 #define ELS_CMD_QFPA 0xB0
677 #define ELS_CMD_UVEM 0xB1
689 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
691 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
693 #define LSRJT_INVALID_CMD 0x01
694 #define LSRJT_LOGICAL_ERR 0x03
695 #define LSRJT_LOGICAL_BSY 0x05
696 #define LSRJT_PROTOCOL_ERR 0x07
697 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
698 #define LSRJT_CMD_UNSUPPORTED 0x0B
699 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
701 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
703 #define LSEXP_NOTHING_MORE 0x00
704 #define LSEXP_SPARM_OPTIONS 0x01
705 #define LSEXP_SPARM_ICTL 0x03
706 #define LSEXP_SPARM_RCTL 0x05
707 #define LSEXP_SPARM_RCV_SIZE 0x07
708 #define LSEXP_SPARM_CONCUR_SEQ 0x09
709 #define LSEXP_SPARM_CREDIT 0x0B
710 #define LSEXP_INVALID_PNAME 0x0D
711 #define LSEXP_INVALID_NNAME 0x0E
712 #define LSEXP_INVALID_CSP 0x0F
713 #define LSEXP_INVALID_ASSOC_HDR 0x11
714 #define LSEXP_ASSOC_HDR_REQ 0x13
715 #define LSEXP_INVALID_O_SID 0x15
716 #define LSEXP_INVALID_OX_RX 0x17
717 #define LSEXP_CMD_IN_PROGRESS 0x19
718 #define LSEXP_PORT_LOGIN_REQ 0x1E
719 #define LSEXP_INVALID_NPORT_ID 0x1F
720 #define LSEXP_INVALID_SEQ_ID 0x21
721 #define LSEXP_INVALID_XCHG 0x23
722 #define LSEXP_INACTIVE_XCHG 0x25
723 #define LSEXP_RQ_REQUIRED 0x27
724 #define LSEXP_OUT_OF_RESOURCE 0x29
725 #define LSEXP_CANT_GIVE_DATA 0x2A
726 #define LSEXP_REQ_UNSUPPORTED 0x2C
727 #define LSEXP_AUTH_REQ 0x48
728 #define LSEXP_NO_RSRC_ASSIGN 0x52
729 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
745 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
755 #define PRLX_PAGE_LEN 0x10
756 #define TPRLO_PAGE_LEN 0x14
759 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
761 #define PRLI_FCP_TYPE 0x08
762 #define PRLI_NVME_TYPE 0x28
763 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
766 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
767 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
768 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
771 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
772 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
774 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
775 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
776 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
777 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
778 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
782 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
783 #define PRLI_NO_RESOURCES 0x2
784 #define PRLI_INIT_INCOMPLETE 0x3
785 #define PRLI_NO_SUCH_PA 0x4
786 #define PRLI_PREDEF_CONFIG 0x5
787 #define PRLI_PARTIAL_SUCCESS 0x6
788 #define PRLI_INVALID_PAGE_CNT 0x7
789 #define PRLI_INV_SRV_PARM 0x8
791 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
793 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
795 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
816 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
826 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
842 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
844 #define PRLO_FCP_TYPE 0x08
845 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
848 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
849 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
850 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
851 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
853 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
854 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
855 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
856 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
859 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
860 #define PRLO_NO_SUCH_IMAGE 0x4
861 #define PRLO_INVALID_PAGE_CNT 0x7
863 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
865 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
867 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
869 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
882 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
884 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
885 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
886 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
887 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
889 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
893 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
894 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
914 #define SCR_FUNC_FABRIC 0x01
915 #define SCR_FUNC_NPORT 0x02
916 #define SCR_FUNC_FULL 0x03
917 #define SCR_CLEAR 0xff
924 #define RNID_HBA 0x7
925 #define RNID_HOST 0xa
926 #define RNID_DRIVER 0xd
930 #define RNID_IPV4 0x1
931 #define RNID_IPV6 0x2
936 #define RNID_TD_SUPPORT 0x1
937 #define RNID_LP_VALID 0x2
942 #define RNID_TOPOLOGY_DISC 0xdf
949 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
956 #define rls_rsvd_MASK 0x000000ff
958 #define rls_did_SHIFT 0
959 #define rls_did_MASK 0x00ffffff
975 #define rrq_rsvd_MASK 0x000000ff
977 #define rrq_did_SHIFT 0
978 #define rrq_did_MASK 0x00ffffff
982 #define rrq_oxid_MASK 0xffff
984 #define rrq_rxid_SHIFT 0
985 #define rrq_rxid_MASK 0xffff
990 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
997 #define qtov_rsvd0_MASK 0x0000000f
1000 #define qtov_edtovres_MASK 0x00000001
1003 #define qtov_rsvd1_MASK 0x0000003f
1006 #define qtov_rttov_MASK 0x00000001
1008 #define qtov_rsvd2_SHIFT 0
1009 #define qtov_rsvd2_MASK 0x0003ffff
1051 #define RSCN_ADDRESS_FORMAT_PORT 0x0
1052 #define RSCN_ADDRESS_FORMAT_AREA 0x1
1053 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1054 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1055 #define RSCN_ADDRESS_FORMAT_MASK 0x3
1062 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1086 uint32_t lcb_command; /* ELS command opcode (0x81) */
1088 #define LPFC_LCB_ON 0x1
1089 #define LPFC_LCB_OFF 0x2
1091 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1093 #define LPFC_LCB_GREEN 0x1
1094 #define LPFC_LCB_AMBER 0x2
1098 #define BEACON_VERSION_V0 0
1099 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1106 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1109 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1112 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1118 #define SFF_PG0_IDENT_SFP 0x3
1120 #define SFP_FLAG_PT_OPTICAL 0x0
1121 #define SFP_FLAG_PT_SWLASER 0x01
1122 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1123 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1124 #define SFP_FLAG_PT_MASK 0x0F
1125 #define SFP_FLAG_PT_SHIFT 0
1127 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1128 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1131 #define SFP_FLAG_IS_DESC_VALID 0x01
1132 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1135 #define SFP_FLAG_CT_UNKNOWN 0x0
1136 #define SFP_FLAG_CT_SFP_PLUS 0x01
1137 #define SFP_FLAG_CT_MASK 0x3C
1160 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1173 #define RDP_FEC_DESC_TAG 0x00010005
1185 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1192 #define VN_PT_PHY_UNKNOWN 0x00
1193 #define VN_PT_PHY_PF_PORT 0x01
1194 #define VN_PT_PHY_ETH_MAC 0x10
1197 #define RDP_PS_1GB 0x8000
1198 #define RDP_PS_2GB 0x4000
1199 #define RDP_PS_4GB 0x2000
1200 #define RDP_PS_10GB 0x1000
1201 #define RDP_PS_8GB 0x0800
1202 #define RDP_PS_16GB 0x0400
1203 #define RDP_PS_32GB 0x0200
1204 #define RDP_PS_64GB 0x0100
1205 #define RDP_PS_128GB 0x0080
1206 #define RDP_PS_256GB 0x0040
1208 #define RDP_CAP_USER_CONFIGURED 0x0002
1209 #define RDP_CAP_UNKNOWN 0x0001
1210 #define RDP_PS_UNKNOWN 0x0002
1211 #define RDP_PS_NOT_ESTABLISHED 0x0001
1222 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1230 #define RDP_N_PORT_DESC_TAG 0x00000003
1240 uint32_t els_req; /* Request payload word 0 value.*/
1243 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1248 /* must be ELS req Word 0(0x18) */
1260 #define RDP_SFP_DESC_TAG 0x00010000
1273 #define RDP_BBC_DESC_TAG 0x00010006
1281 #define RDP_OET_LOW_WARNING 0x1
1282 #define RDP_OET_HIGH_WARNING 0x2
1283 #define RDP_OET_LOW_ALARM 0x4
1284 #define RDP_OET_HIGH_ALARM 0x8
1286 #define RDP_OED_TEMPERATURE 0x1
1287 #define RDP_OED_VOLTAGE 0x2
1288 #define RDP_OED_TXBIAS 0x3
1289 #define RDP_OED_TXPOWER 0x4
1290 #define RDP_OED_RXPOWER 0x5
1301 #define RDP_OED_DESC_TAG 0x00010007
1317 #define RDP_OPD_DESC_TAG 0x00010008
1325 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1357 #define VEM_ID_DESC_TAG 0x0001000A
1366 #define INSTANTIATED_VE_DESC_TAG 0x0001000B
1372 #define lpfc_instantiated_local_id_SHIFT 0
1373 #define lpfc_instantiated_local_id_MASK 0x000000ff
1376 #define lpfc_instantiated_nport_id_MASK 0x00ffffff
1380 #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C
1386 #define lpfc_deinstantiated_nport_id_SHIFT 0
1387 #define lpfc_deinstantiated_nport_id_MASK 0x000000ff
1390 #define lpfc_deinstantiated_local_id_MASK 0x00ffffff
1415 #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */
1417 #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */
1418 #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */
1419 #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */
1421 #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */
1423 #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */
1424 #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */
1426 #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */
1450 #define GALLAPPIA_ID_LAST 0x80
1465 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1552 #define SLI_CT_MIB_Subtypes 0x11
1573 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1574 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1575 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1576 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1577 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1578 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1579 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1580 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1581 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1582 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1583 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1584 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1585 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1592 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1593 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1594 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1595 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1596 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1597 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1598 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1599 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1600 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1601 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1602 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1603 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1604 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1605 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1606 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1607 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1608 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1609 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1612 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1613 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1614 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1615 #define LPFC_FDMI_HBA_ATTR_model 0x00000008
1616 #define LPFC_FDMI_HBA_ATTR_description 0x00000010
1617 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1618 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1619 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1620 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1621 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1622 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1623 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1624 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1625 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1626 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1627 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1628 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1629 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1632 #define LPFC_FDMI1_HBA_ATTR 0x000007ff
1636 #define LPFC_FDMI2_HBA_ATTR 0x0002efff
1641 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1642 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1643 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1644 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1645 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1646 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1647 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1648 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1649 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1650 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1651 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1652 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1653 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1654 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1655 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1656 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1657 #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */
1658 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1659 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1660 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1661 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1662 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1663 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1664 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1667 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1668 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1669 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1670 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1671 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1672 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1673 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1674 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1675 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1676 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1677 #define LPFC_FDMI_PORT_ATTR_class 0x00000400
1678 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1679 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1680 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1681 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1682 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1683 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1684 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1685 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1686 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1687 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1688 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1689 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1690 #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */
1693 #define LPFC_FDMI1_PORT_ATTR 0x0000003f
1696 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1699 #define LPFC_FDMI2_SMART_ATTR 0x007fffff
1706 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1713 * BAR0, offset 0x10 - SLIM base memory address
1714 * BAR1, offset 0x14 - SLIM base memory high address
1715 * BAR2, offset 0x18 - REGISTER base memory address
1716 * BAR3, offset 0x1c - REGISTER base memory high address
1717 * BAR4, offset 0x20 - BIU I/O registers
1718 * BAR5, offset 0x24 - REGISTER base io high address
1729 #define OWN_HOST 0
1735 #define FC_NET_HDR 0x20
1738 #define PCI_VENDOR_ID_EMULEX 0x10df
1739 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1740 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1741 #define PCI_DEVICE_ID_BALIUS 0xe131
1742 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1743 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1744 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1745 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1746 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1747 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1748 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1749 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500
1750 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1751 #define PCI_DEVICE_ID_SAT_MID 0xf015
1752 #define PCI_DEVICE_ID_RFLY 0xf095
1753 #define PCI_DEVICE_ID_PFLY 0xf098
1754 #define PCI_DEVICE_ID_LP101 0xf0a1
1755 #define PCI_DEVICE_ID_TFLY 0xf0a5
1756 #define PCI_DEVICE_ID_BSMB 0xf0d1
1757 #define PCI_DEVICE_ID_BMID 0xf0d5
1758 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1759 #define PCI_DEVICE_ID_ZMID 0xf0e5
1760 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1761 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1762 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1763 #define PCI_DEVICE_ID_SAT 0xf100
1764 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1765 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1766 #define PCI_DEVICE_ID_FALCON 0xf180
1767 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1768 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1769 #define PCI_DEVICE_ID_CENTAUR 0xf900
1770 #define PCI_DEVICE_ID_PEGASUS 0xf980
1771 #define PCI_DEVICE_ID_THOR 0xfa00
1772 #define PCI_DEVICE_ID_VIPER 0xfb00
1773 #define PCI_DEVICE_ID_LP10000S 0xfc00
1774 #define PCI_DEVICE_ID_LP11000S 0xfc10
1775 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1776 #define PCI_DEVICE_ID_SAT_S 0xfc40
1777 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1778 #define PCI_DEVICE_ID_HELIOS 0xfd00
1779 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1780 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1781 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1782 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1783 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1784 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1785 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1786 #define PCI_DEVICE_ID_TOMCAT 0x0714
1787 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1788 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1789 #define PCI_VENDOR_ID_ATTO 0x117c
1790 #define PCI_DEVICE_ID_CLRY_16XE 0x0064
1791 #define PCI_DEVICE_ID_CLRY_161E 0x0063
1792 #define PCI_DEVICE_ID_CLRY_162E 0x0064
1793 #define PCI_DEVICE_ID_CLRY_164E 0x0065
1794 #define PCI_DEVICE_ID_CLRY_16XP 0x0094
1795 #define PCI_DEVICE_ID_CLRY_161P 0x00a0
1796 #define PCI_DEVICE_ID_CLRY_162P 0x0094
1797 #define PCI_DEVICE_ID_CLRY_164P 0x00a1
1798 #define PCI_DEVICE_ID_CLRY_32XE 0x0094
1799 #define PCI_DEVICE_ID_CLRY_321E 0x00a2
1800 #define PCI_DEVICE_ID_CLRY_322E 0x00a3
1801 #define PCI_DEVICE_ID_CLRY_324E 0x00ac
1802 #define PCI_DEVICE_ID_CLRY_32XP 0x00bb
1803 #define PCI_DEVICE_ID_CLRY_321P 0x00bc
1804 #define PCI_DEVICE_ID_CLRY_322P 0x00bd
1805 #define PCI_DEVICE_ID_CLRY_324P 0x00be
1806 #define PCI_DEVICE_ID_TLFC_2 0x0064
1807 #define PCI_DEVICE_ID_TLFC_2XX2 0x4064
1808 #define PCI_DEVICE_ID_TLFC_3 0x0094
1809 #define PCI_DEVICE_ID_TLFC_3162 0x40a6
1810 #define PCI_DEVICE_ID_TLFC_3322 0x40a7
1812 #define JEDEC_ID_ADDRESS 0x0080001c
1813 #define FIREFLY_JEDEC_ID 0x1ACC
1814 #define SUPERFLY_JEDEC_ID 0x0020
1815 #define DRAGONFLY_JEDEC_ID 0x0021
1816 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1817 #define CENTAUR_2G_JEDEC_ID 0x0026
1818 #define CENTAUR_1G_JEDEC_ID 0x0028
1819 #define PEGASUS_ORION_JEDEC_ID 0x0036
1820 #define PEGASUS_JEDEC_ID 0x0038
1821 #define THOR_JEDEC_ID 0x0012
1822 #define HELIOS_JEDEC_ID 0x0364
1823 #define ZEPHYR_JEDEC_ID 0x0577
1824 #define VIPER_JEDEC_ID 0x4838
1825 #define SATURN_JEDEC_ID 0x1004
1827 #define JEDEC_ID_MASK 0x0FFFF000
1847 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1849 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1850 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1851 #define HA_R0ATT 0x00000008 /* Bit 3 */
1852 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1853 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1854 #define HA_R1ATT 0x00000080 /* Bit 7 */
1855 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1856 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1857 #define HA_R2ATT 0x00000800 /* Bit 11 */
1858 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1859 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1860 #define HA_R3ATT 0x00008000 /* Bit 15 */
1861 #define HA_LATT 0x20000000 /* Bit 29 */
1862 #define HA_MBATT 0x40000000 /* Bit 30 */
1863 #define HA_ERATT 0x80000000 /* Bit 31 */
1865 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1866 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1867 #define HA_RXATT 0x00000008 /* Bit 3 */
1868 #define HA_RXMASK 0x0000000f
1886 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1887 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1888 #define CA_R0ATT 0x00000008 /* Bit 3 */
1889 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1890 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1891 #define CA_R1ATT 0x00000080 /* Bit 7 */
1892 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1893 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1894 #define CA_R2ATT 0x00000800 /* Bit 11 */
1895 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1896 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1897 #define CA_R3ATT 0x00008000 /* Bit 15 */
1898 #define CA_MBATT 0x40000000 /* Bit 30 */
1904 #define HS_MBRDY 0x00400000 /* Bit 22 */
1905 #define HS_FFRDY 0x00800000 /* Bit 23 */
1906 #define HS_FFER8 0x01000000 /* Bit 24 */
1907 #define HS_FFER7 0x02000000 /* Bit 25 */
1908 #define HS_FFER6 0x04000000 /* Bit 26 */
1909 #define HS_FFER5 0x08000000 /* Bit 27 */
1910 #define HS_FFER4 0x10000000 /* Bit 28 */
1911 #define HS_FFER3 0x20000000 /* Bit 29 */
1912 #define HS_FFER2 0x40000000 /* Bit 30 */
1913 #define HS_FFER1 0x80000000 /* Bit 31 */
1914 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1915 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1916 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1921 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1922 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1923 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1924 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1925 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1926 #define HC_INITHBI 0x02000000 /* Bit 25 */
1927 #define HC_INITMB 0x04000000 /* Bit 26 */
1928 #define HC_INITFF 0x08000000 /* Bit 27 */
1929 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1930 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1933 #define MSIX_DFLT_ID 0
1934 #define MSIX_RNG0_ID 0
1946 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1947 #define MBX_LOAD_SM 0x01
1948 #define MBX_READ_NV 0x02
1949 #define MBX_WRITE_NV 0x03
1950 #define MBX_RUN_BIU_DIAG 0x04
1951 #define MBX_INIT_LINK 0x05
1952 #define MBX_DOWN_LINK 0x06
1953 #define MBX_CONFIG_LINK 0x07
1954 #define MBX_CONFIG_RING 0x09
1955 #define MBX_RESET_RING 0x0A
1956 #define MBX_READ_CONFIG 0x0B
1957 #define MBX_READ_RCONFIG 0x0C
1958 #define MBX_READ_SPARM 0x0D
1959 #define MBX_READ_STATUS 0x0E
1960 #define MBX_READ_RPI 0x0F
1961 #define MBX_READ_XRI 0x10
1962 #define MBX_READ_REV 0x11
1963 #define MBX_READ_LNK_STAT 0x12
1964 #define MBX_REG_LOGIN 0x13
1965 #define MBX_UNREG_LOGIN 0x14
1966 #define MBX_CLEAR_LA 0x16
1967 #define MBX_DUMP_MEMORY 0x17
1968 #define MBX_DUMP_CONTEXT 0x18
1969 #define MBX_RUN_DIAGS 0x19
1970 #define MBX_RESTART 0x1A
1971 #define MBX_UPDATE_CFG 0x1B
1972 #define MBX_DOWN_LOAD 0x1C
1973 #define MBX_DEL_LD_ENTRY 0x1D
1974 #define MBX_RUN_PROGRAM 0x1E
1975 #define MBX_SET_MASK 0x20
1976 #define MBX_SET_VARIABLE 0x21
1977 #define MBX_UNREG_D_ID 0x23
1978 #define MBX_KILL_BOARD 0x24
1979 #define MBX_CONFIG_FARP 0x25
1980 #define MBX_BEACON 0x2A
1981 #define MBX_CONFIG_MSI 0x30
1982 #define MBX_HEARTBEAT 0x31
1983 #define MBX_WRITE_VPARMS 0x32
1984 #define MBX_ASYNCEVT_ENABLE 0x33
1985 #define MBX_READ_EVENT_LOG_STATUS 0x37
1986 #define MBX_READ_EVENT_LOG 0x38
1987 #define MBX_WRITE_EVENT_LOG 0x39
1989 #define MBX_PORT_CAPABILITIES 0x3B
1990 #define MBX_PORT_IOV_CONTROL 0x3C
1992 #define MBX_CONFIG_HBQ 0x7C
1993 #define MBX_LOAD_AREA 0x81
1994 #define MBX_RUN_BIU_DIAG64 0x84
1995 #define MBX_CONFIG_PORT 0x88
1996 #define MBX_READ_SPARM64 0x8D
1997 #define MBX_READ_RPI64 0x8F
1998 #define MBX_REG_LOGIN64 0x93
1999 #define MBX_READ_TOPOLOGY 0x95
2000 #define MBX_REG_VPI 0x96
2001 #define MBX_UNREG_VPI 0x97
2003 #define MBX_WRITE_WWN 0x98
2004 #define MBX_SET_DEBUG 0x99
2005 #define MBX_LOAD_EXP_ROM 0x9C
2006 #define MBX_SLI4_CONFIG 0x9B
2007 #define MBX_SLI4_REQ_FTRS 0x9D
2008 #define MBX_MAX_CMDS 0x9E
2009 #define MBX_RESUME_RPI 0x9E
2010 #define MBX_SLI2_CMD_MASK 0x80
2011 #define MBX_REG_VFI 0x9F
2012 #define MBX_REG_FCFI 0xA0
2013 #define MBX_UNREG_VFI 0xA1
2014 #define MBX_UNREG_FCFI 0xA2
2015 #define MBX_INIT_VFI 0xA3
2016 #define MBX_INIT_VPI 0xA4
2017 #define MBX_ACCESS_VDATA 0xA5
2018 #define MBX_REG_FCFI_MRQ 0xAF
2020 #define MBX_AUTH_PORT 0xF8
2021 #define MBX_SECURITY_MGMT 0xF9
2025 #define CMD_RCV_SEQUENCE_CX 0x01
2026 #define CMD_XMIT_SEQUENCE_CR 0x02
2027 #define CMD_XMIT_SEQUENCE_CX 0x03
2028 #define CMD_XMIT_BCAST_CN 0x04
2029 #define CMD_XMIT_BCAST_CX 0x05
2030 #define CMD_QUE_RING_BUF_CN 0x06
2031 #define CMD_QUE_XRI_BUF_CX 0x07
2032 #define CMD_IOCB_CONTINUE_CN 0x08
2033 #define CMD_RET_XRI_BUF_CX 0x09
2034 #define CMD_ELS_REQUEST_CR 0x0A
2035 #define CMD_ELS_REQUEST_CX 0x0B
2036 #define CMD_RCV_ELS_REQ_CX 0x0D
2037 #define CMD_ABORT_XRI_CN 0x0E
2038 #define CMD_ABORT_XRI_CX 0x0F
2039 #define CMD_CLOSE_XRI_CN 0x10
2040 #define CMD_CLOSE_XRI_CX 0x11
2041 #define CMD_CREATE_XRI_CR 0x12
2042 #define CMD_CREATE_XRI_CX 0x13
2043 #define CMD_GET_RPI_CN 0x14
2044 #define CMD_XMIT_ELS_RSP_CX 0x15
2045 #define CMD_GET_RPI_CR 0x16
2046 #define CMD_XRI_ABORTED_CX 0x17
2047 #define CMD_FCP_IWRITE_CR 0x18
2048 #define CMD_FCP_IWRITE_CX 0x19
2049 #define CMD_FCP_IREAD_CR 0x1A
2050 #define CMD_FCP_IREAD_CX 0x1B
2051 #define CMD_FCP_ICMND_CR 0x1C
2052 #define CMD_FCP_ICMND_CX 0x1D
2053 #define CMD_FCP_TSEND_CX 0x1F
2054 #define CMD_FCP_TRECEIVE_CX 0x21
2055 #define CMD_FCP_TRSP_CX 0x23
2056 #define CMD_FCP_AUTO_TRSP_CX 0x29
2058 #define CMD_ADAPTER_MSG 0x20
2059 #define CMD_ADAPTER_DUMP 0x22
2063 #define CMD_ASYNC_STATUS 0x7C
2064 #define CMD_RCV_SEQUENCE64_CX 0x81
2065 #define CMD_XMIT_SEQUENCE64_CR 0x82
2066 #define CMD_XMIT_SEQUENCE64_CX 0x83
2067 #define CMD_XMIT_BCAST64_CN 0x84
2068 #define CMD_XMIT_BCAST64_CX 0x85
2069 #define CMD_QUE_RING_BUF64_CN 0x86
2070 #define CMD_QUE_XRI_BUF64_CX 0x87
2071 #define CMD_IOCB_CONTINUE64_CN 0x88
2072 #define CMD_RET_XRI_BUF64_CX 0x89
2073 #define CMD_ELS_REQUEST64_CR 0x8A
2074 #define CMD_ELS_REQUEST64_CX 0x8B
2075 #define CMD_ABORT_MXRI64_CN 0x8C
2076 #define CMD_RCV_ELS_REQ64_CX 0x8D
2077 #define CMD_XMIT_ELS_RSP64_CX 0x95
2078 #define CMD_XMIT_BLS_RSP64_CX 0x97
2079 #define CMD_FCP_IWRITE64_CR 0x98
2080 #define CMD_FCP_IWRITE64_CX 0x99
2081 #define CMD_FCP_IREAD64_CR 0x9A
2082 #define CMD_FCP_IREAD64_CX 0x9B
2083 #define CMD_FCP_ICMND64_CR 0x9C
2084 #define CMD_FCP_ICMND64_CX 0x9D
2085 #define CMD_FCP_TSEND64_CX 0x9F
2086 #define CMD_FCP_TRECEIVE64_CX 0xA1
2087 #define CMD_FCP_TRSP64_CX 0xA3
2089 #define CMD_QUE_XRI64_CX 0xB3
2090 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
2091 #define CMD_IOCB_RCV_ELS64_CX 0xB7
2092 #define CMD_IOCB_RET_XRI64_CX 0xB9
2093 #define CMD_IOCB_RCV_CONT64_CX 0xBB
2095 #define CMD_GEN_REQUEST64_CR 0xC2
2096 #define CMD_GEN_REQUEST64_CX 0xC3
2099 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
2100 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
2101 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
2102 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
2103 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
2104 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
2105 #define CMD_IOCB_RET_HBQE64_CN 0xCA
2106 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
2107 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
2108 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
2109 #define CMD_IOCB_LOGENTRY_CN 0x94
2110 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
2113 #define DSSCMD_IWRITE64_CR 0xF8
2114 #define DSSCMD_IWRITE64_CX 0xF9
2115 #define DSSCMD_IREAD64_CR 0xFA
2116 #define DSSCMD_IREAD64_CX 0xFB
2118 #define CMD_MAX_IOCB_CMD 0xFB
2119 #define CMD_IOCB_MASK 0xff
2127 #define MBX_SUCCESS 0
2144 #define MBXERR_LINK_DOWN 0x33
2145 #define MBXERR_SEC_NO_PERMISSION 0xF02
2148 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
2149 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
2151 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
2198 uint32_t addrLow; /* Address 0:31 */
2208 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2215 #define LPFC_PDE5_DESCRIPTOR 0x85
2216 #define LPFC_PDE6_DESCRIPTOR 0x86
2217 #define LPFC_PDE7_DESCRIPTOR 0x87
2220 #define BG_OP_IN_NODIF_OUT_CRC 0x0
2221 #define BG_OP_IN_CRC_OUT_NODIF 0x1
2222 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
2223 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
2224 #define BG_OP_IN_CRC_OUT_CRC 0x4
2225 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
2226 #define BG_OP_IN_CRC_OUT_CSUM 0x6
2227 #define BG_OP_IN_CSUM_OUT_CRC 0x7
2228 #define BG_OP_RAW_MODE 0x8
2233 #define pde5_type_MASK 0x000000ff
2235 #define pde5_rsvd0_SHIFT 0
2236 #define pde5_rsvd0_MASK 0x00ffffff
2245 #define pde6_type_MASK 0x000000ff
2247 #define pde6_rsvd0_SHIFT 0
2248 #define pde6_rsvd0_MASK 0x00ffffff
2252 #define pde6_rsvd1_MASK 0x0000003f
2255 #define pde6_na_MASK 0x00000001
2258 #define pde6_rsvd2_MASK 0x000001FF
2260 #define pde6_apptagtr_SHIFT 0
2261 #define pde6_apptagtr_MASK 0x0000ffff
2265 #define pde6_optx_MASK 0x0000000f
2268 #define pde6_oprx_MASK 0x0000000f
2271 #define pde6_nr_MASK 0x00000001
2274 #define pde6_ce_MASK 0x00000001
2277 #define pde6_re_MASK 0x00000001
2280 #define pde6_ae_MASK 0x00000001
2283 #define pde6_ai_MASK 0x00000001
2286 #define pde6_bs_MASK 0x00000007
2288 #define pde6_apptagval_SHIFT 0
2289 #define pde6_apptagval_MASK 0x0000ffff
2296 #define pde7_type_MASK 0x000000ff
2298 #define pde7_rsvd0_SHIFT 0
2299 #define pde7_rsvd0_MASK 0x00ffffff
2378 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2394 /* Structure for MB command READ_EVENT_LOG (0x38) */
2398 #define lpfc_event_log_MASK 0x00000001
2426 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2427 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2428 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2429 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2430 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2431 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2432 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2434 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2435 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2436 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2439 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2440 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2441 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2442 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2443 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2444 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2445 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2446 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2447 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
2448 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
2449 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
2626 #define LMT_RESERVED 0x000 /* Not used */
2627 #define LMT_1Gb 0x004
2628 #define LMT_2Gb 0x008
2629 #define LMT_4Gb 0x040
2630 #define LMT_8Gb 0x080
2631 #define LMT_10Gb 0x100
2632 #define LMT_16Gb 0x200
2633 #define LMT_32Gb 0x400
2634 #define LMT_64Gb 0x800
2635 #define LMT_128Gb 0x1000
2636 #define LMT_256Gb 0x2000
2702 /* Structure for MB Command READ_SPARM64 (0x8D) */
2723 RD_ST_CC = 0x01,
2724 RD_ST_XKB = 0x80,
2728 RD_ST_XMIT_XKB_MASK = 0x3fffff,
2732 RD_ST_RCV_XKB_MASK = 0x3fffff,
2736 u8 clear_counters; /* rsvd 7:1, cc 0 */
2739 u8 xkb; /* xkb 7, rsvd 6:0 */
2759 u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */
2760 u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */
2764 /* Structure for MB Command READ_RPI64 (0x8F) */
2903 #define lpfc_read_link_stat_rec_SHIFT 0
2904 #define lpfc_read_link_stat_rec_MASK 0x1
2908 #define lpfc_read_link_stat_gec_MASK 0x1
2912 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2916 #define lpfc_read_link_stat_rsvd_MASK 0x1F
2920 #define lpfc_read_link_stat_gec2_MASK 0x1
2924 #define lpfc_read_link_stat_clrc_MASK 0x1
2928 #define lpfc_read_link_stat_clof_MASK 0x1
2956 /* Structure for MB Command REG_LOGIN64 (0x93) */
3026 /* Structure for MB Command REG_VPI (0x96) */
3049 /* Structure for MB Command UNREG_VPI (0x97) */
3071 /* Structure for MB Command UNREG_D_ID (0x23) */
3088 /* Structure for MB Command READ_TOPOLOGY (0x95) */
3093 #define lpfc_mbx_read_top_fa_MASK 0x00000001
3096 #define lpfc_mbx_read_top_mm_MASK 0x00000001
3099 #define lpfc_mbx_read_top_pb_MASK 0X00000001
3102 #define lpfc_mbx_read_top_il_MASK 0x00000001
3104 #define lpfc_mbx_read_top_att_type_SHIFT 0
3105 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
3107 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
3108 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
3109 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
3110 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
3113 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
3116 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
3119 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
3121 #define lpfc_mbx_read_top_topology_SHIFT 0
3122 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
3124 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
3125 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
3131 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
3134 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
3137 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
3140 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
3143 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
3145 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
3146 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
3150 #define lpfc_mbx_read_top_lu_MASK 0x00000001
3153 #define lpfc_mbx_read_top_tf_MASK 0x00000001
3156 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
3159 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
3162 #define lpfc_mbx_read_top_tx_MASK 0x00000003
3164 #define lpfc_mbx_read_top_rx_SHIFT 0
3165 #define lpfc_mbx_read_top_rx_MASK 0x00000003
3167 #define LPFC_LINK_SPEED_UNKNOWN 0x0
3168 #define LPFC_LINK_SPEED_1GHZ 0x04
3169 #define LPFC_LINK_SPEED_2GHZ 0x08
3170 #define LPFC_LINK_SPEED_4GHZ 0x10
3171 #define LPFC_LINK_SPEED_8GHZ 0x20
3172 #define LPFC_LINK_SPEED_10GHZ 0x40
3173 #define LPFC_LINK_SPEED_16GHZ 0x80
3174 #define LPFC_LINK_SPEED_32GHZ 0x90
3175 #define LPFC_LINK_SPEED_64GHZ 0xA0
3176 #define LPFC_LINK_SPEED_128GHZ 0xB0
3177 #define LPFC_LINK_SPEED_256GHZ 0xC0
3213 #define DMP_MEM_REG 0x1
3214 #define DMP_NV_PARAMS 0x2
3215 #define DMP_LMSD 0x3 /* Link Module Serial Data */
3216 #define DMP_WELL_KNOWN 0x4
3218 #define DMP_REGION_VPD 0xe
3219 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
3220 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
3221 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
3223 #define DMP_REGION_VPORT 0x16 /* VPort info region */
3224 #define DMP_VPORT_REGION_SIZE 0x200
3225 #define DMP_MBOX_OFFSET_WORD 0x5
3227 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
3228 #define DMP_RGN23_SIZE 0x400
3238 #define VPORT_INFO_SIG 0x32324752
3239 #define VPORT_INFO_REV_MASK 0xff
3240 #define VPORT_INFO_REV 0x1
3270 /* Structure for MB Command UPDATE_CFG (0x1B) */
3441 /* Structure for MB Command CONFIG_PORT (0x88) */
3449 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3452 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3461 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3555 /* Structure for MB Command CONFIG_MSI (0x30) */
3592 #define SLIMOFF 0x30 /* WORD */
3607 #define TYPE_NATIVE_SLI2 0x01
3609 #define FEATURE_INITIAL_SLI2 0x01
3616 #define FEATURE_INITIAL_SLI2 0x01
3618 #define TYPE_NATIVE_SLI2 0x01
3659 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3664 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3666 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3677 #define MAILBOX_HBA_EXT_OFFSET 0x100
3707 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3708 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3711 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3712 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3713 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3714 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3715 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3716 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3718 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3804 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3805 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3806 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3807 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3808 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3809 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3810 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3811 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3812 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3813 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3814 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3815 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3816 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3817 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3818 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3819 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3820 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3821 #define RJT_PROT_ERR 0x12 /* Protocol error */
3822 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3823 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3824 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3825 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3826 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3827 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3828 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3829 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3831 #define IOERR_SUCCESS 0x00 /* statLocalError */
3832 #define IOERR_MISSING_CONTINUE 0x01
3833 #define IOERR_SEQUENCE_TIMEOUT 0x02
3834 #define IOERR_INTERNAL_ERROR 0x03
3835 #define IOERR_INVALID_RPI 0x04
3836 #define IOERR_NO_XRI 0x05
3837 #define IOERR_ILLEGAL_COMMAND 0x06
3838 #define IOERR_XCHG_DROPPED 0x07
3839 #define IOERR_ILLEGAL_FIELD 0x08
3840 #define IOERR_RPI_SUSPENDED 0x09
3841 #define IOERR_TOO_MANY_BUFFERS 0x0A
3842 #define IOERR_RCV_BUFFER_WAITING 0x0B
3843 #define IOERR_NO_CONNECTION 0x0C
3844 #define IOERR_TX_DMA_FAILED 0x0D
3845 #define IOERR_RX_DMA_FAILED 0x0E
3846 #define IOERR_ILLEGAL_FRAME 0x0F
3847 #define IOERR_EXTRA_DATA 0x10
3848 #define IOERR_NO_RESOURCES 0x11
3849 #define IOERR_RESERVED 0x12
3850 #define IOERR_ILLEGAL_LENGTH 0x13
3851 #define IOERR_UNSUPPORTED_FEATURE 0x14
3852 #define IOERR_ABORT_IN_PROGRESS 0x15
3853 #define IOERR_ABORT_REQUESTED 0x16
3854 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3855 #define IOERR_LOOP_OPEN_FAILURE 0x18
3856 #define IOERR_RING_RESET 0x19
3857 #define IOERR_LINK_DOWN 0x1A
3858 #define IOERR_CORRUPTED_DATA 0x1B
3859 #define IOERR_CORRUPTED_RPI 0x1C
3860 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3861 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3862 #define IOERR_DUP_FRAME 0x1F
3863 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3864 #define IOERR_BAD_HOST_ADDRESS 0x21
3865 #define IOERR_RCV_HDRBUF_WAITING 0x22
3866 #define IOERR_MISSING_HDR_BUFFER 0x23
3867 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3868 #define IOERR_ABORTMULT_REQUESTED 0x25
3869 #define IOERR_BUFFER_SHORTAGE 0x28
3870 #define IOERR_DEFAULT 0x29
3871 #define IOERR_CNT 0x2A
3872 #define IOERR_SLER_FAILURE 0x46
3873 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3874 #define IOERR_SLER_REC_RJT_ERR 0x48
3875 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3876 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3877 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3878 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3879 #define IOERR_SLER_ABTS_ERR 0x4E
3880 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3881 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3882 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3883 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3884 #define IOERR_DRVR_MASK 0x100
3885 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3886 #define IOERR_SLI_BRESET 0x102
3887 #define IOERR_SLI_ABORTED 0x103
3888 #define IOERR_PARAM_MASK 0x1ff
3897 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3899 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3905 #define BC 0x02 /* Broadcast Received - Fctl */
3906 #define SI 0x04 /* Sequence Initiative */
3907 #define LA 0x08 /* Ignore Link Attention state */
3908 #define LS 0x80 /* Last Sequence */
3964 #define ABORT_TYPE_ABTX 0x00000000
3965 #define ABORT_TYPE_ABTS 0x00000001
4126 #define ASYNC_TEMP_WARN 0x100
4127 #define ASYNC_TEMP_SAFE 0x101
4128 #define ASYNC_STATUS_CN 0x102
4130 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
4131 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
4158 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
4177 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
4179 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
4181 #define BGS_BG_PROFILE_MASK 0x0000ff00
4183 #define BGS_INVALID_PROF_MASK 0x00000020
4185 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
4187 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
4189 #define BGS_REFTAG_ERR_MASK 0x00000004
4191 #define BGS_APPTAG_ERR_MASK 0x00000002
4193 #define BGS_GUARD_ERR_MASK 0x00000001
4194 #define BGS_GUARD_ERR_SHIFT 0
4379 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
4383 #define CLASS1 0 /* Class 1 */
4388 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4389 #define IOSTAT_FCP_RSP_ERROR 0x1
4390 #define IOSTAT_REMOTE_STOP 0x2
4391 #define IOSTAT_LOCAL_REJECT 0x3
4392 #define IOSTAT_NPORT_RJT 0x4
4393 #define IOSTAT_FABRIC_RJT 0x5
4394 #define IOSTAT_NPORT_BSY 0x6
4395 #define IOSTAT_FABRIC_BSY 0x7
4396 #define IOSTAT_INTERMED_RSP 0x8
4397 #define IOSTAT_LS_RJT 0x9
4398 #define IOSTAT_BA_RJT 0xA
4399 #define IOSTAT_RSVD1 0xB
4400 #define IOSTAT_RSVD2 0xC
4401 #define IOSTAT_RSVD3 0xD
4402 #define IOSTAT_RSVD4 0xE
4403 #define IOSTAT_NEED_BUFFER 0xF
4404 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4405 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4406 #define IOSTAT_CNT 0x11
4442 * 0 => FALSE
4459 return 0; in lpfc_is_LC_HBA()