Lines Matching refs:mem_ptr
2035 (unsigned long)ha->mem_ptr); in ips_host_info()
2235 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2239 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_get_bios_version()
2242 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2246 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_get_bios_version()
2250 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2254 major = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2257 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2260 minor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2263 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2266 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
4241 if (ha->mem_ptr) { in ips_free()
4244 ha->mem_ptr = NULL; in ips_free()
4487 isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isinit_copperhead_memio()
4488 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); in ips_isinit_copperhead_memio()
4516 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_isinit_morpheus()
4517 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isinit_morpheus()
4646 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_enable_int_copperhead_memio()
4647 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ in ips_enable_int_copperhead_memio()
4665 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4667 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4668 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ in ips_enable_int_morpheus()
4785 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4797 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4798 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4811 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4823 readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4824 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4828 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); in ips_init_copperhead_memio()
4842 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); in ips_init_copperhead_memio()
4845 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); in ips_init_copperhead_memio()
4849 writel(0, ha->mem_ptr + IPS_REG_NDAE); in ips_init_copperhead_memio()
4852 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4880 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4897 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4905 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4908 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4925 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4936 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4953 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_morpheus()
4957 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4960 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
4962 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
5044 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5049 writeb(0, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5090 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); in ips_reset_morpheus()
5161 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); in ips_statinit_memio()
5163 ha->mem_ptr + IPS_REG_SQER); in ips_statinit_memio()
5164 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); in ips_statinit_memio()
5165 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); in ips_statinit_memio()
5220 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); in ips_statupd_copperhead_memio()
5241 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); in ips_statupd_morpheus()
5331 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { in ips_issue_copperhead_memio()
5347 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); in ips_issue_copperhead_memio()
5348 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); in ips_issue_copperhead_memio()
5412 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); in ips_issue_i2o_memio()
5466 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5477 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5499 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isintr_morpheus()
6119 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6123 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6128 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6133 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6138 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6146 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6150 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6164 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6172 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6176 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6200 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6205 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6325 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6329 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6333 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6341 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6345 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6356 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6360 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6370 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6374 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6383 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6387 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6461 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6465 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_verify_bios_memio()
6468 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6471 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_verify_bios_memio()
6477 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6482 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); in ips_verify_bios_memio()
6826 char __iomem *mem_ptr; in ips_init_phase1() local
6870 mem_ptr = ioremap_ptr + offs; in ips_init_phase1()
6873 mem_ptr = NULL; in ips_init_phase1()
6893 ha->mem_ptr = mem_ptr; in ips_init_phase1()
6995 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_phase1()