Lines Matching +full:early +full:- +full:to +full:- +full:mid
1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
40 /* ESP config reg 1, read-write, found on all ESP chips */
48 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
52 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */
55 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
58 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */
63 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
65 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
67 #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
70 #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
75 #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
76 #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
77 #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
79 #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
81 /* ESP config register 4 read-write */
82 #define ESP_CONFIG4_BBTE 0x01 /* Back-to-back transfers (fsc) */
95 /* ESP command register read-write */
96 /* Group 1 commands: These may be sent at any point in time to the ESP
106 /* Group 2 commands: ESP must be an initiator and connected to a target
107 * for these commands to work.
111 #define ESP_CMD_MOK 0x12 /* Message okie-dokie */
114 #define ESP_CMD_RATN 0x1b /* De-assert ATN */
117 * to a target as the initiator for these commands to work.
132 * not be connected to any targets as initiator for
133 * these commands to work.
147 /* ESP status register read-only */
162 * with the following values to determine the current phase the ESP
174 #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
183 /* ESP interrupt register read-only */
193 /* ESP sequence step register read-only */
198 #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
199 * bytes to be lost
203 /* Ho hum, some ESP's set the step register to this as well... */
208 /* ESP chip-test register read-write */
213 /* ESP unique ID register read-only, found on fas236+fas100a only */
222 #define ESP_UID_FSC 0x14 /* NCR/Symbios Logic 53CF9x-2 */
224 /* ESP fifo flags register read-only */
230 /* ESP clock conversion factor register write-only */
231 #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
232 #define ESP_CCF_NEVER 0x01 /* Set it to this and die */
234 #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
235 #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
236 #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
237 #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
238 #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
244 #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */
251 /* For slow to medium speed input clock rates we shoot for 5mb/s, but for high
252 * input clock rates we try to do 10mb/s although I don't think a transfer can
270 ESP100, /* NCR53C90 - very broken */
275 FSC, /* NCR/Symbios Logic 53CF9x-2 */
339 /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this
340 * device we will try to negotiate the following parameters.
367 /* Read and write the ESP 8-bit registers. On some
368 * applications of the ESP chip the registers are at 4-byte
369 * instead of 1-byte intervals.
374 /* Return non-zero if there is an IRQ pending. Usually this
376 * the ESP. This has to be accurate or else the ESP interrupt
394 * This is for writes to memory.
406 * is non-zero, this transfer is a write into memory. 'cmd'
414 /* Return non-zero if the DMA engine is reporting an error
445 /* The following are used to determine the cause of an IRQ. Upon every
545 /* A front-end driver for the ESP chip should do the following in
548 * with size 'sizeof(struct esp)'. The first argument to
550 * 2) Set host->max_id as appropriate.
551 * 3) Set esp->host to the scsi_host itself, and esp->dev
552 * to the device object pointer.
553 * 4) Hook up esp->ops to the front-end implementation.
555 * in esp->flags.
558 * in esp->command_block_dma.
561 * esp->scsi_id (assign to esp->host->this_id too)
562 * esp->scsi_id_mask
564 * esp->cfreq
565 * DMA burst bit mask in esp->bursts, if necessary
568 * example, the DMA engine has to be reset before ESP can