1 /* SPDX-License-Identifier: GPL-2.0 */
9  * All common SLI-4 structures and function prototypes.
22  * Common SLI-4 register offsets and field definitions
25 /* SLI_INTF - SLI Interface Definition Register */
51 /* ASIC_ID - SLI ASIC Type and Revision Register */
80 /* BMBX - Bootstrap Mailbox Register */
110 /* SLIPORT_CONTROL - SLI Port Control Register */
118 /* SLI4_SLIPORT_ERROR - SLI Port Error Register */
122 /* EQCQ_DOORBELL - EQ and CQ Doorbell Register */
168 /* EQ_DOORBELL - EQ Doorbell Register for IF_TYPE = 6*/
188 /* CQ_DOORBELL - CQ Doorbell Register for IF_TYPE = 6 */
208 /* MQ_DOORBELL - MQ Doorbell Register */
228 /* RQ_DOORBELL - RQ Doorbell Register */
248 /* WQ_DOORBELL - WQ Doorbell Register */
271 /* SLIPORT_STATUS - SLI Port Status Register */
314  * a 3-word Buffer Descriptor Entry with
343 	SLI4_BDE_TYPE_64	= 0x00,	/* Generic 64-bit data */
351 /* Scatter-Gather Entry (SGE) */
381 /* T10 DIF Scatter-Gather Entry (SGE) */
443 /* List Segment Pointer Scatter-Gather Entry (SGE) */
478 #define SLI4_MCQE_STATUS_NOT_COMPLETED	-2
489 	SLI4_ACQE_AE	= 1 << 6, /* async event - this is an ACQE */
490 	SLI4_ACQE_VAL	= 1 << 7, /* valid - contents of CQE are valid */
555 	__le32		timeout;  member
578 		cpu_to_le32(sizeof(struct sli4_rqst_##stype) - \
583 			varpyld) - sizeof(struct sli4_rqst_hdr))
660 	u8	ulp;  member
834 	u8			ulp;  member
1998 #define SLI4_BMBX_DELAY_US			1000	/* 1 ms */
1999 #define SLI4_INIT_PORT_DELAY_US			10000	/* 10 ms */
2007 	return (bytes + (page_size - 1)) >> __ffs(page_size);  in sli_page_count()
2011  * SLI-4 mailbox command formats and definitions
2058 /* CONFIG_LINK - configure link-oriented parameters,
2099 /* INIT_LINK - initialize the link for a FC port */
2155 /* INIT_VFI - initialize the VFI resource */
2178 /* INIT_VPI - initialize the VPI resource */
2185 /* POST_XRI - post XRI resources to the SLI Port */
2200 /* RELEASE_XRI - Release XRI resources from the SLI Port */
2217 /* READ_CONFIG - read SLI port configuration parameters */
2229 	SLI4_READ_CFG_TOPO_NON_FC_AL	= 0x2,	/* FC point-to-point or fabric */
2230 	SLI4_READ_CFG_TOPO_FC_AL	= 0x3,	/* FC-AL topology */
2278 /* READ_NVPARMS - read SLI port configuration parameters */
2295 /* WRITE_NVPARMS - write SLI port configuration parameters */
2307 /* READ_REV - read the Port revision levels */
2341 /* READ_SPARM64 - read the Port service parameters */
2358 /* READ_TOPOLOGY - read the link event information */
2432 /* REG_FCFI - activate a FC Forwarder */
2496 /* REG_RPI - register a Remote Port Indicator */
2517 /* REG_VFI - register a Virtual Fabric Indicator */
2538 /* REG_VPI - register a Virtual Port Indicator */
2554 /* REQUEST_FEATURES - request / query SLI features */
2585  * SLI_CONFIG - submit a configuration command to Port
2611 /* READ_STATUS - read tx/rx status of a particular port */
2634 /* READ_LNK_STAT - read link status of a particular port */
2701 /* UNREG_FCFI - unregister a FCFI */
2709 /* UNREG_RPI - unregister one or more RPI */
2729 /* UNREG_VFI - unregister one or more VFI */
2751 /* UNREG_VPI - unregister one or more VPI */
2767 /* AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature */
2786  * SLI-4 common configuration command formats and definitions
2847  * Resets the Port, returning it to a power-on state. This configuration
3147  * by the SFF-8472 specification).
3259 	SLI4_DUMP_READY_STATUS_FAILED = -1,
3571 	u8		timeout;  member
3581 	u8		timeout;  member
3602 	u8		timeout;  member
3713 	/* Save pointer to physical memory descriptor for non-embedded
3724 	hdr->opcode = opc;  in sli_cmd_fill_hdr()
3725 	hdr->subsystem = sub;  in sli_cmd_fill_hdr()
3726 	hdr->dw3_version = cpu_to_le32(ver);  in sli_cmd_fill_hdr()
3727 	hdr->request_length = len;  in sli_cmd_fill_hdr()
3737 	return sli4->sge_supported_length;  in sli_get_max_sge()
3743 	if (sli4->sgl_page_sizes != 1) {  in sli_get_max_sgl()
3745 			    sli4->sgl_page_sizes);  in sli_get_max_sgl()
3749 	return (sli4->max_sgl_pages * SLI_PAGE_SIZE) / sizeof(struct sli4_sge);  in sli_get_max_sgl()
3755 	switch (sli4->topology) {  in sli_get_medium()
3768 	return sli4->link_module_type;  in sli_get_lmt()
3780 		sli4->topology = value;  in sli_set_topology()
3784 		rc = -1;  in sli_set_topology()
3796 		count = 1 << (31 - __builtin_clz(mask));  in sli_convert_mask_to_count()
3808 	return readl(sli->reg[0] + SLI4_PORT_STATUS_REGOFF);  in sli_reg_read_status()
3820 	return readl(sli->reg[0] + SLI4_PORT_ERROR1);  in sli_reg_read_err1()
3826 	return readl(sli->reg[0] + SLI4_PORT_ERROR2);  in sli_reg_read_err2()
3837 	if (rcqe->status == SLI4_FC_ASYNC_RQ_SUCCESS) {  in sli_fc_rqe_length()
3838 		*len_hdr  = rcqe->hdpl_byte & SLI4_RACQE_HDPL;  in sli_fc_rqe_length()
3839 		*len_data = le16_to_cpu(rcqe->data_placement_length);  in sli_fc_rqe_length()
3842 		return -1;  in sli_fc_rqe_length()
3856 		fcfi = le16_to_cpu(rcqe->fcfi_rq_id_word) & SLI4_RACQE_FCFI;  in sli_fc_rqe_fcfi()
3862 		fcfi = rcqev1->fcfi_byte & SLI4_RACQE_FCFI;  in sli_fc_rqe_fcfi()
3868 		fcfi = opt_wr->flags0 & SLI4_OCQE_FCFI;  in sli_fc_rqe_fcfi()
4068 		   u32 *hdr, struct efc_dma *payload, u32 req_len, u8 timeout,
4081 		    u16 tag, u16 cq_id, u32 rpi, u32 rnode_fcid, u8 timeout);
4087 		    u8 timeout);
4093 		     u32 rnode_fcid, u8 dif, u8 bs, u8 timeout);
4128 			       u16 timeout);