Lines Matching full:transfer
250 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
251 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
273 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
319 /* transfer. */
325 /* are used to transfer data */
330 /* are used to transfer data */
333 /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
335 /* the Synchronous SCSI Transfer */
381 #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
413 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
414 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
415 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
416 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
428 /* C0 Transfer information out with FIFO */
429 /* C1 Transfer information out with DMA */
430 /* C2 Transfer information in with FIFO */
431 /* C3 Transfer information in with DMA */
433 /* 50 Initiator transfer information out sequence without ATN */
435 /* 70 Initiator transfer information out sequence with ATN */
437 /* 74 Initiator transfer information out sequence with ATN3 */
439 /* 52 Initiator transfer information in sequence without ATN */
441 /* 72 Initiator transfer information in sequence with ATN */
443 /* 76 Initiator transfer information in sequence with ATN3 */
445 /* 90 Initiator transfer information out command complete */
447 /* 92 Initiator transfer information in command complete */
472 #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
492 #define XFERDATAIN_SG 0x0103 /* Transfer data in w/ SG */
493 #define XFERDATAOUT_SG 0x0102 /* Transfer data out w/ SG */
494 #define XFERDATAIN 0x0101 /* Transfer data in w/o SG */
495 #define XFERDATAOUT 0x0100 /* Transfer data out w/o SG */
501 #define STOPDMAXFER 0x08 /* Stop DMA transfer */
502 #define ABORTXFER 0x04 /* Abort DMA transfer */
503 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
504 #define STARTDMAXFER 0x01 /* Start DMA transfer */
509 #define XFERPENDING 0x80 /* Transfer pending */
512 #define FORCEDMACOMP 0x10 /* Force DMA transfer complete */
513 #define DMAXFERERROR 0x08 /* DMA transfer error */
514 #define DMAXFERABORT 0x04 /* DMA transfer abort */
519 #define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */
520 #define EN_DMAXFERERROR 0x08 /* DMA transfer error */
521 #define EN_DMAXFERABORT 0x04 /* DMA transfer abort */
535 #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W), 24bits */
536 #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
537 #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
538 #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */