Lines Matching +full:nc +full:- +full:si
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
70 {"T540-CH 10G", "Chelsio T540-CH 10G [FCoE]"},
71 {"T520-SO 10G", "Chelsio T520-SO 10G [FCoE]"},
72 {"T520-CX4 10G", "Chelsio T520-CX4 10G [FCoE]"},
73 {"T520-BT 10G", "Chelsio T520-BT 10G [FCoE]"},
74 {"T504-BT 1G", "Chelsio T504-BT 1G [FCoE]"},
75 {"B520-SR 10G", "Chelsio B520-SR 10G [FCoE]"},
76 {"B504-BT 1G", "Chelsio B504-BT 1G [FCoE]"},
77 {"T580-CR 10G", "Chelsio T580-CR 10G [FCoE]"},
78 {"T540-LP-CR 10G", "Chelsio T540-LP-CR 10G [FCoE]"},
80 {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"},
81 {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"},
82 {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"},
83 {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"},
84 {"T580-SO 40G", "Chelsio T580-SO 40G [FCoE]"},
85 {"T502-BT 1G", "Chelsio T502-BT 1G [FCoE]"}
118 * csio_hw_wait_op_done_val - wait until an operation is completed
121 * @mask: a single-bit field within @reg that indicates completion
130 * operation completes and -EAGAIN otherwise.
146 if (--attempts == 0) in csio_hw_wait_op_done_val()
147 return -EAGAIN; in csio_hw_wait_op_done_val()
154 * csio_hw_tp_wr_bits_indirect - set/clear bits in an indirect TP register
186 return hw->chip_ops->chip_memory_rw(hw, MEMWIN_CSIOSTOR, mtype, in csio_memory_write()
202 * csio_hw_seeprom_read - read a serial EEPROM location
207 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
216 uint32_t base = hw->params.pci.vpd_cap_addr; in csio_hw_seeprom_read()
219 return -EINVAL; in csio_hw_seeprom_read()
221 pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr); in csio_hw_seeprom_read()
225 pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val); in csio_hw_seeprom_read()
226 } while (!(val & PCI_VPD_ADDR_F) && --attempts); in csio_hw_seeprom_read()
230 return -EINVAL; in csio_hw_seeprom_read()
233 pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data); in csio_hw_seeprom_read()
241 * VPD-R sections.
252 * csio_hw_get_vpd_keyword_val - Locates an information field keyword in
258 * -EINVAL otherwise.
265 const uint8_t *buf = &v->id_tag; in csio_hw_get_vpd_keyword_val()
266 const uint8_t *vpdr_len = &v->vpdr_tag; in csio_hw_get_vpd_keyword_val()
271 return -EINVAL; in csio_hw_get_vpd_keyword_val()
282 return -EINVAL; in csio_hw_get_vpd_keyword_val()
292 return -1; in csio_pci_capability()
296 * csio_hw_get_vpd_params - read VPD parameters from VPD EEPROM
314 ret = csio_pci_capability(hw->pdev, PCI_CAP_ID_VPD, in csio_hw_get_vpd_params()
315 &hw->params.pci.vpd_cap_addr); in csio_hw_get_vpd_params()
317 return -EINVAL; in csio_hw_get_vpd_params()
321 return -ENOMEM; in csio_hw_get_vpd_params()
339 hw->flags &= (~CSIO_HWF_VPD_VALID); in csio_hw_get_vpd_params()
348 return -EINVAL; \ in csio_hw_get_vpd_params()
353 for (csum = 0; i >= 0; i--) in csio_hw_get_vpd_params()
359 return -EINVAL; in csio_hw_get_vpd_params()
365 memcpy(p->id, v->id_data, ID_LEN); in csio_hw_get_vpd_params()
366 s = strstrip(p->id); in csio_hw_get_vpd_params()
367 memcpy(p->ec, vpd + ec, EC_LEN); in csio_hw_get_vpd_params()
368 s = strstrip(p->ec); in csio_hw_get_vpd_params()
369 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; in csio_hw_get_vpd_params()
370 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); in csio_hw_get_vpd_params()
371 s = strstrip(p->sn); in csio_hw_get_vpd_params()
380 * csio_hw_sf1_read - read data from the serial flash
398 return -EINVAL; in csio_hw_sf1_read()
400 return -EBUSY; in csio_hw_sf1_read()
403 BYTECNT_V(byte_cnt - 1), SF_OP_A); in csio_hw_sf1_read()
412 * csio_hw_sf1_write - write data to the serial flash
428 return -EINVAL; in csio_hw_sf1_write()
430 return -EBUSY; in csio_hw_sf1_write()
433 csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | in csio_hw_sf1_write()
441 * csio_hw_flash_wait_op - wait for a flash operation to complete
465 if (--attempts == 0) in csio_hw_flash_wait_op()
466 return -EAGAIN; in csio_hw_flash_wait_op()
473 * csio_hw_read_flash - read words from serial flash
476 * @nwords: how many 32-bit words to read
480 * Read the specified number of 32-bit words from the serial flash.
482 * (i.e., big-endian), otherwise as 32-bit words in the platform's
491 if (addr + nwords * sizeof(uint32_t) > hw->params.sf_size || (addr & 3)) in csio_hw_read_flash()
492 return -EINVAL; in csio_hw_read_flash()
504 for ( ; nwords; nwords--, data++) { in csio_hw_read_flash()
517 * csio_hw_write_flash - write up to a page of data to the serial flash
530 int ret = -EINVAL; in csio_hw_write_flash()
534 if (addr >= hw->params.sf_size || offset + n > SF_PAGE_SIZE) in csio_hw_write_flash()
535 return -EINVAL; in csio_hw_write_flash()
547 for (left = n; left; left -= c) { in csio_hw_write_flash()
567 if (memcmp(data - n, (uint8_t *)buf + offset, n)) { in csio_hw_write_flash()
571 return -EINVAL; in csio_hw_write_flash()
582 * csio_hw_flash_erase_sectors - erase a range of flash sectors
623 FW_HDR_FW_VER_MAJOR_G(hw->fwrev), in csio_hw_print_fw_version()
624 FW_HDR_FW_VER_MINOR_G(hw->fwrev), in csio_hw_print_fw_version()
625 FW_HDR_FW_VER_MICRO_G(hw->fwrev), in csio_hw_print_fw_version()
626 FW_HDR_FW_VER_BUILD_G(hw->fwrev)); in csio_hw_print_fw_version()
630 * csio_hw_get_fw_version - read the firmware version
645 * csio_hw_get_tp_version - read the TP microcode version
660 * csio_hw_fw_dload - download firmware.
679 if ((!hw->params.sf_size) || (!hw->params.sf_nsec)) { in csio_hw_fw_dload()
681 return -EINVAL; in csio_hw_fw_dload()
686 return -EINVAL; in csio_hw_fw_dload()
691 return -EINVAL; in csio_hw_fw_dload()
694 if (ntohs(hdr->len512) * 512 != size) { in csio_hw_fw_dload()
696 return -EINVAL; in csio_hw_fw_dload()
702 return -EINVAL; in csio_hw_fw_dload()
710 return -EINVAL; in csio_hw_fw_dload()
713 sf_sec_size = hw->params.sf_size / hw->params.sf_nsec; in csio_hw_fw_dload()
717 FLASH_FW_START_SEC, FLASH_FW_START_SEC + i - 1); in csio_hw_fw_dload()
720 FLASH_FW_START_SEC + i - 1); in csio_hw_fw_dload()
732 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); in csio_hw_fw_dload()
741 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in csio_hw_fw_dload()
752 sizeof(hdr->fw_ver), in csio_hw_fw_dload()
753 (const uint8_t *)&hdr->fw_ver); in csio_hw_fw_dload()
764 /* Table for non-Numonix supported flash parts. Numonix parts are left in csio_hw_get_flash_params()
786 /* Check to see if it's one of our non-standard supported Flash parts. in csio_hw_get_flash_params()
790 hw->params.sf_size = supported_flash[part].size_mb; in csio_hw_get_flash_params()
791 hw->params.sf_nsec = in csio_hw_get_flash_params()
792 hw->params.sf_size / SF_SEC_SIZE; in csio_hw_get_flash_params()
807 /* This Density -> Size decoding table is taken from Micron in csio_hw_get_flash_params()
812 case 0x14 ... 0x19: /* 1MB - 32MB */ in csio_hw_get_flash_params()
826 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */ in csio_hw_get_flash_params()
827 /* This Density -> Size decoding table is taken from ISSI in csio_hw_get_flash_params()
842 /* This Density -> Size decoding table is taken from in csio_hw_get_flash_params()
867 hw->params.sf_size = size; in csio_hw_get_flash_params()
868 hw->params.sf_nsec = size / SF_SEC_SIZE; in csio_hw_get_flash_params()
871 if (hw->params.sf_size < FLASH_MIN_SIZE) in csio_hw_get_flash_params()
873 flashid, hw->params.sf_size, FLASH_MIN_SIZE); in csio_hw_get_flash_params()
889 (--cnt != 0)) in csio_hw_dev_ready()
892 if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK)) in csio_hw_dev_ready()
900 return -EIO; in csio_hw_dev_ready()
903 hw->pfn = src_pf; in csio_hw_dev_ready()
909 * csio_do_hello - Perform the HELLO FW Mailbox command and process response.
927 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_do_hello()
929 rv = -ENOMEM; in csio_do_hello()
935 csio_mb_hello(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, in csio_do_hello()
936 hw->pfn, CSIO_MASTER_MAY, NULL); in csio_do_hello()
947 rv = -EINVAL; in csio_do_hello()
952 if (hw->pfn == mpfn) { in csio_do_hello()
953 hw->flags |= CSIO_HWF_MASTER; in csio_do_hello()
959 * Note that we also do this wait if we're a non-Master-capable in csio_do_hello()
980 spin_unlock_irq(&hw->lock); in csio_do_hello()
982 spin_lock_irq(&hw->lock); in csio_do_hello()
983 waiting -= 50; in csio_do_hello()
994 if (retries-- > 0) in csio_do_hello()
997 rv = -ETIMEDOUT; in csio_do_hello()
1010 rv = -ETIMEDOUT; in csio_do_hello()
1025 hw->flags &= ~CSIO_HWF_MASTER; in csio_do_hello()
1043 if (hw->pfn == mpfn) in csio_do_hello()
1045 hw->pfn, state_str); in csio_do_hello()
1049 hw->pfn, mpfn, state_str); in csio_do_hello()
1052 mempool_free(mbp, hw->mb_mempool); in csio_do_hello()
1058 * csio_do_bye - Perform the BYE FW Mailbox command and process response.
1068 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_do_bye()
1071 return -ENOMEM; in csio_do_bye()
1078 mempool_free(mbp, hw->mb_mempool); in csio_do_bye()
1079 return -EINVAL; in csio_do_bye()
1084 mempool_free(mbp, hw->mb_mempool); in csio_do_bye()
1085 return -EINVAL; in csio_do_bye()
1088 mempool_free(mbp, hw->mb_mempool); in csio_do_bye()
1094 * csio_do_reset- Perform the device reset.
1115 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_do_reset()
1118 return -ENOMEM; in csio_do_reset()
1126 mempool_free(mbp, hw->mb_mempool); in csio_do_reset()
1127 return -EINVAL; in csio_do_reset()
1133 mempool_free(mbp, hw->mb_mempool); in csio_do_reset()
1134 return -EINVAL; in csio_do_reset()
1137 mempool_free(mbp, hw->mb_mempool); in csio_do_reset()
1145 struct fw_caps_config_cmd *rsp = (struct fw_caps_config_cmd *)mbp->mb; in csio_hw_validate_caps()
1148 caps = ntohs(rsp->fcoecaps); in csio_hw_validate_caps()
1152 return -EINVAL; in csio_hw_validate_caps()
1157 return -EINVAL; in csio_hw_validate_caps()
1164 * csio_hw_fw_halt - issue a reset/halt to FW and put uP into RESET
1191 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_hw_fw_halt()
1194 return -ENOMEM; in csio_hw_fw_halt()
1203 mempool_free(mbp, hw->mb_mempool); in csio_hw_fw_halt()
1204 return -EINVAL; in csio_hw_fw_halt()
1208 mempool_free(mbp, hw->mb_mempool); in csio_hw_fw_halt()
1234 return retval ? -EINVAL : 0; in csio_hw_fw_halt()
1238 * csio_hw_fw_restart - restart the firmware by taking the uP out of RESET
1295 return -ETIMEDOUT; in csio_hw_fw_restart()
1301 * csio_hw_fw_upgrade - perform all of the steps necessary to upgrade FW
1344 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); in csio_hw_fw_upgrade()
1349 * csio_get_device_params - Get device parameters.
1362 /* Initialize portids to -1 */ in csio_get_device_params()
1364 hw->pport[i].portid = -1; in csio_get_device_params()
1366 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_get_device_params()
1369 return -ENOMEM; in csio_get_device_params()
1386 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, in csio_get_device_params()
1390 mempool_free(mbp, hw->mb_mempool); in csio_get_device_params()
1391 return -EINVAL; in csio_get_device_params()
1399 mempool_free(mbp, hw->mb_mempool); in csio_get_device_params()
1400 return -EINVAL; in csio_get_device_params()
1404 hw->port_vec = param[0]; in csio_get_device_params()
1405 hw->vpd.cclk = param[1]; in csio_get_device_params()
1406 wrm->fw_eq_start = param[2]; in csio_get_device_params()
1407 wrm->fw_iq_start = param[4]; in csio_get_device_params()
1410 if ((hw->flags & CSIO_HWF_USING_SOFT_PARAMS) || in csio_get_device_params()
1412 hw->cfg_niq = param[5] - param[4] + 1; in csio_get_device_params()
1413 hw->cfg_neq = param[3] - param[2] + 1; in csio_get_device_params()
1415 hw->cfg_niq, hw->cfg_neq); in csio_get_device_params()
1418 hw->port_vec &= csio_port_mask; in csio_get_device_params()
1420 hw->num_pports = hweight32(hw->port_vec); in csio_get_device_params()
1423 hw->port_vec, hw->num_pports); in csio_get_device_params()
1425 for (i = 0; i < hw->num_pports; i++) { in csio_get_device_params()
1426 while ((hw->port_vec & (1 << j)) == 0) in csio_get_device_params()
1428 hw->pport[i].portid = j++; in csio_get_device_params()
1429 csio_dbg(hw, "Found Port:%d\n", hw->pport[i].portid); in csio_get_device_params()
1431 mempool_free(mbp, hw->mb_mempool); in csio_get_device_params()
1438 * csio_config_device_caps - Get and set device capabilities.
1447 int rv = -EINVAL; in csio_config_device_caps()
1449 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_config_device_caps()
1452 return -ENOMEM; in csio_config_device_caps()
1475 if (hw->fw_state == CSIO_DEV_STATE_INIT) { in csio_config_device_caps()
1497 mempool_free(mbp, hw->mb_mempool); in csio_config_device_caps()
1538 * fwcap_to_fwspeed - return highest speed in Port Capabilities
1568 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
1569 * @caps16: a 16-bit Port Capabilities value
1571 * Returns the equivalent 32-bit Port Capabilities value.
1605 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
1606 * @caps32: a 32-bit Port Capabilities value
1608 * Returns the equivalent 16-bit Port Capabilities value. Note that
1609 * not all 32-bit Port Capabilities can be represented in the 16-bit
1645 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
1649 * 32-bit Port Capabilities value.
1656 * 16-bit Port Information message isn't the same as the in lstatus_to_fwcap()
1657 * 16-bit Port Capabilities bitfield used everywhere else. in lstatus_to_fwcap()
1680 * csio_init_link_config - initialize a link's SW state
1686 * capabilities and default speed/flow-control/autonegotiation settings.
1691 lc->pcaps = pcaps; in csio_init_link_config()
1692 lc->def_acaps = acaps; in csio_init_link_config()
1693 lc->lpacaps = 0; in csio_init_link_config()
1694 lc->speed_caps = 0; in csio_init_link_config()
1695 lc->speed = 0; in csio_init_link_config()
1696 lc->requested_fc = PAUSE_RX | PAUSE_TX; in csio_init_link_config()
1697 lc->fc = lc->requested_fc; in csio_init_link_config()
1703 lc->requested_fec = FEC_AUTO; in csio_init_link_config()
1704 lc->fec = fwcap_to_cc_fec(lc->def_acaps); in csio_init_link_config()
1706 /* If the Port is capable of Auto-Negtotiation, initialize it as in csio_init_link_config()
1709 * Auto-Negotiate disabled and select the highest supported speed in csio_init_link_config()
1713 if (lc->pcaps & FW_PORT_CAP32_ANEG) { in csio_init_link_config()
1714 lc->acaps = lc->pcaps & ADVERT_MASK; in csio_init_link_config()
1715 lc->autoneg = AUTONEG_ENABLE; in csio_init_link_config()
1716 lc->requested_fc |= PAUSE_AUTONEG; in csio_init_link_config()
1718 lc->acaps = 0; in csio_init_link_config()
1719 lc->autoneg = AUTONEG_DISABLE; in csio_init_link_config()
1729 lc->link_ok = 0; in csio_link_l1cfg()
1735 fw_fc = cc_to_fwcap_pause(lc->requested_fc); in csio_link_l1cfg()
1741 * sent us as part of it's IEEE 802.3-based interpretation of in csio_link_l1cfg()
1745 if (lc->requested_fec & FEC_AUTO) in csio_link_l1cfg()
1746 cc_fec = fwcap_to_cc_fec(lc->def_acaps); in csio_link_l1cfg()
1748 cc_fec = lc->requested_fec; in csio_link_l1cfg()
1755 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { in csio_link_l1cfg()
1756 lrcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec; in csio_link_l1cfg()
1757 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG; in csio_link_l1cfg()
1758 lc->fec = cc_fec; in csio_link_l1cfg()
1759 } else if (lc->autoneg == AUTONEG_DISABLE) { in csio_link_l1cfg()
1760 lrcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi; in csio_link_l1cfg()
1761 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG; in csio_link_l1cfg()
1762 lc->fec = cc_fec; in csio_link_l1cfg()
1764 lrcap = lc->acaps | fw_fc | fw_fec | fw_mdi; in csio_link_l1cfg()
1771 * csio_enable_ports - Bring up all available ports.
1785 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_enable_ports()
1788 return -ENOMEM; in csio_enable_ports()
1791 for (i = 0; i < hw->num_pports; i++) { in csio_enable_ports()
1792 portid = hw->pport[i].portid; in csio_enable_ports()
1802 hw->pfn, 0, 1, ¶m, &val, true, in csio_enable_ports()
1808 mempool_free(mbp, hw->mb_mempool); in csio_enable_ports()
1809 return -EINVAL; in csio_enable_ports()
1824 mempool_free(mbp, hw->mb_mempool); in csio_enable_ports()
1825 return -EINVAL; in csio_enable_ports()
1833 mempool_free(mbp, hw->mb_mempool); in csio_enable_ports()
1834 return -EINVAL; in csio_enable_ports()
1837 csio_init_link_config(&hw->pport[i].link_cfg, pcaps, acaps); in csio_enable_ports()
1839 csio_link_l1cfg(&hw->pport[i].link_cfg, fw_caps, &rcaps); in csio_enable_ports()
1848 mempool_free(mbp, hw->mb_mempool); in csio_enable_ports()
1849 return -EINVAL; in csio_enable_ports()
1856 mempool_free(mbp, hw->mb_mempool); in csio_enable_ports()
1857 return -EINVAL; in csio_enable_ports()
1862 mempool_free(mbp, hw->mb_mempool); in csio_enable_ports()
1868 * csio_get_fcoe_resinfo - Read fcoe fw resource info.
1875 struct csio_fcoe_res_info *res_info = &hw->fres_info; in csio_get_fcoe_resinfo()
1880 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_get_fcoe_resinfo()
1883 return -ENOMEM; in csio_get_fcoe_resinfo()
1891 mempool_free(mbp, hw->mb_mempool); in csio_get_fcoe_resinfo()
1892 return -EINVAL; in csio_get_fcoe_resinfo()
1895 rsp = (struct fw_fcoe_res_info_cmd *)(mbp->mb); in csio_get_fcoe_resinfo()
1896 retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16)); in csio_get_fcoe_resinfo()
1900 mempool_free(mbp, hw->mb_mempool); in csio_get_fcoe_resinfo()
1901 return -EINVAL; in csio_get_fcoe_resinfo()
1904 res_info->e_d_tov = ntohs(rsp->e_d_tov); in csio_get_fcoe_resinfo()
1905 res_info->r_a_tov_seq = ntohs(rsp->r_a_tov_seq); in csio_get_fcoe_resinfo()
1906 res_info->r_a_tov_els = ntohs(rsp->r_a_tov_els); in csio_get_fcoe_resinfo()
1907 res_info->r_r_tov = ntohs(rsp->r_r_tov); in csio_get_fcoe_resinfo()
1908 res_info->max_xchgs = ntohl(rsp->max_xchgs); in csio_get_fcoe_resinfo()
1909 res_info->max_ssns = ntohl(rsp->max_ssns); in csio_get_fcoe_resinfo()
1910 res_info->used_xchgs = ntohl(rsp->used_xchgs); in csio_get_fcoe_resinfo()
1911 res_info->used_ssns = ntohl(rsp->used_ssns); in csio_get_fcoe_resinfo()
1912 res_info->max_fcfs = ntohl(rsp->max_fcfs); in csio_get_fcoe_resinfo()
1913 res_info->max_vnps = ntohl(rsp->max_vnps); in csio_get_fcoe_resinfo()
1914 res_info->used_fcfs = ntohl(rsp->used_fcfs); in csio_get_fcoe_resinfo()
1915 res_info->used_vnps = ntohl(rsp->used_vnps); in csio_get_fcoe_resinfo()
1917 csio_dbg(hw, "max ssns:%d max xchgs:%d\n", res_info->max_ssns, in csio_get_fcoe_resinfo()
1918 res_info->max_xchgs); in csio_get_fcoe_resinfo()
1919 mempool_free(mbp, hw->mb_mempool); in csio_get_fcoe_resinfo()
1931 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_hw_check_fwconfig()
1934 return -ENOMEM; in csio_hw_check_fwconfig()
1944 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, in csio_hw_check_fwconfig()
1948 mempool_free(mbp, hw->mb_mempool); in csio_hw_check_fwconfig()
1949 return -EINVAL; in csio_hw_check_fwconfig()
1957 mempool_free(mbp, hw->mb_mempool); in csio_hw_check_fwconfig()
1958 return -EINVAL; in csio_hw_check_fwconfig()
1961 mempool_free(mbp, hw->mb_mempool); in csio_hw_check_fwconfig()
1972 struct pci_dev *pci_dev = hw->pdev; in csio_hw_flash_config()
1973 struct device *dev = &pci_dev->dev; in csio_hw_flash_config()
1979 if (csio_is_t5(pci_dev->device & CSIO_HW_CHIP_MASK)) in csio_hw_flash_config()
1987 return -ENOENT; in csio_hw_flash_config()
1990 if (cf->size%4 != 0) in csio_hw_flash_config()
1991 value_to_add = 4 - (cf->size % 4); in csio_hw_flash_config()
1993 cfg_data = kzalloc(cf->size+value_to_add, GFP_KERNEL); in csio_hw_flash_config()
1995 ret = -ENOMEM; in csio_hw_flash_config()
1999 memcpy((void *)cfg_data, (const void *)cf->data, cf->size); in csio_hw_flash_config()
2001 ret = -EINVAL; in csio_hw_flash_config()
2009 cf->size + value_to_add, cfg_data); in csio_hw_flash_config()
2016 size_t size = cf->size & ~0x3; in csio_hw_flash_config()
2039 * we use that to perform all configuration -- either using the configuration
2040 * file stored in flash on the adapter or using a filesystem-local file
2044 * have to set things up the old fashioned way with hard-coded register
2057 int rv = -EINVAL; in csio_hw_use_fwconfig()
2076 spin_unlock_irq(&hw->lock); in csio_hw_use_fwconfig()
2078 spin_lock_irq(&hw->lock); in csio_hw_use_fwconfig()
2086 maddr = hw->chip_ops->chip_flash_cfg_addr(hw); in csio_hw_use_fwconfig()
2093 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_hw_use_fwconfig()
2096 return -ENOMEM; in csio_hw_use_fwconfig()
2104 caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb); in csio_hw_use_fwconfig()
2106 caps_cmd->op_to_write = in csio_hw_use_fwconfig()
2110 caps_cmd->cfvalid_to_len16 = in csio_hw_use_fwconfig()
2117 rv = -EINVAL; in csio_hw_use_fwconfig()
2130 caps_cmd->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | in csio_hw_use_fwconfig()
2133 caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd)); in csio_hw_use_fwconfig()
2136 rv = -EINVAL; in csio_hw_use_fwconfig()
2146 finiver = ntohl(caps_cmd->finiver); in csio_hw_use_fwconfig()
2147 finicsum = ntohl(caps_cmd->finicsum); in csio_hw_use_fwconfig()
2148 cfcsum = ntohl(caps_cmd->cfcsum); in csio_hw_use_fwconfig()
2153 caps_cmd->op_to_write = in csio_hw_use_fwconfig()
2157 caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd)); in csio_hw_use_fwconfig()
2160 rv = -EINVAL; in csio_hw_use_fwconfig()
2181 mempool_free(mbp, hw->mb_mempool); in csio_hw_use_fwconfig()
2186 * not supplied by the driver, rather than from hard-wired in csio_hw_use_fwconfig()
2189 hw->flags |= CSIO_HWF_USING_SOFT_PARAMS; in csio_hw_use_fwconfig()
2204 csio_post_event(&hw->sm, CSIO_HWE_INIT); in csio_hw_use_fwconfig()
2216 mempool_free(mbp, hw->mb_mempool); in csio_hw_use_fwconfig()
2217 hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS; in csio_hw_use_fwconfig()
2229 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) in fw_compatible()
2232 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) in fw_compatible()
2233 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && in fw_compatible()
2323 drv_fw = &fw_info->fw_hdr; in csio_hw_prep_fw()
2345 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && in csio_hw_prep_fw()
2346 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { in csio_hw_prep_fw()
2353 be32_to_cpu(fs_fw->fw_ver), in csio_hw_prep_fw()
2354 be32_to_cpu(card_fw->fw_ver))) { in csio_hw_prep_fw()
2355 ret = csio_hw_fw_upgrade(hw, hw->pfn, fw_data, in csio_hw_prep_fw()
2372 d = be32_to_cpu(drv_fw->fw_ver); in csio_hw_prep_fw()
2373 c = be32_to_cpu(card_fw->fw_ver); in csio_hw_prep_fw()
2374 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; in csio_hw_prep_fw()
2387 ret = -EINVAL; in csio_hw_prep_fw()
2392 hw->fwrev = be32_to_cpu(card_fw->fw_ver); in csio_hw_prep_fw()
2393 hw->tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in csio_hw_prep_fw()
2400 * Returns -EINVAL if attempts to flash the firmware failed,
2401 * -ENOMEM if memory allocation failed else returns 0,
2408 int ret = -ECANCELED; in csio_hw_flash_fw()
2412 struct pci_dev *pci_dev = hw->pdev; in csio_hw_flash_fw()
2413 struct device *dev = &pci_dev->dev ; in csio_hw_flash_fw()
2421 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(hw->chip_id)); in csio_hw_flash_fw()
2425 CHELSIO_CHIP_VERSION(hw->chip_id)); in csio_hw_flash_fw()
2426 return -EINVAL; in csio_hw_flash_fw()
2434 return -ENOMEM; in csio_hw_flash_fw()
2436 if (csio_is_t5(pci_dev->device & CSIO_HW_CHIP_MASK)) in csio_hw_flash_fw()
2445 fw_data = fw->data; in csio_hw_flash_fw()
2446 fw_size = fw->size; in csio_hw_flash_fw()
2451 hw->fw_state, reset); in csio_hw_flash_fw()
2462 if (csio_is_t6(hw->pdev->device & CSIO_HW_CHIP_MASK) && in csio_hw_check_fwver()
2463 (hw->fwrev < CSIO_MIN_T6_FW)) { in csio_hw_check_fwver()
2465 return -1; in csio_hw_check_fwver()
2472 * csio_hw_configure - Configure HW
2473 * @hw - HW module
2486 csio_post_event(&hw->sm, CSIO_HWE_FATAL); in csio_hw_configure()
2491 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A); in csio_hw_configure()
2497 csio_post_event(&hw->sm, CSIO_HWE_FATAL); in csio_hw_configure()
2502 if (pci_is_pcie(hw->pdev)) in csio_hw_configure()
2503 pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2, in csio_hw_configure()
2506 hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR); in csio_hw_configure()
2508 rv = csio_hw_get_fw_version(hw, &hw->fwrev); in csio_hw_configure()
2514 rv = csio_do_hello(hw, &hw->fw_state); in csio_hw_configure()
2517 csio_post_event(&hw->sm, CSIO_HWE_FATAL); in csio_hw_configure()
2522 rv = csio_hw_get_vpd_params(hw, &hw->vpd); in csio_hw_configure()
2526 csio_hw_get_fw_version(hw, &hw->fwrev); in csio_hw_configure()
2527 csio_hw_get_tp_version(hw, &hw->tp_vers); in csio_hw_configure()
2528 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { in csio_hw_configure()
2531 spin_unlock_irq(&hw->lock); in csio_hw_configure()
2533 spin_lock_irq(&hw->lock); in csio_hw_configure()
2557 if (rv == -ENOENT) { in csio_hw_configure()
2573 if (hw->fw_state == CSIO_DEV_STATE_INIT) { in csio_hw_configure()
2575 hw->flags |= CSIO_HWF_USING_SOFT_PARAMS; in csio_hw_configure()
2591 csio_post_event(&hw->sm, CSIO_HWE_INIT); in csio_hw_configure()
2601 * csio_hw_initialize - Initialize HW
2602 * @hw - HW module
2613 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { in csio_hw_initialize()
2614 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); in csio_hw_initialize()
2632 mempool_free(mbp, hw->mb_mempool); in csio_hw_initialize()
2641 spin_unlock_irq(&hw->lock); in csio_hw_initialize()
2643 spin_lock_irq(&hw->lock); in csio_hw_initialize()
2650 for (i = 0; i < hw->num_pports; i++) in csio_hw_initialize()
2651 hw->pport[i].mod_type = FW_PORT_MOD_TYPE_NA; in csio_hw_initialize()
2653 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { in csio_hw_initialize()
2661 csio_post_event(&hw->sm, CSIO_HWE_INIT_DONE); in csio_hw_initialize()
2665 mempool_free(mbp, hw->mb_mempool); in csio_hw_initialize()
2673 * csio_hw_intr_enable - Enable HW interrupts
2685 if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK)) in csio_hw_intr_enable()
2694 if (hw->intr_mode == CSIO_IM_MSIX) in csio_hw_intr_enable()
2697 else if (hw->intr_mode == CSIO_IM_MSI) in csio_hw_intr_enable()
2703 /* Turn on MB interrupts - this will internally flush PIO as well */ in csio_hw_intr_enable()
2706 /* These are common registers - only a master can modify them */ in csio_hw_intr_enable()
2726 hw->flags |= CSIO_HWF_HW_INTR_ENABLED; in csio_hw_intr_enable()
2731 * csio_hw_intr_disable - Disable HW interrupts
2741 if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK)) in csio_hw_intr_disable()
2746 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED)) in csio_hw_intr_disable()
2749 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED; in csio_hw_intr_disable()
2774 * csio_hws_uninit - Uninit state
2775 * @hw - HW module
2776 * @evt - Event
2782 hw->prev_evt = hw->cur_evt; in csio_hws_uninit()
2783 hw->cur_evt = evt; in csio_hws_uninit()
2788 csio_set_state(&hw->sm, csio_hws_configuring); in csio_hws_uninit()
2799 * csio_hws_configuring - Configuring state
2800 * @hw - HW module
2801 * @evt - Event
2807 hw->prev_evt = hw->cur_evt; in csio_hws_configuring()
2808 hw->cur_evt = evt; in csio_hws_configuring()
2813 csio_set_state(&hw->sm, csio_hws_initializing); in csio_hws_configuring()
2818 csio_set_state(&hw->sm, csio_hws_ready); in csio_hws_configuring()
2824 csio_set_state(&hw->sm, csio_hws_uninit); in csio_hws_configuring()
2837 * csio_hws_initializing - Initializing state
2838 * @hw - HW module
2839 * @evt - Event
2845 hw->prev_evt = hw->cur_evt; in csio_hws_initializing()
2846 hw->cur_evt = evt; in csio_hws_initializing()
2851 csio_set_state(&hw->sm, csio_hws_ready); in csio_hws_initializing()
2861 csio_set_state(&hw->sm, csio_hws_uninit); in csio_hws_initializing()
2875 * csio_hws_ready - Ready state
2876 * @hw - HW module
2877 * @evt - Event
2884 hw->evtflag = evt; in csio_hws_ready()
2886 hw->prev_evt = hw->cur_evt; in csio_hws_ready()
2887 hw->cur_evt = evt; in csio_hws_ready()
2896 csio_set_state(&hw->sm, csio_hws_quiescing); in csio_hws_ready()
2910 csio_post_event(&hw->sm, CSIO_HWE_QUIESCED); in csio_hws_ready()
2914 csio_set_state(&hw->sm, csio_hws_uninit); in csio_hws_ready()
2924 * csio_hws_quiescing - Quiescing state
2925 * @hw - HW module
2926 * @evt - Event
2932 hw->prev_evt = hw->cur_evt; in csio_hws_quiescing()
2933 hw->cur_evt = evt; in csio_hws_quiescing()
2938 switch (hw->evtflag) { in csio_hws_quiescing()
2940 csio_set_state(&hw->sm, csio_hws_resetting); in csio_hws_quiescing()
2945 csio_set_state(&hw->sm, csio_hws_resetting); in csio_hws_quiescing()
2950 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET_DONE); in csio_hws_quiescing()
2954 csio_set_state(&hw->sm, csio_hws_removing); in csio_hws_quiescing()
2962 csio_set_state(&hw->sm, csio_hws_quiesced); in csio_hws_quiescing()
2966 csio_set_state(&hw->sm, csio_hws_pcierr); in csio_hws_quiescing()
2984 * csio_hws_quiesced - Quiesced state
2985 * @hw - HW module
2986 * @evt - Event
2992 hw->prev_evt = hw->cur_evt; in csio_hws_quiesced()
2993 hw->cur_evt = evt; in csio_hws_quiesced()
2998 csio_set_state(&hw->sm, csio_hws_configuring); in csio_hws_quiesced()
3009 * csio_hws_resetting - HW Resetting state
3010 * @hw - HW module
3011 * @evt - Event
3017 hw->prev_evt = hw->cur_evt; in csio_hws_resetting()
3018 hw->cur_evt = evt; in csio_hws_resetting()
3024 csio_set_state(&hw->sm, csio_hws_configuring); in csio_hws_resetting()
3035 * csio_hws_removing - PCI Hotplug removing state
3036 * @hw - HW module
3037 * @evt - Event
3043 hw->prev_evt = hw->cur_evt; in csio_hws_removing()
3044 hw->cur_evt = evt; in csio_hws_removing()
3070 * csio_hws_pcierr - PCI Error state
3071 * @hw - HW module
3072 * @evt - Event
3078 hw->prev_evt = hw->cur_evt; in csio_hws_pcierr()
3079 hw->cur_evt = evt; in csio_hws_pcierr()
3085 csio_set_state(&hw->sm, csio_hws_configuring); in csio_hws_pcierr()
3100 * csio_handle_intr_status - table driven interrupt handler
3120 for ( ; acts->mask; ++acts) { in csio_handle_intr_status()
3121 if (!(status & acts->mask)) in csio_handle_intr_status()
3123 if (acts->fatal) { in csio_handle_intr_status()
3126 acts->msg, status & acts->mask); in csio_handle_intr_status()
3127 } else if (acts->msg) in csio_handle_intr_status()
3129 acts->msg, status & acts->mask); in csio_handle_intr_status()
3130 mask |= acts->mask; in csio_handle_intr_status()
3144 { 0x3fffffff, "TP parity error", -1, 1 }, in csio_tp_intr_handler()
3145 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, in csio_tp_intr_handler()
3162 "SGE received CPL exceeding IQE size", -1, 1 }, in csio_sge_intr_handler()
3164 "SGE GTS CIDX increment too large", -1, 0 }, in csio_sge_intr_handler()
3165 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, in csio_sge_intr_handler()
3166 { ERR_DROPPED_DB_F, "SGE doorbell dropped", -1, 0 }, in csio_sge_intr_handler()
3168 "SGE IQID > 1023 received CPL for FL", -1, 0 }, in csio_sge_intr_handler()
3169 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, in csio_sge_intr_handler()
3171 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, in csio_sge_intr_handler()
3173 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, in csio_sge_intr_handler()
3175 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, in csio_sge_intr_handler()
3178 "SGE too many priority ingress contexts", -1, 0 }, in csio_sge_intr_handler()
3180 "SGE too many priority egress contexts", -1, 0 }, in csio_sge_intr_handler()
3181 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, in csio_sge_intr_handler()
3182 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, in csio_sge_intr_handler()
3214 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, in csio_cim_intr_handler()
3215 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, in csio_cim_intr_handler()
3216 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, in csio_cim_intr_handler()
3217 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, in csio_cim_intr_handler()
3218 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, in csio_cim_intr_handler()
3219 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, in csio_cim_intr_handler()
3220 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, in csio_cim_intr_handler()
3224 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, in csio_cim_intr_handler()
3225 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, in csio_cim_intr_handler()
3226 { ILLWRINT_F, "CIM illegal write", -1, 1 }, in csio_cim_intr_handler()
3227 { ILLRDINT_F, "CIM illegal read", -1, 1 }, in csio_cim_intr_handler()
3228 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, in csio_cim_intr_handler()
3229 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, in csio_cim_intr_handler()
3230 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, in csio_cim_intr_handler()
3231 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, in csio_cim_intr_handler()
3232 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, in csio_cim_intr_handler()
3233 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, in csio_cim_intr_handler()
3234 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, in csio_cim_intr_handler()
3235 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, in csio_cim_intr_handler()
3236 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, in csio_cim_intr_handler()
3237 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, in csio_cim_intr_handler()
3238 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, in csio_cim_intr_handler()
3239 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, in csio_cim_intr_handler()
3240 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, in csio_cim_intr_handler()
3241 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, in csio_cim_intr_handler()
3242 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, in csio_cim_intr_handler()
3243 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, in csio_cim_intr_handler()
3244 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, in csio_cim_intr_handler()
3245 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, in csio_cim_intr_handler()
3246 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, in csio_cim_intr_handler()
3247 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, in csio_cim_intr_handler()
3248 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, in csio_cim_intr_handler()
3249 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, in csio_cim_intr_handler()
3250 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, in csio_cim_intr_handler()
3251 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, in csio_cim_intr_handler()
3271 { 0x1800000, "ULPRX context error", -1, 1 }, in csio_ulprx_intr_handler()
3272 { 0x7fffff, "ULPRX parity error", -1, 1 }, in csio_ulprx_intr_handler()
3286 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, in csio_ulptx_intr_handler()
3288 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, in csio_ulptx_intr_handler()
3290 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, in csio_ulptx_intr_handler()
3292 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, in csio_ulptx_intr_handler()
3294 { 0xfffffff, "ULPTX parity error", -1, 1 }, in csio_ulptx_intr_handler()
3308 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, in csio_pmtx_intr_handler()
3309 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, in csio_pmtx_intr_handler()
3310 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, in csio_pmtx_intr_handler()
3311 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, in csio_pmtx_intr_handler()
3312 { 0xffffff0, "PMTX framing error", -1, 1 }, in csio_pmtx_intr_handler()
3313 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, in csio_pmtx_intr_handler()
3314 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1, in csio_pmtx_intr_handler()
3316 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, in csio_pmtx_intr_handler()
3317 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, in csio_pmtx_intr_handler()
3331 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, in csio_pmrx_intr_handler()
3332 { 0x3ffff0, "PMRX framing error", -1, 1 }, in csio_pmrx_intr_handler()
3333 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, in csio_pmrx_intr_handler()
3334 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1, in csio_pmrx_intr_handler()
3336 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, in csio_pmrx_intr_handler()
3337 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, in csio_pmrx_intr_handler()
3351 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, in csio_cplsw_intr_handler()
3352 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, in csio_cplsw_intr_handler()
3353 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, in csio_cplsw_intr_handler()
3354 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, in csio_cplsw_intr_handler()
3355 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, in csio_cplsw_intr_handler()
3356 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, in csio_cplsw_intr_handler()
3369 enum chip_type chip = CHELSIO_CHIP_VERSION(hw->chip_id); in csio_le_intr_handler()
3372 { LIPMISS_F, "LE LIP miss", -1, 0 }, in csio_le_intr_handler()
3373 { LIP0_F, "LE 0 LIP error", -1, 0 }, in csio_le_intr_handler()
3374 { PARITYERR_F, "LE parity error", -1, 1 }, in csio_le_intr_handler()
3375 { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, in csio_le_intr_handler()
3376 { REQQPARERR_F, "LE request queue parity error", -1, 1 }, in csio_le_intr_handler()
3381 { T6_LIPMISS_F, "LE LIP miss", -1, 0 }, in csio_le_intr_handler()
3382 { T6_LIP0_F, "LE 0 LIP error", -1, 0 }, in csio_le_intr_handler()
3383 { TCAMINTPERR_F, "LE parity error", -1, 1 }, in csio_le_intr_handler()
3384 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 }, in csio_le_intr_handler()
3385 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 }, in csio_le_intr_handler()
3401 { 0xffffff, "MPS Rx parity error", -1, 1 }, in csio_mps_intr_handler()
3405 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, in csio_mps_intr_handler()
3406 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, in csio_mps_intr_handler()
3408 -1, 1 }, in csio_mps_intr_handler()
3410 -1, 1 }, in csio_mps_intr_handler()
3411 { BUBBLE_F, "MPS Tx underflow", -1, 1 }, in csio_mps_intr_handler()
3412 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, in csio_mps_intr_handler()
3413 { FRMERR_F, "MPS Tx framing error", -1, 1 }, in csio_mps_intr_handler()
3417 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, in csio_mps_intr_handler()
3419 -1, 1 }, in csio_mps_intr_handler()
3420 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, in csio_mps_intr_handler()
3424 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, in csio_mps_intr_handler()
3428 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, in csio_mps_intr_handler()
3432 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, in csio_mps_intr_handler()
3436 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, in csio_mps_intr_handler()
3437 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, in csio_mps_intr_handler()
3438 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, in csio_mps_intr_handler()
3516 "MA address wrap-around error by client %u to address %#x\n", in csio_ma_intr_handler()
3529 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, in csio_smb_intr_handler()
3530 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, in csio_smb_intr_handler()
3531 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, in csio_smb_intr_handler()
3540 * NC-SI interrupt handler.
3545 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, in csio_ncsi_intr_handler()
3546 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, in csio_ncsi_intr_handler()
3547 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, in csio_ncsi_intr_handler()
3548 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, in csio_ncsi_intr_handler()
3581 { FATALPERR_F, "T4 fatal parity error", -1, 1 }, in csio_pl_intr_handler()
3582 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, in csio_pl_intr_handler()
3591 * csio_hw_slow_intr_handler - control path interrupt handler
3594 * Interrupt handler for non-data global interrupt events, e.g., errors.
3640 hw->chip_ops->chip_pcie_intr_handler(hw); in csio_hw_slow_intr_handler()
3686 * HW <--> mailbox interfacing routines.
3689 * csio_mberr_worker - Worker thread (dpc) for mailbox/error completions
3699 struct csio_mbm *mbm = &hw->mbm; in csio_mberr_worker()
3704 del_timer_sync(&mbm->timer); in csio_mberr_worker()
3706 spin_lock_irq(&hw->lock); in csio_mberr_worker()
3707 if (list_empty(&mbm->cbfn_q)) { in csio_mberr_worker()
3708 spin_unlock_irq(&hw->lock); in csio_mberr_worker()
3712 list_splice_tail_init(&mbm->cbfn_q, &cbfn_q); in csio_mberr_worker()
3713 mbm->stats.n_cbfnq = 0; in csio_mberr_worker()
3716 if (!list_empty(&mbm->req_q)) { in csio_mberr_worker()
3717 mbp_next = list_first_entry(&mbm->req_q, struct csio_mb, list); in csio_mberr_worker()
3718 list_del_init(&mbp_next->list); in csio_mberr_worker()
3722 list_add_tail(&mbp_next->list, &mbm->req_q); in csio_mberr_worker()
3726 spin_unlock_irq(&hw->lock); in csio_mberr_worker()
3733 * csio_hw_mb_timer - Top-level Mailbox timeout handler.
3742 struct csio_hw *hw = mbm->hw; in csio_hw_mb_timer()
3745 spin_lock_irq(&hw->lock); in csio_hw_mb_timer()
3747 spin_unlock_irq(&hw->lock); in csio_hw_mb_timer()
3749 /* Call back the function for the timed-out Mailbox */ in csio_hw_mb_timer()
3751 mbp->mb_cbfn(hw, mbp); in csio_hw_mb_timer()
3756 * csio_hw_mbm_cleanup - Cleanup Mailbox module.
3760 * Cancels outstanding mailboxes (waiting, in-flight) and gathers them
3771 spin_unlock_irq(&hw->lock); in csio_hw_mbm_cleanup()
3773 spin_lock_irq(&hw->lock); in csio_hw_mbm_cleanup()
3786 return -EINVAL; in csio_enqueue_evt()
3789 return -EINVAL; in csio_enqueue_evt()
3791 if (hw->flags & CSIO_HWF_FWEVT_STOP) in csio_enqueue_evt()
3792 return -EINVAL; in csio_enqueue_evt()
3794 if (list_empty(&hw->evt_free_q)) { in csio_enqueue_evt()
3797 return -ENOMEM; in csio_enqueue_evt()
3800 evt_entry = list_first_entry(&hw->evt_free_q, in csio_enqueue_evt()
3802 list_del_init(&evt_entry->list); in csio_enqueue_evt()
3805 evt_entry->type = type; in csio_enqueue_evt()
3806 memcpy((void *)evt_entry->data, evt_msg, len); in csio_enqueue_evt()
3807 list_add_tail(&evt_entry->list, &hw->evt_active_q); in csio_enqueue_evt()
3826 return -EINVAL; in csio_enqueue_evt_lock()
3829 return -EINVAL; in csio_enqueue_evt_lock()
3831 spin_lock_irqsave(&hw->lock, flags); in csio_enqueue_evt_lock()
3832 if (hw->flags & CSIO_HWF_FWEVT_STOP) { in csio_enqueue_evt_lock()
3833 ret = -EINVAL; in csio_enqueue_evt_lock()
3837 if (list_empty(&hw->evt_free_q)) { in csio_enqueue_evt_lock()
3840 ret = -ENOMEM; in csio_enqueue_evt_lock()
3844 evt_entry = list_first_entry(&hw->evt_free_q, in csio_enqueue_evt_lock()
3846 list_del_init(&evt_entry->list); in csio_enqueue_evt_lock()
3849 evt_entry->type = type; in csio_enqueue_evt_lock()
3855 memcpy((void *)((uintptr_t)evt_entry->data + off), in csio_enqueue_evt_lock()
3856 fl_sg->flbufs[n].vaddr, in csio_enqueue_evt_lock()
3857 fl_sg->flbufs[n].len); in csio_enqueue_evt_lock()
3858 off += fl_sg->flbufs[n].len; in csio_enqueue_evt_lock()
3861 memcpy((void *)evt_entry->data, evt_msg, len); in csio_enqueue_evt_lock()
3863 list_add_tail(&evt_entry->list, &hw->evt_active_q); in csio_enqueue_evt_lock()
3867 spin_unlock_irqrestore(&hw->lock, flags); in csio_enqueue_evt_lock()
3875 spin_lock_irq(&hw->lock); in csio_free_evt()
3876 list_del_init(&evt_entry->list); in csio_free_evt()
3877 list_add_tail(&evt_entry->list, &hw->evt_free_q); in csio_free_evt()
3880 spin_unlock_irq(&hw->lock); in csio_free_evt()
3889 while (hw->flags & CSIO_HWF_FWEVT_PENDING && count--) { in csio_evtq_flush()
3890 spin_unlock_irq(&hw->lock); in csio_evtq_flush()
3892 spin_lock_irq(&hw->lock); in csio_evtq_flush()
3895 CSIO_DB_ASSERT(!(hw->flags & CSIO_HWF_FWEVT_PENDING)); in csio_evtq_flush()
3901 hw->flags |= CSIO_HWF_FWEVT_STOP; in csio_evtq_stop()
3907 hw->flags &= ~CSIO_HWF_FWEVT_STOP; in csio_evtq_start()
3916 if (!list_empty(&hw->evt_active_q)) in csio_evtq_cleanup()
3917 list_splice_tail_init(&hw->evt_active_q, &hw->evt_free_q); in csio_evtq_cleanup()
3919 hw->stats.n_evt_activeq = 0; in csio_evtq_cleanup()
3920 hw->flags &= ~CSIO_HWF_FWEVT_PENDING; in csio_evtq_cleanup()
3923 list_for_each_safe(evt_entry, next_entry, &hw->evt_free_q) { in csio_evtq_cleanup()
3928 hw->stats.n_evt_freeq = 0; in csio_evtq_cleanup()
3941 op = ((struct rss_header *) wr)->opcode; in csio_process_fwevtq_entry()
3944 if (!flb || !flb->totlen) { in csio_process_fwevtq_entry()
3950 msg_len = flb->totlen; in csio_process_fwevtq_entry()
3987 hw->stats.n_evt_activeq); in csio_evtq_worker()
3989 spin_lock_irq(&hw->lock); in csio_evtq_worker()
3990 while (!list_empty(&hw->evt_active_q)) { in csio_evtq_worker()
3991 list_splice_tail_init(&hw->evt_active_q, &evt_q); in csio_evtq_worker()
3992 spin_unlock_irq(&hw->lock); in csio_evtq_worker()
3998 spin_lock_irq(&hw->lock); in csio_evtq_worker()
3999 if (hw->flags & CSIO_HWF_FWEVT_STOP) in csio_evtq_worker()
4001 spin_unlock_irq(&hw->lock); in csio_evtq_worker()
4007 switch (evt_msg->type) { in csio_evtq_worker()
4009 msg = (struct cpl_fw6_msg *)(evt_msg->data); in csio_evtq_worker()
4011 if ((msg->opcode == CPL_FW6_MSG || in csio_evtq_worker()
4012 msg->opcode == CPL_FW4_MSG) && in csio_evtq_worker()
4013 !msg->type) { in csio_evtq_worker()
4015 msg->data); in csio_evtq_worker()
4020 msg->opcode, msg->data); in csio_evtq_worker()
4021 } else if (msg->opcode == CPL_FW6_PLD) { in csio_evtq_worker()
4024 msg->opcode, msg->data); in csio_evtq_worker()
4028 msg->opcode, msg->type); in csio_evtq_worker()
4038 memcpy(&rn, evt_msg->data, sizeof(rn)); in csio_evtq_worker()
4044 evt_msg->type); in csio_evtq_worker()
4052 spin_lock_irq(&hw->lock); in csio_evtq_worker()
4054 hw->flags &= ~CSIO_HWF_FWEVT_PENDING; in csio_evtq_worker()
4055 spin_unlock_irq(&hw->lock); in csio_evtq_worker()
4063 if (csio_q_iqid(hw, hw->fwevt_iq_idx) == CSIO_MAX_QID) { in csio_fwevtq_handler()
4065 return -EINVAL; in csio_fwevtq_handler()
4068 rv = csio_wr_process_iq_idx(hw, hw->fwevt_iq_idx, in csio_fwevtq_handler()
4079 * csio_mgmt_req_lookup - Lookup the given IO req exist in Active Q.
4080 * mgmt - mgmt module
4081 * @io_req - io request
4083 * Return - 0:if given IO Req exists in active Q.
4084 * -EINVAL :if lookup fails.
4092 list_for_each(tmp, &mgmtm->active_q) { in csio_mgmt_req_lookup()
4096 return -EINVAL; in csio_mgmt_req_lookup()
4102 * csio_mgmts_tmo_handler - MGMT IO Timeout handler.
4103 * @data - Event data.
4105 * Return - none.
4114 csio_dbg(mgmtm->hw, "Mgmt timer invoked!\n"); in csio_mgmt_tmo_handler()
4116 spin_lock_irq(&mgmtm->hw->lock); in csio_mgmt_tmo_handler()
4118 list_for_each(tmp, &mgmtm->active_q) { in csio_mgmt_tmo_handler()
4120 io_req->tmo -= min_t(uint32_t, io_req->tmo, ECM_MIN_TMO); in csio_mgmt_tmo_handler()
4122 if (!io_req->tmo) { in csio_mgmt_tmo_handler()
4125 list_del_init(&io_req->sm.sm_list); in csio_mgmt_tmo_handler()
4126 if (io_req->io_cbfn) { in csio_mgmt_tmo_handler()
4128 io_req->wr_status = -ETIMEDOUT; in csio_mgmt_tmo_handler()
4129 io_req->io_cbfn(mgmtm->hw, io_req); in csio_mgmt_tmo_handler()
4136 /* If retry queue is not empty, re-arm timer */ in csio_mgmt_tmo_handler()
4137 if (!list_empty(&mgmtm->active_q)) in csio_mgmt_tmo_handler()
4138 mod_timer(&mgmtm->mgmt_timer, in csio_mgmt_tmo_handler()
4140 spin_unlock_irq(&mgmtm->hw->lock); in csio_mgmt_tmo_handler()
4146 struct csio_hw *hw = mgmtm->hw; in csio_mgmtm_cleanup()
4153 while ((!list_empty(&mgmtm->active_q)) && count--) { in csio_mgmtm_cleanup()
4154 spin_unlock_irq(&hw->lock); in csio_mgmtm_cleanup()
4156 spin_lock_irq(&hw->lock); in csio_mgmtm_cleanup()
4160 list_for_each(tmp, &mgmtm->active_q) { in csio_mgmtm_cleanup()
4163 list_del_init(&io_req->sm.sm_list); in csio_mgmtm_cleanup()
4164 mgmtm->stats.n_active--; in csio_mgmtm_cleanup()
4165 if (io_req->io_cbfn) { in csio_mgmtm_cleanup()
4167 io_req->wr_status = -ETIMEDOUT; in csio_mgmtm_cleanup()
4168 io_req->io_cbfn(mgmtm->hw, io_req); in csio_mgmtm_cleanup()
4174 * csio_mgmt_init - Mgmt module init entry point
4175 * @mgmtsm - mgmt module
4176 * @hw - HW module
4184 * Returns: 0 - on success
4185 * -ENOMEM - on error.
4190 timer_setup(&mgmtm->mgmt_timer, csio_mgmt_tmo_handler, 0); in csio_mgmtm_init()
4192 INIT_LIST_HEAD(&mgmtm->active_q); in csio_mgmtm_init()
4193 INIT_LIST_HEAD(&mgmtm->cbfn_q); in csio_mgmtm_init()
4195 mgmtm->hw = hw; in csio_mgmtm_init()
4196 /*mgmtm->iq_idx = hw->fwevt_iq_idx;*/ in csio_mgmtm_init()
4202 * csio_mgmtm_exit - MGMT module exit entry point
4203 * @mgmtsm - mgmt module
4213 del_timer_sync(&mgmtm->mgmt_timer); in csio_mgmtm_exit()
4218 * csio_hw_start - Kicks off the HW State machine
4228 spin_lock_irq(&hw->lock); in csio_hw_start()
4229 csio_post_event(&hw->sm, CSIO_HWE_CFG); in csio_hw_start()
4230 spin_unlock_irq(&hw->lock); in csio_hw_start()
4235 return -EINVAL; in csio_hw_start()
4237 return -ENODEV; in csio_hw_start()
4243 csio_post_event(&hw->sm, CSIO_HWE_PCI_REMOVE); in csio_hw_stop()
4248 return -EINVAL; in csio_hw_stop()
4255 * csio_hw_reset - Reset the hardware
4264 return -EPERM; in csio_hw_reset()
4266 if (hw->rst_retries >= CSIO_MAX_RESET_RETRIES) { in csio_hw_reset()
4268 return -EINVAL; in csio_hw_reset()
4271 hw->rst_retries++; in csio_hw_reset()
4272 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET); in csio_hw_reset()
4275 hw->rst_retries = 0; in csio_hw_reset()
4276 hw->stats.n_reset_start = jiffies_to_msecs(jiffies); in csio_hw_reset()
4279 return -EINVAL; in csio_hw_reset()
4283 * csio_hw_get_device_id - Caches the Adapter's vendor & device id.
4294 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, in csio_hw_get_device_id()
4295 &hw->params.pci.vendor_id); in csio_hw_get_device_id()
4296 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, in csio_hw_get_device_id()
4297 &hw->params.pci.device_id); in csio_hw_get_device_id()
4300 hw->chip_id = (hw->params.pci.device_id & CSIO_HW_CHIP_MASK); in csio_hw_get_device_id()
4305 * csio_hw_set_description - Set the model, description of the hw.
4320 memcpy(hw->hw_ver, in csio_hw_set_description()
4322 memcpy(hw->model_desc, in csio_hw_set_description()
4327 memcpy(hw->model_desc, tempName, 32); in csio_hw_set_description()
4333 * csio_hw_init - Initialize HW module.
4341 int rv = -EINVAL; in csio_hw_init()
4346 INIT_LIST_HEAD(&hw->sm.sm_list); in csio_hw_init()
4347 csio_init_state(&hw->sm, csio_hws_uninit); in csio_hw_init()
4348 spin_lock_init(&hw->lock); in csio_hw_init()
4349 INIT_LIST_HEAD(&hw->sln_head); in csio_hw_init()
4354 strcpy(hw->name, CSIO_HW_NAME); in csio_hw_init()
4357 hw->chip_ops = &t5_ops; in csio_hw_init()
4361 ven_id = hw->params.pci.vendor_id; in csio_hw_init()
4362 dev_id = hw->params.pci.device_id; in csio_hw_init()
4367 hw->params.log_level = (uint32_t) csio_dbg_level; in csio_hw_init()
4369 csio_set_fwevt_intr_idx(hw, -1); in csio_hw_init()
4370 csio_set_nondata_intr_idx(hw, -1); in csio_hw_init()
4387 /* Pre-allocate evtq and initialize them */ in csio_hw_init()
4388 INIT_LIST_HEAD(&hw->evt_active_q); in csio_hw_init()
4389 INIT_LIST_HEAD(&hw->evt_free_q); in csio_hw_init()
4394 rv = -ENOMEM; in csio_hw_init()
4399 list_add_tail(&evt_entry->list, &hw->evt_free_q); in csio_hw_init()
4403 hw->dev_num = dev_num; in csio_hw_init()
4422 * csio_hw_exit - Un-initialize HW module.