322 		writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/  in arcmsr_remap_pciregion()
335 		writel(0, &acb->pmuF->host_int_status); /* clear interrupt */  in arcmsr_remap_pciregion()
484 			writel(0, &phbcmu->host_int_status); /*clear interrupt*/  in arcmsr_hbaE_wait_msgint_ready()
630 	reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);  in arcmsr_hbaD_assign_regAddr()
1240 		writel(0, &acb->pmuE->host_int_status);  in arcmsr_resume()
1247 		writel(0, &acb->pmuF->host_int_status);  in arcmsr_resume()
1576 …while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOuts…  in arcmsr_done4abort_postqueue()
2518 		writel(0, &reg->host_int_status); /* clear interrupt */  in arcmsr_hbaE_doorbell_isr()
2775 	writel(0, &reg->host_int_status);  in arcmsr_hbaE_message_isr()
2841 	host_interrupt_status = readl(&phbcmu->host_int_status) &  in arcmsr_hbaC_handle_isr()
2852 		host_interrupt_status = readl(&phbcmu->host_int_status);  in arcmsr_hbaC_handle_isr()
2863 	host_interrupt_status = readl(pmu->host_int_status) &  in arcmsr_hbaD_handle_isr()
2876 		host_interrupt_status = readl(pmu->host_int_status);  in arcmsr_hbaD_handle_isr()
2888 	host_interrupt_status = readl(&pmu->host_int_status) &  in arcmsr_hbaE_handle_isr()
2902 		host_interrupt_status = readl(&pmu->host_int_status);  in arcmsr_hbaE_handle_isr()
2913 	host_interrupt_status = readl(&phbcmu->host_int_status) &  in arcmsr_hbaF_handle_isr()
2927 		host_interrupt_status = readl(&phbcmu->host_int_status);  in arcmsr_hbaF_handle_isr()
3718 		if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {  in arcmsr_hbaC_polling_ccbdone()
4486 		writel(0, &reg->host_int_status); /*clear interrupt*/  in arcmsr_clear_doorbell_queue_buffer()
4494 				writel(0, &reg->host_int_status); /*clear interrupt*/  in arcmsr_clear_doorbell_queue_buffer()