Lines Matching +full:006 +full:- +full:0 +full:- +full:0007
9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
12 ** E-mail: support@areca.com.tw
53 #define ARCMSR_DRIVER_VERSION "v1.51.00.14-20230915"
69 #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
73 #define PCI_DEVICE_ID_ARECA_1880 0x1880
76 #define PCI_DEVICE_ID_ARECA_1214 0x1214
79 #define PCI_DEVICE_ID_ARECA_1203 0x1203
82 #define PCI_DEVICE_ID_ARECA_1883 0x1883
85 #define PCI_DEVICE_ID_ARECA_1884 0x1884
87 #define PCI_DEVICE_ID_ARECA_1886_0 0x1886
88 #define PCI_DEVICE_ID_ARECA_1886 0x188A
97 #define ARC_SUCCESS 0
105 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
132 #define ARCMSR_MESSAGE_FAIL 0x0001
134 #define ARECA_SATA_RAID 0x90000000
136 #define FUNCTION_READ_RQBUFFER 0x0801
137 #define FUNCTION_WRITE_WQBUFFER 0x0802
138 #define FUNCTION_CLEAR_RQBUFFER 0x0803
139 #define FUNCTION_CLEAR_WQBUFFER 0x0804
140 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
141 #define FUNCTION_RETURN_CODE_3F 0x0806
142 #define FUNCTION_SAY_HELLO 0x0807
143 #define FUNCTION_SAY_GOODBYE 0x0808
144 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
145 #define FUNCTION_GET_FIRMWARE_STATUS 0x080A
146 #define FUNCTION_HARDWARE_RESET 0x080B
167 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
168 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
169 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
170 #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
177 #define IS_SG64_ADDR 0x01000000 /* bit24 */
206 uint32_t signature; /*0, 00-03*/
207 uint32_t request_len; /*1, 04-07*/
208 uint32_t numbers_queue; /*2, 08-11*/
209 uint32_t sdram_size; /*3, 12-15*/
210 uint32_t ide_channels; /*4, 16-19*/
211 char vendor[40]; /*5, 20-59*/
212 char model[8]; /*15, 60-67*/
213 char firmware_ver[16]; /*17, 68-83*/
214 char device_map[16]; /*21, 84-99*/
215 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
216 uint8_t cfgSerial[16]; /*26,104-119*/
217 uint32_t cfgPicStatus; /*30,120-123*/
220 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
221 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
223 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
224 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
225 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
226 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
227 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
228 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
229 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
230 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
231 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
233 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
234 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
235 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
236 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
238 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
239 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
240 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
241 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
242 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
244 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
245 /* ARC-1680 Bus Reset*/
246 #define ARCMSR_ARC1680_BUS_RESET 0x00000003
247 /* ARC-1880 Bus Reset*/
248 #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
249 #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
258 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400
259 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
261 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408
262 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
264 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870
265 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
267 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878
268 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
271 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
273 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
274 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
275 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
277 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
278 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
279 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
281 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
283 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
285 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
287 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
289 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
291 #define ARCMSR_MESSAGE_START_BGRB 0x00060008
292 #define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
293 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
294 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
295 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
297 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
299 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
301 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
302 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
303 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
304 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
308 #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
310 #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
312 #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
314 #define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x)
315 #define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x)
324 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes t…
325 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Door…
326 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List F…
327 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
329 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
334 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
336 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
341 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
347 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
353 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
354 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
355 /*inbound message 0 ready*/
356 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
358 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
359 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
361 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
362 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
364 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
365 /*outbound message 0 ready*/
366 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
368 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
370 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
376 #define ARCMSR_ARC1214_CHIP_ID 0x00004
377 #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
378 #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
379 #define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
380 #define ARCMSR_ARC1214_RESET_REQUEST 0x00108
381 #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
382 #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
383 #define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
384 #define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
385 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
386 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
387 #define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
388 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
389 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
390 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
391 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
392 #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
393 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
394 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
395 #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
396 #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
397 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
398 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
399 #define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
400 #define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
401 #define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
403 #define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
404 #define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
406 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
407 #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
409 #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
410 #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
411 /*inbound message 0 ready*/
412 #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
414 #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
415 /*outbound message 0 ready*/
416 #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
419 #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
420 #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
426 #define ARCMSR_SIGNATURE_1884 0x188417D3
428 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
429 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
430 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
432 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
433 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
434 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
436 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000
438 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
439 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
440 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009
442 /* ARC-1884 doorbell sync */
443 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
444 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
445 #define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080
452 #define ARCMSR_SIGNATURE_1886 0x188617D3
454 /* ARC-1886 doorbell sync */
455 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
456 //set host rw buffer physical address at inbound message 0, 1 (low,high)
457 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
458 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
459 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
463 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
475 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
476 #define ARCMSR_CDB_FLAG_BIOS 0x02
477 #define ARCMSR_CDB_FLAG_WRITE 0x04
478 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
479 #define ARCMSR_CDB_FLAG_HEADQ 0x08
480 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
487 #define ARCMSR_DEV_CHECK_CONDITION 0x02
488 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
489 #define ARCMSR_DEV_ABORTED 0xF1
490 #define ARCMSR_DEV_INIT_FAIL 0xF2
523 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
524 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
525 uint32_t reserved5[32]; /*0E80 0EFF 32*/
526 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
527 uint32_t reserved6[32]; /*0F80 0FFF 32*/
551 uint32_t slave_error_attribute; /*0004 0007*/
576 uint32_t outbound_free_list_index; /*0068 006B*/
577 uint32_t outbound_post_list_index; /*006C 006F*/
642 u32 __iomem *chip_id; /* 0x00004 */
643 u32 __iomem *cpu_mem_config; /* 0x00008 */
644 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
645 u32 __iomem *sample_at_reset; /* 0x00100 */
646 u32 __iomem *reset_request; /* 0x00108 */
647 u32 __iomem *host_int_status; /* 0x00200 */
648 u32 __iomem *pcief0_int_enable; /* 0x0020C */
649 u32 __iomem *inbound_msgaddr0; /* 0x00400 */
650 u32 __iomem *inbound_msgaddr1; /* 0x00404 */
651 u32 __iomem *outbound_msgaddr0; /* 0x00420 */
652 u32 __iomem *outbound_msgaddr1; /* 0x00424 */
653 u32 __iomem *inbound_doorbell; /* 0x00460 */
654 u32 __iomem *outbound_doorbell; /* 0x00480 */
655 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
656 u32 __iomem *inboundlist_base_low; /* 0x01000 */
657 u32 __iomem *inboundlist_base_high; /* 0x01004 */
658 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
659 u32 __iomem *outboundlist_base_low; /* 0x01060 */
660 u32 __iomem *outboundlist_base_high; /* 0x01064 */
661 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
662 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
663 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
664 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
665 u32 __iomem *message_wbuffer; /* 0x2000 */
666 u32 __iomem *message_rbuffer; /* 0x2100 */
667 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
676 uint32_t write_sequence_3xxx; /*0004 0007*/
701 uint32_t reply_post_producer_index; /*0068 006B*/
702 uint32_t reply_post_consumer_index; /*006C 006F*/
752 uint32_t write_sequence_3xxx; /*0004 0007*/
777 uint32_t reply_post_producer_index; /*0068 006B*/
778 uint32_t reply_post_consumer_index; /*006C 006F*/
822 uint16_t cmdLMID; // reserved (0)
823 uint16_t cmdFlag2; // reserved (0)
830 uint32_t hrbRes[2]; // reserved, must be set to 0
850 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
851 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
852 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
853 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
854 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
855 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */
882 //0x000 - COMPORT_IN (Host sent to ROC)
884 //0x100 - COMPORT_OUT (ROC sent to Host)
886 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
890 #define ACB_F_SCSISTOPADAPTER 0x0001
891 #define ACB_F_MSG_STOP_BGRB 0x0002
893 #define ACB_F_MSG_START_BGRB 0x0004
895 #define ACB_F_IOPDATA_OVERFLOW 0x0008
897 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
899 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
901 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
902 #define ACB_F_BUS_RESET 0x0080
904 #define ACB_F_IOP_INITED 0x0100
906 #define ACB_F_ABORT 0x0200
907 #define ACB_F_FIRMWARE_TRAP 0x0400
908 #define ACB_F_ADAPTER_REMOVED 0x0800
909 #define ACB_F_MSG_GET_CONFIG 0x1000
940 #define ARECA_RAID_GONE 0x55
941 #define ARECA_RAID_GOOD 0xaa
952 char device_map[20]; /*21,84-99*/
957 #define FW_NORMAL 0x0000
958 #define FW_BOG 0x0001
959 #define FW_DEADLOCK 0x0010
991 #define CCB_FLAG_READ 0x0000
992 #define CCB_FLAG_WRITE 0x0001
993 #define CCB_FLAG_ERROR 0x0002
994 #define CCB_FLAG_FLUSHCACHE 0x0004
995 #define CCB_FLAG_MASTER_ABORTED 0x0008
997 #define ARCMSR_CCB_DONE 0x0000
998 #define ARCMSR_CCB_START 0x55AA
999 #define ARCMSR_CCB_ABORTED 0xAA55
1000 #define ARCMSR_CCB_ILLEGAL 0xFFFF
1020 #define SCSI_SENSE_CURRENT_ERRORS 0x70
1021 #define SCSI_SENSE_DEFERRED_ERRORS 0x71
1039 ** Outbound Interrupt Status Register - OISR
1042 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
1043 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
1044 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
1045 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
1046 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
1047 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
1056 ** Outbound Interrupt Mask Register - OIMR
1059 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
1060 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
1061 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
1062 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
1063 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
1064 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
1065 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F