Lines Matching +full:0 +full:xffff
35 static u16 first_scb_site_no = 0xFFFF;
44 * Return 0 on success, negative on failure.
53 return 0; in asd_pause_cseq()
59 return 0; in asd_pause_cseq()
61 } while (--count > 0); in asd_pause_cseq()
71 * Return 0 on success, negative on error.
80 return 0; in asd_unpause_cseq()
86 return 0; in asd_unpause_cseq()
88 } while (--count > 0); in asd_unpause_cseq()
99 * Return 0 on success, negative on error.
108 return 0; in asd_seq_pause_lseq()
114 return 0; in asd_seq_pause_lseq()
116 } while (--count > 0); in asd_seq_pause_lseq()
127 * Return 0 on success, negative on failure.
132 int err = 0; in asd_pause_lseq()
148 * Return 0 on success, negative on error.
157 return 0; in asd_seq_unpause_lseq()
163 return 0; in asd_seq_unpause_lseq()
165 } while (--count > 0); in asd_seq_unpause_lseq()
168 return 0; in asd_seq_unpause_lseq()
181 for (i = 0; i < size; i += 4, prog++, addr += 4) { in asd_verify_cseq()
186 "read:0x%x, wanted:0x%x\n", in asd_verify_cseq()
193 return 0; in asd_verify_cseq()
216 for (page = 0; page < pages; page++) { in asd_verify_lseq()
221 for (i = 0; size > 0 && i < LSEQ_CODEPAGE_SIZE; in asd_verify_lseq()
237 return 0; in asd_verify_lseq()
245 * @lseq_mask: if 0, verify CSEQ microcode, else mask of LSEQs of interest
247 * Return 0 if microcode is correct, negative on mismatch.
252 if (lseq_mask == 0) in asd_verify_seq()
264 return 0; in asd_verify_seq()
278 int err = 0; in asd_download_seq()
286 asd_pause_lseq(asd_ha, 0xFF); in asd_download_seq()
290 asd_write_reg_dword(asd_ha, COMSTATEN, 0); in asd_download_seq()
304 for (page = 0; page < pages; page++) { in asd_download_seq()
312 reg = !page ? RESETOVLYDMA : 0; in asd_download_seq()
318 for (i = PAUSE_TRIES*100; i > 0; i--) { in asd_download_seq()
345 u32 reg = 0; in asd_download_seq()
354 asd_pause_lseq(asd_ha, 0xFF); in asd_download_seq()
365 for (i = 0; i < size; i += 4, prog++) in asd_download_seq()
392 err = asd_download_seq(asd_ha, cseq_code, cseq_code_size, 0); in asd_seq_download_seqs()
431 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_HEAD, 0xFFFF); in asd_init_cseq_mip()
432 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_TAIL, 0xFFFF); in asd_init_cseq_mip()
433 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_HEAD, 0xFFFF); in asd_init_cseq_mip()
434 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_TAIL, 0xFFFF); in asd_init_cseq_mip()
435 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_HEAD, 0xFFFF); in asd_init_cseq_mip()
436 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_TAIL, 0xFFFF); in asd_init_cseq_mip()
437 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_HEAD, 0xFFFF); in asd_init_cseq_mip()
438 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_TAIL, 0xFFFF); in asd_init_cseq_mip()
439 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_HEAD, 0xFFFF); in asd_init_cseq_mip()
440 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_TAIL, 0xFFFF); in asd_init_cseq_mip()
441 asd_write_reg_word(asd_ha, CSEQ_REG0, 0); in asd_init_cseq_mip()
442 asd_write_reg_word(asd_ha, CSEQ_REG1, 0); in asd_init_cseq_mip()
443 asd_write_reg_dword(asd_ha, CSEQ_REG2, 0); in asd_init_cseq_mip()
444 asd_write_reg_byte(asd_ha, CSEQ_LINK_CTL_Q_MAP, 0); in asd_init_cseq_mip()
450 asd_write_reg_word(asd_ha, CSEQ_FREE_LIST_HACK_COUNT, 0); in asd_init_cseq_mip()
453 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE, 0); in asd_init_cseq_mip()
454 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE+4, 0); in asd_init_cseq_mip()
455 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT, 0); in asd_init_cseq_mip()
456 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT+4, 0); in asd_init_cseq_mip()
457 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_HEAD, 0xFFFF); in asd_init_cseq_mip()
458 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_TAIL, 0xFFFF); in asd_init_cseq_mip()
459 asd_write_reg_word(asd_ha, CSEQ_NEED_EST_NEXUS_SCB, 0); in asd_init_cseq_mip()
460 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_HEAD, 0); in asd_init_cseq_mip()
461 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_TAIL, 0); in asd_init_cseq_mip()
462 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_SCB_OFFSET, 0); in asd_init_cseq_mip()
465 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR0, 0); in asd_init_cseq_mip()
466 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR1, 0); in asd_init_cseq_mip()
467 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_SCBPTR, 0); in asd_init_cseq_mip()
468 asd_write_reg_byte(asd_ha, CSEQ_INT_ROUT_MODE, 0); in asd_init_cseq_mip()
469 asd_write_reg_byte(asd_ha, CSEQ_ISR_SCRATCH_FLAGS, 0); in asd_init_cseq_mip()
470 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_SINDEX, 0); in asd_init_cseq_mip()
471 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_DINDEX, 0); in asd_init_cseq_mip()
472 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_HEAD, 0xFFFF); in asd_init_cseq_mip()
473 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_TAIL, 0xFFFF); in asd_init_cseq_mip()
484 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_HEAD, 0xFFFF); in asd_init_cseq_mip()
485 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_TAIL, 0xFFFF); in asd_init_cseq_mip()
488 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE, 0); in asd_init_cseq_mip()
489 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE+4, 0); in asd_init_cseq_mip()
490 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT, 0); in asd_init_cseq_mip()
491 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT+4, 0); in asd_init_cseq_mip()
492 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_HEAD, 0xFFFF); in asd_init_cseq_mip()
493 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_TAIL, 0xFFFF); in asd_init_cseq_mip()
494 asd_write_reg_word(asd_ha, CSEQ_NEED_EMPTY_SCB, 0); in asd_init_cseq_mip()
495 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_HEAD, 0); in asd_init_cseq_mip()
496 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_TAIL, 0); in asd_init_cseq_mip()
497 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_SCB_OFFSET, 0); in asd_init_cseq_mip()
498 asd_write_reg_word(asd_ha, CSEQ_PRIMITIVE_DATA, 0); in asd_init_cseq_mip()
499 asd_write_reg_dword(asd_ha, CSEQ_TIMEOUT_CONST, 0); in asd_init_cseq_mip()
513 /* CSEQ Mode dependent, modes 0-7, page 0 setup. */ in asd_init_cseq_mdp()
514 for (i = 0; i < 8; i++) { in asd_init_cseq_mdp()
515 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SINDEX, 0); in asd_init_cseq_mdp()
516 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCBPTR, 0); in asd_init_cseq_mdp()
517 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_HEAD, 0xFFFF); in asd_init_cseq_mdp()
518 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_TAIL, 0xFFFF); in asd_init_cseq_mdp()
519 asd_write_reg_byte(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCRPAGE, 0); in asd_init_cseq_mdp()
522 /* CSEQ Mode dependent, mode 0-7, page 1 and 2 shall be ignored. */ in asd_init_cseq_mdp()
524 /* CSEQ Mode dependent, mode 8, page 0 setup. */ in asd_init_cseq_mdp()
525 asd_write_reg_word(asd_ha, CSEQ_RET_ADDR, 0xFFFF); in asd_init_cseq_mdp()
526 asd_write_reg_word(asd_ha, CSEQ_RET_SCBPTR, 0); in asd_init_cseq_mdp()
527 asd_write_reg_word(asd_ha, CSEQ_SAVE_SCBPTR, 0); in asd_init_cseq_mdp()
528 asd_write_reg_word(asd_ha, CSEQ_EMPTY_TRANS_CTX, 0); in asd_init_cseq_mdp()
529 asd_write_reg_word(asd_ha, CSEQ_RESP_LEN, 0); in asd_init_cseq_mdp()
530 asd_write_reg_word(asd_ha, CSEQ_TMF_SCBPTR, 0); in asd_init_cseq_mdp()
531 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_PREV_SCB, 0); in asd_init_cseq_mdp()
532 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_HEAD, 0); in asd_init_cseq_mdp()
533 asd_write_reg_word(asd_ha, CSEQ_CLEAR_LU_HEAD, 0); in asd_init_cseq_mdp()
534 asd_write_reg_byte(asd_ha, CSEQ_TMF_OPCODE, 0); in asd_init_cseq_mdp()
535 asd_write_reg_byte(asd_ha, CSEQ_SCRATCH_FLAGS, 0); in asd_init_cseq_mdp()
536 asd_write_reg_word(asd_ha, CSEQ_HSB_SITE, 0); in asd_init_cseq_mdp()
543 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR, 0); in asd_init_cseq_mdp()
544 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR + 4, 0); in asd_init_cseq_mdp()
545 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK, 0); in asd_init_cseq_mdp()
546 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK + 4, 0); in asd_init_cseq_mdp()
552 ASD_DPRINTK("First SCB dma_handle: 0x%llx\n", in asd_init_cseq_mdp()
583 * asd_init_lseq_mip -- initialize LSEQ Mode independent pages 0-3
591 /* LSEQ Mode independent page 0 setup. */ in asd_init_lseq_mip()
592 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_HEAD(lseq), 0xFFFF); in asd_init_lseq_mip()
593 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_TAIL(lseq), 0xFFFF); in asd_init_lseq_mip()
597 asd_write_reg_dword(asd_ha, LmSEQ_CONNECTION_STATE(lseq),0x08000000); in asd_init_lseq_mip()
598 asd_write_reg_word(asd_ha, LmSEQ_CONCTL(lseq), 0); in asd_init_lseq_mip()
599 asd_write_reg_byte(asd_ha, LmSEQ_CONSTAT(lseq), 0); in asd_init_lseq_mip()
600 asd_write_reg_byte(asd_ha, LmSEQ_CONNECTION_MODES(lseq), 0); in asd_init_lseq_mip()
601 asd_write_reg_word(asd_ha, LmSEQ_REG1_ISR(lseq), 0); in asd_init_lseq_mip()
602 asd_write_reg_word(asd_ha, LmSEQ_REG2_ISR(lseq), 0); in asd_init_lseq_mip()
603 asd_write_reg_word(asd_ha, LmSEQ_REG3_ISR(lseq), 0); in asd_init_lseq_mip()
604 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq), 0); in asd_init_lseq_mip()
605 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq)+4, 0); in asd_init_lseq_mip()
608 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR0(lseq), 0xFFFF); in asd_init_lseq_mip()
609 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR1(lseq), 0xFFFF); in asd_init_lseq_mip()
610 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR2(lseq), 0xFFFF); in asd_init_lseq_mip()
611 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR3(lseq), 0xFFFF); in asd_init_lseq_mip()
612 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE0(lseq), 0); in asd_init_lseq_mip()
613 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE1(lseq), 0); in asd_init_lseq_mip()
614 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE2(lseq), 0); in asd_init_lseq_mip()
615 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE3(lseq), 0); in asd_init_lseq_mip()
616 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_HEAD(lseq), 0); in asd_init_lseq_mip()
617 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_TAIL(lseq), 0); in asd_init_lseq_mip()
618 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_BUF_AVAIL(lseq), 0); in asd_init_lseq_mip()
619 asd_write_reg_dword(asd_ha, LmSEQ_TIMEOUT_CONST(lseq), 0); in asd_init_lseq_mip()
620 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_SINDEX(lseq), 0); in asd_init_lseq_mip()
621 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_DINDEX(lseq), 0); in asd_init_lseq_mip()
624 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR0(lseq), 0xFFFF); in asd_init_lseq_mip()
625 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR1(lseq), 0xFFFF); in asd_init_lseq_mip()
626 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR2(lseq), 0xFFFF); in asd_init_lseq_mip()
627 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR3(lseq), 0xFFFF); in asd_init_lseq_mip()
628 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD0(lseq), 0); in asd_init_lseq_mip()
629 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD1(lseq), 0); in asd_init_lseq_mip()
630 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD2(lseq), 0); in asd_init_lseq_mip()
631 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD3(lseq), 0); in asd_init_lseq_mip()
632 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_HEAD(lseq), 0); in asd_init_lseq_mip()
633 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_TAIL(lseq), 0); in asd_init_lseq_mip()
634 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_BUFS_AVAIL(lseq), 0); in asd_init_lseq_mip()
635 for (i = 0; i < 12; i += 4) in asd_init_lseq_mip()
636 asd_write_reg_dword(asd_ha, LmSEQ_ATA_SCR_REGS(lseq) + i, 0); in asd_init_lseq_mip()
649 * always 0. */ in asd_init_lseq_mip()
680 0xFFFF, /* mode 0 */ in asd_init_lseq_mdp()
681 0xFFFF, /* mode 1 */ in asd_init_lseq_mdp()
683 0, in asd_init_lseq_mdp()
684 0xFFFF, /* mode 4/5 */ in asd_init_lseq_mdp()
685 0xFFFF, /* mode 4/5 */ in asd_init_lseq_mdp()
689 * Mode 0,1,2 and 4/5 have common field on page 0 for the first in asd_init_lseq_mdp()
692 for (i = 0; i < 3; i++) { in asd_init_lseq_mdp()
696 asd_write_reg_word(asd_ha, LmSEQ_REG0_MODE(lseq)+moffs, 0); in asd_init_lseq_mdp()
697 asd_write_reg_word(asd_ha, LmSEQ_MODE_FLAGS(lseq)+moffs, 0); in asd_init_lseq_mdp()
698 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR2(lseq)+moffs,0xFFFF); in asd_init_lseq_mdp()
699 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR1(lseq)+moffs,0xFFFF); in asd_init_lseq_mdp()
700 asd_write_reg_byte(asd_ha, LmSEQ_OPCODE_TO_CSEQ(lseq)+moffs,0); in asd_init_lseq_mdp()
701 asd_write_reg_word(asd_ha, LmSEQ_DATA_TO_CSEQ(lseq)+moffs,0); in asd_init_lseq_mdp()
704 * Mode 5 page 0 overlaps the same scratch page with Mode 0 page 3. in asd_init_lseq_mdp()
710 LmSEQ_REG0_MODE(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0); in asd_init_lseq_mdp()
712 LmSEQ_MODE_FLAGS(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0); in asd_init_lseq_mdp()
714 LmSEQ_RET_ADDR2(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF); in asd_init_lseq_mdp()
716 LmSEQ_RET_ADDR1(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF); in asd_init_lseq_mdp()
718 LmSEQ_OPCODE_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0); in asd_init_lseq_mdp()
720 LmSEQ_DATA_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0); in asd_init_lseq_mdp()
722 /* LSEQ Mode dependent 0, page 0 setup. */ in asd_init_lseq_mdp()
725 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_TRANS_CTX(lseq), 0); in asd_init_lseq_mdp()
726 asd_write_reg_word(asd_ha, LmSEQ_RESP_LEN(lseq), 0); in asd_init_lseq_mdp()
730 (u16) ((LmM0INTEN_MASK & 0xFFFF0000) >> 16)); in asd_init_lseq_mdp()
732 (u16) LmM0INTEN_MASK & 0xFFFF); in asd_init_lseq_mdp()
733 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_FRM_LEN(lseq), 0); in asd_init_lseq_mdp()
734 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_PROTOCOL(lseq), 0); in asd_init_lseq_mdp()
735 asd_write_reg_byte(asd_ha, LmSEQ_RESP_STATUS(lseq), 0); in asd_init_lseq_mdp()
736 asd_write_reg_byte(asd_ha, LmSEQ_LAST_LOADED_SGE(lseq), 0); in asd_init_lseq_mdp()
737 asd_write_reg_word(asd_ha, LmSEQ_SAVE_SCBPTR(lseq), 0); in asd_init_lseq_mdp()
739 /* LSEQ mode dependent, mode 1, page 0 setup. */ in asd_init_lseq_mdp()
740 asd_write_reg_word(asd_ha, LmSEQ_Q_XMIT_HEAD(lseq), 0xFFFF); in asd_init_lseq_mdp()
741 asd_write_reg_word(asd_ha, LmSEQ_M1_EMPTY_TRANS_CTX(lseq), 0); in asd_init_lseq_mdp()
742 asd_write_reg_word(asd_ha, LmSEQ_INI_CONN_TAG(lseq), 0); in asd_init_lseq_mdp()
743 asd_write_reg_byte(asd_ha, LmSEQ_FAILED_OPEN_STATUS(lseq), 0); in asd_init_lseq_mdp()
744 asd_write_reg_byte(asd_ha, LmSEQ_XMIT_REQUEST_TYPE(lseq), 0); in asd_init_lseq_mdp()
745 asd_write_reg_byte(asd_ha, LmSEQ_M1_RESP_STATUS(lseq), 0); in asd_init_lseq_mdp()
746 asd_write_reg_byte(asd_ha, LmSEQ_M1_LAST_LOADED_SGE(lseq), 0); in asd_init_lseq_mdp()
747 asd_write_reg_word(asd_ha, LmSEQ_M1_SAVE_SCBPTR(lseq), 0); in asd_init_lseq_mdp()
749 /* LSEQ Mode dependent mode 2, page 0 setup */ in asd_init_lseq_mdp()
750 asd_write_reg_word(asd_ha, LmSEQ_PORT_COUNTER(lseq), 0); in asd_init_lseq_mdp()
751 asd_write_reg_word(asd_ha, LmSEQ_PM_TABLE_PTR(lseq), 0); in asd_init_lseq_mdp()
752 asd_write_reg_word(asd_ha, LmSEQ_SATA_INTERLOCK_TMR_SAVE(lseq), 0); in asd_init_lseq_mdp()
753 asd_write_reg_word(asd_ha, LmSEQ_IP_BITL(lseq), 0); in asd_init_lseq_mdp()
754 asd_write_reg_word(asd_ha, LmSEQ_COPY_SMP_CONN_TAG(lseq), 0); in asd_init_lseq_mdp()
755 asd_write_reg_byte(asd_ha, LmSEQ_P0M2_OFFS1AH(lseq), 0); in asd_init_lseq_mdp()
757 /* LSEQ Mode dependent, mode 4/5, page 0 setup. */ in asd_init_lseq_mdp()
758 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_STATUS(lseq), 0); in asd_init_lseq_mdp()
759 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_MODE(lseq), 0); in asd_init_lseq_mdp()
760 asd_write_reg_word(asd_ha, LmSEQ_Q_LINK_HEAD(lseq), 0xFFFF); in asd_init_lseq_mdp()
761 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_ERR(lseq), 0); in asd_init_lseq_mdp()
762 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_SIGNALS(lseq), 0); in asd_init_lseq_mdp()
763 asd_write_reg_byte(asd_ha, LmSEQ_SAS_RESET_MODE(lseq), 0); in asd_init_lseq_mdp()
764 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RESET_RETRY_COUNT(lseq), 0); in asd_init_lseq_mdp()
765 asd_write_reg_byte(asd_ha, LmSEQ_NUM_LINK_RESET_RETRIES(lseq), 0); in asd_init_lseq_mdp()
766 asd_write_reg_word(asd_ha, LmSEQ_OOB_INT_ENABLES(lseq), 0); in asd_init_lseq_mdp()
779 /* LSEQ Mode dependent, mode 0 and 1, page 1 setup. */ in asd_init_lseq_mdp()
780 for (i = 0; i < 2; i++) { in asd_init_lseq_mdp()
782 /* Start from Page 1 of Mode 0 and 1. */ in asd_init_lseq_mdp()
784 /* All the fields of page 1 can be initialized to 0. */ in asd_init_lseq_mdp()
785 for (j = 0; j < LSEQ_PAGE_SIZE; j += 4) in asd_init_lseq_mdp()
786 asd_write_reg_dword(asd_ha, LmSCRATCH(lseq)+moffs+j,0); in asd_init_lseq_mdp()
790 asd_write_reg_dword(asd_ha, LmSEQ_INVALID_DWORD_COUNT(lseq), 0); in asd_init_lseq_mdp()
791 asd_write_reg_dword(asd_ha, LmSEQ_DISPARITY_ERROR_COUNT(lseq), 0); in asd_init_lseq_mdp()
792 asd_write_reg_dword(asd_ha, LmSEQ_LOSS_OF_SYNC_COUNT(lseq), 0); in asd_init_lseq_mdp()
795 for (i = 0; i < LSEQ_PAGE_SIZE; i+=4) in asd_init_lseq_mdp()
796 asd_write_reg_dword(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq)+i, 0); in asd_init_lseq_mdp()
797 asd_write_reg_byte(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq), 0xFF); in asd_init_lseq_mdp()
798 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq), 0xFF); in asd_init_lseq_mdp()
799 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+1,0xFF); in asd_init_lseq_mdp()
800 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+2,0xFF); in asd_init_lseq_mdp()
801 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq), 0xFF); in asd_init_lseq_mdp()
802 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+1, 0xFF); in asd_init_lseq_mdp()
803 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+2, 0xFF); in asd_init_lseq_mdp()
804 asd_write_reg_dword(asd_ha, LmSEQ_DATA_OFFSET(lseq), 0xFFFFFFFF); in asd_init_lseq_mdp()
806 /* LSEQ Mode dependent, mode 0, page 2 setup. */ in asd_init_lseq_mdp()
807 asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
808 asd_write_reg_byte(asd_ha, LmSEQ_DEVICE_BITS(lseq), 0); in asd_init_lseq_mdp()
809 asd_write_reg_word(asd_ha, LmSEQ_SDB_DDB(lseq), 0); in asd_init_lseq_mdp()
810 asd_write_reg_byte(asd_ha, LmSEQ_SDB_NUM_TAGS(lseq), 0); in asd_init_lseq_mdp()
811 asd_write_reg_byte(asd_ha, LmSEQ_SDB_CURR_TAG(lseq), 0); in asd_init_lseq_mdp()
814 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq), 0); in asd_init_lseq_mdp()
815 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq)+4, 0); in asd_init_lseq_mdp()
816 asd_write_reg_dword(asd_ha, LmSEQ_OPEN_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
817 asd_write_reg_dword(asd_ha, LmSEQ_SRST_AS_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
818 asd_write_reg_dword(asd_ha, LmSEQ_LAST_LOADED_SG_EL(lseq), 0); in asd_init_lseq_mdp()
822 * i.e. always 0. */ in asd_init_lseq_mdp()
823 asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(lseq),0); in asd_init_lseq_mdp()
824 asd_write_reg_dword(asd_ha, LmSEQ_CLOSE_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
825 asd_write_reg_dword(asd_ha, LmSEQ_BREAK_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
826 asd_write_reg_dword(asd_ha, LmSEQ_DWS_RESET_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
827 asd_write_reg_dword(asd_ha,LmSEQ_SATA_INTERLOCK_TIMER_TERM_TS(lseq),0); in asd_init_lseq_mdp()
828 asd_write_reg_dword(asd_ha, LmSEQ_MCTL_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
831 asd_write_reg_dword(asd_ha, LmSEQ_COMINIT_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
832 asd_write_reg_dword(asd_ha, LmSEQ_RCV_ID_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
833 asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
834 asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TIMER_TERM_TS(lseq), 0); in asd_init_lseq_mdp()
864 u16 max_scbs = 0; in asd_init_scb_sites()
871 /* Initialize all fields in the SCB site to 0. */ in asd_init_scb_sites()
872 for (i = 0; i < ASD_SCB_SIZE; i += 4) in asd_init_scb_sites()
873 asd_scbsite_write_dword(asd_ha, site_no, i, 0); in asd_init_scb_sites()
878 0xFF); in asd_init_scb_sites()
883 asd_scbsite_write_byte(asd_ha, site_no, 0x49, 0x01); in asd_init_scb_sites()
890 if (last_scb_site_no == 0) in asd_init_scb_sites()
898 asd_scbsite_write_word(asd_ha, site_no, 0, first_scb_site_no); in asd_init_scb_sites()
905 ASD_DPRINTK("first_scb_site_no:0x%x\n", first_scb_site_no); in asd_init_scb_sites()
906 ASD_DPRINTK("last_scb_site_no:0x%x\n", last_scb_site_no); in asd_init_scb_sites()
917 asd_write_reg_byte(asd_ha, CSEQCOMINTEN, 0); in asd_init_cseq_cio()
919 asd_write_reg_byte(asd_ha, CSEQDLOFFS, 0); in asd_init_cseq_cio()
920 asd_write_reg_byte(asd_ha, CSEQDLOFFS+1, 0); in asd_init_cseq_cio()
921 asd_ha->seq.scbpro = 0; in asd_init_cseq_cio()
922 asd_write_reg_dword(asd_ha, SCBPRO, 0); in asd_init_cseq_cio()
923 asd_write_reg_dword(asd_ha, CSEQCON, 0); in asd_init_cseq_cio()
929 asd_write_reg_word(asd_ha, CM11INTVEC0, cseq_vecs[0]); in asd_init_cseq_cio()
936 /* Initialize CSEQ Scratch Page to 0x04. */ in asd_init_cseq_cio()
937 asd_write_reg_byte(asd_ha, CSCRATCHPAGE, 0x04); in asd_init_cseq_cio()
939 /* Initialize CSEQ Mode[0-8] Dependent registers. */ in asd_init_cseq_cio()
940 /* Initialize Scratch Page to 0. */ in asd_init_cseq_cio()
941 for (i = 0; i < 9; i++) in asd_init_cseq_cio()
942 asd_write_reg_byte(asd_ha, CMnSCRATCHPAGE(i), 0); in asd_init_cseq_cio()
947 for (i = 0; i < 8; i++) { in asd_init_cseq_cio()
951 asd_write_reg_dword(asd_ha, CMnREQMBX(i), 0); in asd_init_cseq_cio()
968 asd_write_reg_byte(asd_ha, LmSCRATCHPAGE(lseq), 0); in asd_init_lseq_cio()
970 /* Initialize Mode 0,1, and 2 SCRATCHPAGE to 0. */ in asd_init_lseq_cio()
971 for (i = 0; i < 3; i++) in asd_init_lseq_cio()
972 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, i), 0); in asd_init_lseq_cio()
974 /* Initialize Mode 5 SCRATCHPAGE to 0. */ in asd_init_lseq_cio()
975 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, 5), 0); in asd_init_lseq_cio()
977 asd_write_reg_dword(asd_ha, LmRSPMBX(lseq), 0); in asd_init_lseq_cio()
978 /* Initialize Mode 0,1,2 and 5 Interrupt Enable and in asd_init_lseq_cio()
980 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 0), LmM0INTEN_MASK); in asd_init_lseq_cio()
981 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 0), 0xFFFFFFFF); in asd_init_lseq_cio()
984 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 1), 0xFFFFFFFF); in asd_init_lseq_cio()
987 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 2), 0xFFFFFFFF); in asd_init_lseq_cio()
990 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 5), 0xFFFFFFFF); in asd_init_lseq_cio()
995 /* Enable Primitive Status 0 and 1. */ in asd_init_lseq_cio()
1001 asd_write_reg_byte(asd_ha, LmMnHOLDLVL(lseq, 0), 0x50); in asd_init_lseq_cio()
1003 /* Initialize Mode 0 Transfer Level to 512. */ in asd_init_lseq_cio()
1004 asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 0), LmMnXFRLVL_512); in asd_init_lseq_cio()
1018 /* Clear Primitive Status 0 and 1. */ in asd_init_lseq_cio()
1019 asd_write_reg_dword(asd_ha, LmPRMSTAT0(lseq), 0xFFFFFFFF); in asd_init_lseq_cio()
1020 asd_write_reg_dword(asd_ha, LmPRMSTAT1(lseq), 0xFFFFFFFF); in asd_init_lseq_cio()
1023 asd_write_reg_byte(asd_ha, LmHWTSTAT(lseq), 0xFF); in asd_init_lseq_cio()
1025 /* Clear DMA Errors for Mode 0 and 1. */ in asd_init_lseq_cio()
1026 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 0), 0xFF); in asd_init_lseq_cio()
1027 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 1), 0xFF); in asd_init_lseq_cio()
1029 /* Clear SG DMA Errors for Mode 0 and 1. */ in asd_init_lseq_cio()
1030 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 0), 0xFF); in asd_init_lseq_cio()
1031 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 1), 0xFF); in asd_init_lseq_cio()
1033 /* Clear Mode 0 Buffer Parity Error. */ in asd_init_lseq_cio()
1034 asd_write_reg_byte(asd_ha, LmMnBUFSTAT(lseq, 0), LmMnBUFPERR); in asd_init_lseq_cio()
1036 /* Clear Mode 0 Frame Error register. */ in asd_init_lseq_cio()
1037 asd_write_reg_dword(asd_ha, LmMnFRMERR(lseq, 0), 0xFFFFFFFF); in asd_init_lseq_cio()
1044 for (i = 0; i < SAS_ADDR_SIZE; i++) in asd_init_lseq_cio()
1047 /* Set the Transmit Size to 1024 bytes, 0 = 256 Dwords. */ in asd_init_lseq_cio()
1048 asd_write_reg_byte(asd_ha, LmMnXMTSIZE(lseq, 1), 0); in asd_init_lseq_cio()
1054 asd_write_reg_byte(asd_ha, LmMnSATAFS(lseq, 1), 0x80); in asd_init_lseq_cio()
1056 /* Initialize Interrupt Vector[0-10] address in Mode 3. in asd_init_lseq_cio()
1058 asd_write_reg_word(asd_ha, LmM3INTVEC0(lseq), lseq_vecs[0]); in asd_init_lseq_cio()
1090 for (i = 0; i < 8; i++) in asd_post_init_cseq()
1091 asd_write_reg_dword(asd_ha, CMnINT(i), 0xFFFFFFFF); in asd_post_init_cseq()
1092 for (i = 0; i < 8; i++) in asd_post_init_cseq()
1099 * asd_init_ddb_0 -- initialize DDB 0
1102 * Initialize DDB site 0 which is used internally by the sequencer.
1109 for (i = 0; i < sizeof(struct asd_ddb_seq_shared); i+=4) in asd_init_ddb_0()
1110 asd_ddbsite_write_dword(asd_ha, 0, i, 0); in asd_init_ddb_0()
1112 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1113 offsetof(struct asd_ddb_seq_shared, q_free_ddb_head), 0); in asd_init_ddb_0()
1114 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1117 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1118 offsetof(struct asd_ddb_seq_shared, q_free_ddb_cnt), 0); in asd_init_ddb_0()
1119 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1120 offsetof(struct asd_ddb_seq_shared, q_used_ddb_head), 0xFFFF); in asd_init_ddb_0()
1121 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1122 offsetof(struct asd_ddb_seq_shared, q_used_ddb_tail), 0xFFFF); in asd_init_ddb_0()
1123 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1124 offsetof(struct asd_ddb_seq_shared, shared_mem_lock), 0); in asd_init_ddb_0()
1125 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1126 offsetof(struct asd_ddb_seq_shared, smp_conn_tag), 0); in asd_init_ddb_0()
1127 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1128 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_cnt), 0); in asd_init_ddb_0()
1129 asd_ddbsite_write_word(asd_ha, 0, in asd_init_ddb_0()
1132 asd_ddbsite_write_byte(asd_ha, 0, in asd_init_ddb_0()
1133 offsetof(struct asd_ddb_seq_shared, settable_max_contexts),0); in asd_init_ddb_0()
1134 asd_ddbsite_write_byte(asd_ha, 0, in asd_init_ddb_0()
1135 offsetof(struct asd_ddb_seq_shared, conn_not_active), 0xFF); in asd_init_ddb_0()
1136 asd_ddbsite_write_byte(asd_ha, 0, in asd_init_ddb_0()
1137 offsetof(struct asd_ddb_seq_shared, phy_is_up), 0x00); in asd_init_ddb_0()
1138 /* DDB 0 is reserved */ in asd_init_ddb_0()
1139 set_bit(0, asd_ha->hw_prof.ddb_bitmap); in asd_init_ddb_0()
1147 for (ddb_site = 0 ; ddb_site < ASD_MAX_DDBS; ddb_site++) in asd_seq_init_ddb_sites()
1148 for (i = 0; i < sizeof(struct asd_ddb_ssp_smp_target_port); i+= 4) in asd_seq_init_ddb_sites()
1149 asd_ddbsite_write_dword(asd_ha, ddb_site, i, 0); in asd_seq_init_ddb_sites()
1217 return 0; in asd_release_firmware()
1225 u32 csum = 0; in asd_request_firmware()
1230 return 0; in asd_request_firmware()
1285 for (i = 0; i < CSEQ_NUM_VECS; i++) in asd_request_firmware()
1288 for (i = 0; i < LSEQ_NUM_VECS; i++) in asd_request_firmware()
1296 return 0; in asd_request_firmware()
1320 return 0; in asd_init_seqs()
1346 return 0; in asd_start_seqs()
1356 * the phy is up, i.e. we update the phy_is_up in DDB 0. The
1362 * port_map_by_links in DDB 0. When a HARD_RESET primitive has been
1377 asd_ddbsite_write_byte(asd_ha, 0, in asd_update_port_links()
1381 for (i = 0; i < 12; i++) { in asd_update_port_links()
1382 phy_is_up = asd_ddbsite_read_byte(asd_ha, 0, in asd_update_port_links()
1384 err = asd_ddbsite_update_byte(asd_ha, 0, in asd_update_port_links()
1391 asd_printk("phy_is_up: parity error in DDB 0\n"); in asd_update_port_links()
1398 asd_printk("couldn't update DDB 0:error:%d\n", err); in asd_update_port_links()