Lines Matching full:mode
22 #define CSEQ_MODE_PAGE_SIZE 0x200 /* CSEQ mode page size */
23 #define LmSEQ_MODE_PAGE_SIZE 0x200 /* LmSEQ mode page size */
497 * 16 modes, each mode is 512 bytes.
502 #define CSEQm_CIO_REG(Mode, Reg) \ argument
504 ((u32) (Mode) * CSEQ_MODE_PAGE_SIZE) + (u32) (Reg))
552 #define CMnSCBPTR(Mode) CSEQm_CIO_REG(Mode, MnSCBPTR) argument
554 #define CMnDDBPTR(Mode) CSEQm_CIO_REG(Mode, MnDDBPTR) argument
556 #define CMnSCRATCHPAGE(Mode) CSEQm_CIO_REG(Mode, MnSCRATCHPAGE) argument
562 /* mode 0-7 */
564 #define CMnREQMBX(Mode) CSEQm_CIO_REG(Mode, 0x30) argument
566 /* mode 8 */
569 /* mode 0-7 */
571 #define CMnRSPMBX(Mode) CSEQm_CIO_REG(Mode, 0x34) argument
573 /* mode 8 */
576 /* mode 8 */
579 /* mode 8 */
582 /* mode 8 */
591 /* mode 0-7 */
593 #define CMnINT(Mode) CSEQm_CIO_REG(Mode, 0x38) argument
599 /* mode 8 */
602 /* mode 0-7 */
604 #define CMnINTEN(Mode) CSEQm_CIO_REG(Mode, 0x3C) argument
608 /* mode 8 */
611 /* mode 8 */
614 /* mode 8 */
617 /* mode 8 */
635 /* mode 8 */
638 /* mode 11 */
641 /* mode 11 */
644 /* mode 11 */
657 /* mode 8, 32x32 bits, 128 bytes of mapped buffer */
662 /* mode 0-8 */
663 #define CMnSCRATCH(Mode) CSEQm_CIO_REG(Mode, 0x1E0) argument
827 * 8 modes, each mode is 512 bytes.
832 #define LmSEQ_PHY_BASE(Mode, LinkNum) \ argument
836 ((u32) (Mode) * LmSEQ_MODE_PAGE_SIZE))
838 #define LmSEQ_PHY_REG(Mode, LinkNum, Reg) \ argument
839 (LmSEQ_PHY_BASE(Mode, LinkNum) + (u32) (Reg))
887 #define LmMnSCRATCHPAGE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, \ argument
896 #define LmMnINT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x38) argument
926 #define LmMnINTEN(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x3C) argument
986 #define LmMnDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x46) argument
988 #define LmMnSGDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x47) argument
1019 #define LmMnBUFSTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x4E) argument
1023 /* mode 0-1 */
1024 #define LmMnXFRLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x59) argument
1033 /* mode 0-1 */
1034 #define LmMnSGDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5A) argument
1040 /* mode 0-1 */
1041 #define LmMnSGDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5B) argument
1043 /* mode 0-1 */
1044 #define LmMnDDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5C) argument
1054 /* mode 0-1 */
1055 #define LmMnDDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5D) argument
1066 /* mode 0-1 */
1067 #define LmMnDDMAMODE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5E) argument
1085 /* mode 0-1 */
1086 #define LmMnXFRCNT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x70) argument
1088 /* mode 0-1 */
1089 #define LmMnDPSEL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7B) argument
1095 /* Receive Mode n = 0 */
1104 /* Transmit Mode n = 1 */
1112 /* mode 0-1 */
1113 #define LmMnDPACC(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x78) argument
1116 /* mode 0-1 */
1117 #define LmMnHOLDLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7D) argument
1191 /* mode 1 */
1192 #define LmMnSATAFS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7E) argument
1193 #define LmMnXMTSIZE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x93) argument
1195 /* mode 0 */
1196 #define LmMnFRMERR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xB0) argument
1256 #define LmMnDATABUFADR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xC8) argument
1259 #define LmMnDATABUF(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xCA) argument
1343 * LmSEQ CIO Bus Mode 3 Register.
1344 * Mode 3: Configuration and Setup, IOP Context SCB.
1378 * LmSEQ CIO Bus Mode 5 Registers.
1379 * Mode 5: Phy/OOB Control and Status.
1964 * protection. The CSEQ accesses it in 32 byte windows, either as mode
1965 * dependent or mode independent memory. Each mode has 96 bytes,
1967 * Mode Independent memory (four 32 byte pages 3-7). Note that mode
1968 * dependent scratch memory, Mode 8, page 0-3 overlaps mode
1970 * - 896 bytes of mode dependent scratch, 96 bytes per Modes 0-7, and
1971 * 128 bytes in mode 8,
1972 * - 259 bytes of mode independent scratch, common to modes 0-15.
1975 * divided into mode dependent and mode independent scratch with this
1977 * pages (160 bytes) of mode independent scratch and 3 pages of
1978 * dependent scratch memory for modes 0-7 (768 bytes). Mode 8 pages
1979 * 0-2 dependent scratch overlap with pages 0-2 of mode independent
1991 * 800h-83Fh Mode Dependent Scratch Mode 0 Pages 0-1
1992 * 840h-87Fh Mode Dependent Scratch Mode 1 Pages 0-1
1993 * 880h-8BFh Mode Dependent Scratch Mode 2 Pages 0-1
1994 * 8C0h-8FFh Mode Dependent Scratch Mode 3 Pages 0-1
1995 * 900h-93Fh Mode Dependent Scratch Mode 4 Pages 0-1
1996 * 940h-97Fh Mode Dependent Scratch Mode 5 Pages 0-1
1997 * 980h-9BFh Mode Dependent Scratch Mode 6 Pages 0-1
1998 * 9C0h-9FFh Mode Dependent Scratch Mode 7 Pages 0-1
1999 * A00h-A5Fh Mode Dependent Scratch Mode 8 Pages 0-2
2000 * Mode Independent Scratch Pages 0-2
2001 * A60h-A7Fh Mode Dependent Scratch Mode 8 Page 3
2002 * Mode Independent Scratch Page 3
2003 * A80h-AFFh Mode Independent Scratch Pages 4-7
2004 * B00h-B1Fh Mode Dependent Scratch Mode 0 Page 2
2005 * B20h-B3Fh Mode Dependent Scratch Mode 1 Page 2
2006 * B40h-B5Fh Mode Dependent Scratch Mode 2 Page 2
2007 * B60h-B7Fh Mode Dependent Scratch Mode 3 Page 2
2008 * B80h-B9Fh Mode Dependent Scratch Mode 4 Page 2
2009 * BA0h-BBFh Mode Dependent Scratch Mode 5 Page 2
2010 * BC0h-BDFh Mode Dependent Scratch Mode 6 Page 2
2011 * BE0h-BFFh Mode Dependent Scratch Mode 7 Page 2
2018 * Mode dependent scratch page 0, mode 0.
2026 /* Mode dependent scratch page 0 mode 8 macros. */
2042 /* Mode dependent scratch page 1 mode 8 macros. */
2046 /* Mode dependent scratch page 2 mode 8 macros */
2052 /* Mode independent scratch page 4 macros. */
2070 /* Mode independent scratch page 5 macros. */
2080 /* Mode independent scratch page 6 macros. */
2096 /* Mode independent scratch page 7 macros. */
2110 * This scratch memory is divided into mode dependent and mode
2113 * mode independent scratch and 4 pages of dependent scratch
2125 * 800h-85Fh Mode Dependent Scratch Mode 0 Pages 0-2
2126 * 860h-87Fh Mode Dependent Scratch Mode 0 Page 3
2127 * Mode Dependent Scratch Mode 5 Page 0
2128 * 880h-8DFh Mode Dependent Scratch Mode 1 Pages 0-2
2129 * 8E0h-8FFh Mode Dependent Scratch Mode 1 Page 3
2130 * Mode Dependent Scratch Mode 5 Page 1
2131 * 900h-95Fh Mode Dependent Scratch Mode 2 Pages 0-2
2132 * 960h-97Fh Mode Dependent Scratch Mode 2 Page 3
2133 * Mode Dependent Scratch Mode 5 Page 2
2134 * 980h-9DFh Mode Independent Scratch Pages 0-3
2135 * 9E0h-9FFh Mode Independent Scratch Page 3
2136 * Mode Dependent Scratch Mode 5 Page 3
2140 #define LSEQ_MODE_SCRATCH_SIZE 0x80 /* Size of scratch RAM per mode */
2144 /* Common mode dependent scratch page 0 macros for modes 0,1,2, and 5 */
2145 /* Indexed using LSEQ_MODE_SCRATCH_SIZE * mode, for modes 0,1,2. */
2150 /* Mode flag macros (byte 0) */
2160 /* Mode flag macros (byte 1) */
2169 /* Mode dependent scratch page 0 macros for mode 0 (non-common) */
2182 /* Mode dependent scratch page 0 macros for mode 1 (non-common) */
2193 /* Mode dependent scratch page 0 macros for mode 2 (non-common) */
2201 /* Mode dependent scratch page 0 macros for modes 4/5 (non-common) */
2216 /* Mode dependent scratch page 1, mode 0 and mode 1 */
2222 /* Mode dependent scratch page 1 macros for mode 2 */
2228 /* Mode dependent scratch page 1 macros for mode 4/5 */
2238 /* Mode dependent scratch page 2 macros for mode 0 */
2246 /* Mode dependent scratch page 2 macros for mode 1 */
2254 /* Mode dependent scratch page 2 macros for mode 2 */
2264 /* Mode dependent scratch page 2 macros for mode 5 */
2270 /* Mode dependent scratch page 3 macros for modes 0 and 1 */
2273 /* Mode dependent scratch page 3 macros for modes 2 and 5 */
2276 /* Mode Independent Scratch page 0 macros. */
2341 /* Mode independent scratch page 1 macros. */
2357 /* Mode independent scratch page 2 macros. */
2371 /* Mode independent scratch page 3 macros. */