Lines Matching +full:0 +full:x007fffff
22 #define CSEQ_MODE_PAGE_SIZE 0x200 /* CSEQ mode page size */
23 #define LmSEQ_MODE_PAGE_SIZE 0x200 /* LmSEQ mode page size */
24 #define LmSEQ_HOST_REG_SIZE 0x4000 /* LmSEQ Host Register size */
32 * CHIM Registers, Address Range : (0x00-0xFF)
34 #define COMBIST (REG_BASE_ADDR + 0x00)
37 #define L7BLKRST 0x80000000
38 #define L6BLKRST 0x40000000
39 #define L5BLKRST 0x20000000
40 #define L4BLKRST 0x10000000
41 #define L3BLKRST 0x08000000
42 #define L2BLKRST 0x04000000
43 #define L1BLKRST 0x02000000
44 #define L0BLKRST 0x01000000
45 #define LmBLKRST 0xFF000000
48 #define OCMBLKRST 0x00400000
49 #define CTXMEMBLKRST 0x00200000
50 #define CSEQBLKRST 0x00100000
51 #define EXSIBLKRST 0x00040000
52 #define DPIBLKRST 0x00020000
53 #define DFIFBLKRST 0x00010000
54 #define HARDRST 0x00000200
55 #define COMBLKRST 0x00000100
56 #define FRCDFPERR 0x00000080
57 #define FRCCIOPERR 0x00000020
58 #define FRCBISTERR 0x00000010
59 #define COMBISTEN 0x00000004
60 #define COMBISTDONE 0x00000002 /* ro */
61 #define COMBISTFAIL 0x00000001 /* ro */
63 #define COMSTAT (REG_BASE_ADDR + 0x04)
65 #define REQMBXREAD 0x00000040
66 #define RSPMBXAVAIL 0x00000020
67 #define CSBUFPERR 0x00000008
68 #define OVLYERR 0x00000004
69 #define CSERR 0x00000002
70 #define OVLYDMADONE 0x00000001
76 #define COMSTATEN (REG_BASE_ADDR + 0x08)
78 #define EN_REQMBXREAD 0x00000040
79 #define EN_RSPMBXAVAIL 0x00000020
80 #define EN_CSBUFPERR 0x00000008
81 #define EN_OVLYERR 0x00000004
82 #define EN_CSERR 0x00000002
83 #define EN_OVLYDONE 0x00000001
85 #define SCBPRO (REG_BASE_ADDR + 0x0C)
87 #define SCBCONS_MASK 0xFFFF0000
88 #define SCBPRO_MASK 0x0000FFFF
90 #define CHIMREQMBX (REG_BASE_ADDR + 0x10)
92 #define CHIMRSPMBX (REG_BASE_ADDR + 0x14)
94 #define CHIMINT (REG_BASE_ADDR + 0x18)
96 #define EXT_INT0 0x00000800
97 #define EXT_INT1 0x00000400
98 #define PORRSTDET 0x00000200
99 #define HARDRSTDET 0x00000100
100 #define DLAVAILQ 0x00000080 /* ro */
101 #define HOSTERR 0x00000040
102 #define INITERR 0x00000020
103 #define DEVINT 0x00000010
104 #define COMINT 0x00000008
105 #define DEVTIMER2 0x00000004
106 #define DEVTIMER1 0x00000002
107 #define DLAVAIL 0x00000001
114 #define CHIMINTEN (REG_BASE_ADDR + 0x1C)
116 #define RST_EN_EXT_INT1 0x01000000
117 #define RST_EN_EXT_INT0 0x00800000
118 #define RST_EN_HOSTERR 0x00400000
119 #define RST_EN_INITERR 0x00200000
120 #define RST_EN_DEVINT 0x00100000
121 #define RST_EN_COMINT 0x00080000
122 #define RST_EN_DEVTIMER2 0x00040000
123 #define RST_EN_DEVTIMER1 0x00020000
124 #define RST_EN_DLAVAIL 0x00010000
125 #define SET_EN_EXT_INT1 0x00000100
126 #define SET_EN_EXT_INT0 0x00000080
127 #define SET_EN_HOSTERR 0x00000040
128 #define SET_EN_INITERR 0x00000020
129 #define SET_EN_DEVINT 0x00000010
130 #define SET_EN_COMINT 0x00000008
131 #define SET_EN_DEVTIMER2 0x00000004
132 #define SET_EN_DEVTIMER1 0x00000002
133 #define SET_EN_DLAVAIL 0x00000001
144 #define OVLYDMACTL (REG_BASE_ADDR + 0x20)
146 #define OVLYADR_MASK 0x07FF0000
147 #define OVLYLSEQ_MASK 0x0000FF00
148 #define OVLYCSEQ 0x00000080
149 #define OVLYHALTERR 0x00000040
150 #define PIOCMODE 0x00000020
151 #define RESETOVLYDMA 0x00000008 /* wo */
152 #define STARTOVLYDMA 0x00000004
153 #define STOPOVLYDMA 0x00000002 /* wo */
154 #define OVLYDMAACT 0x00000001 /* ro */
156 #define OVLYDMACNT (REG_BASE_ADDR + 0x24)
158 #define OVLYDOMAIN1 0x20000000 /* ro */
159 #define OVLYDOMAIN0 0x10000000
160 #define OVLYBUFADR_MASK 0x007F0000
161 #define OVLYDMACNT_MASK 0x00003FFF
163 #define OVLYDMAADR (REG_BASE_ADDR + 0x28)
165 #define DMAERR (REG_BASE_ADDR + 0x30)
167 #define OVLYERRSTAT_MASK 0x0000FF00 /* ro */
168 #define CSERRSTAT_MASK 0x000000FF /* ro */
170 #define SPIODATA (REG_BASE_ADDR + 0x34)
172 /* 0x38 - 0x3C are reserved */
174 #define T1CNTRLR (REG_BASE_ADDR + 0x40)
176 #define T1DONE 0x00010000 /* ro */
177 #define TIMER64 0x00000400
178 #define T1ENABLE 0x00000200
179 #define T1RELOAD 0x00000100
180 #define T1PRESCALER_MASK 0x00000003
182 #define T1CMPR (REG_BASE_ADDR + 0x44)
184 #define T1CNTR (REG_BASE_ADDR + 0x48)
186 #define T2CNTRLR (REG_BASE_ADDR + 0x4C)
188 #define T2DONE 0x00010000 /* ro */
189 #define T2ENABLE 0x00000200
190 #define T2RELOAD 0x00000100
191 #define T2PRESCALER_MASK 0x00000003
193 #define T2CMPR (REG_BASE_ADDR + 0x50)
195 #define T2CNTR (REG_BASE_ADDR + 0x54)
197 /* 0x58h - 0xFCh are reserved */
200 * DCH_SAS Registers, Address Range : (0x800-0xFFF)
202 #define CMDCTXBASE (REG_BASE_ADDR + 0x800)
204 #define DEVCTXBASE (REG_BASE_ADDR + 0x808)
206 #define CTXDOMAIN (REG_BASE_ADDR + 0x810)
208 #define DEVCTXDOMAIN1 0x00000008 /* ro */
209 #define DEVCTXDOMAIN0 0x00000004
210 #define CMDCTXDOMAIN1 0x00000002 /* ro */
211 #define CMDCTXDOMAIN0 0x00000001
213 #define DCHCTL (REG_BASE_ADDR + 0x814)
215 #define OCMBISTREPAIR 0x00080000
216 #define OCMBISTEN 0x00040000
217 #define OCMBISTDN 0x00020000 /* ro */
218 #define OCMBISTFAIL 0x00010000 /* ro */
219 #define DDBBISTEN 0x00004000
220 #define DDBBISTDN 0x00002000 /* ro */
221 #define DDBBISTFAIL 0x00001000 /* ro */
222 #define SCBBISTEN 0x00000400
223 #define SCBBISTDN 0x00000200 /* ro */
224 #define SCBBISTFAIL 0x00000100 /* ro */
226 #define MEMSEL_MASK 0x000000E0
227 #define MEMSEL_CCM_LSEQ 0x00000000
228 #define MEMSEL_CCM_IOP 0x00000020
229 #define MEMSEL_CCM_SASCTL 0x00000040
230 #define MEMSEL_DCM_LSEQ 0x00000060
231 #define MEMSEL_DCM_IOP 0x00000080
232 #define MEMSEL_OCM 0x000000A0
234 #define FRCERR 0x00000010
235 #define AUTORLS 0x00000001
237 #define DCHREVISION (REG_BASE_ADDR + 0x818)
239 #define DCHREVISION_MASK 0x000000FF
241 #define DCHSTATUS (REG_BASE_ADDR + 0x81C)
243 #define EN_CFIFTOERR 0x00020000
244 #define CFIFTOERR 0x00000200
245 #define CSEQINT 0x00000100 /* ro */
246 #define LSEQ7INT 0x00000080 /* ro */
247 #define LSEQ6INT 0x00000040 /* ro */
248 #define LSEQ5INT 0x00000020 /* ro */
249 #define LSEQ4INT 0x00000010 /* ro */
250 #define LSEQ3INT 0x00000008 /* ro */
251 #define LSEQ2INT 0x00000004 /* ro */
252 #define LSEQ1INT 0x00000002 /* ro */
253 #define LSEQ0INT 0x00000001 /* ro */
259 #define DCHDFIFDEBUG (REG_BASE_ADDR + 0x820)
260 #define ENFAIRMST 0x00FF0000
261 #define DISWRMST9 0x00000200
262 #define DISWRMST8 0x00000100
263 #define DISRDMST 0x000000FF
265 #define ATOMICSTATCTL (REG_BASE_ADDR + 0x824)
267 #define AUTOINC 0x80
268 #define ATOMICERR 0x04
269 #define ATOMICWIN 0x02
270 #define ATOMICDONE 0x01
273 #define ALTCIOADR (REG_BASE_ADDR + 0x828)
274 /* 16 bit; bits 8:0 define CIO addr space of CSEQ */
276 #define ASCBPTR (REG_BASE_ADDR + 0x82C)
279 #define ADDBPTR (REG_BASE_ADDR + 0x82E)
282 #define ANEWDATA (REG_BASE_ADDR + 0x830)
285 #define AOLDDATA (REG_BASE_ADDR + 0x834)
288 #define CTXACCESS (REG_BASE_ADDR + 0x838)
291 /* 0x83Ch - 0xFFCh are reserved */
294 * ARP2 External Processor Registers, Address Range : (0x00-0x1F)
296 #define ARP2CTL 0x00
298 #define FRCSCRPERR 0x00040000
299 #define FRCARP2PERR 0x00020000
300 #define FRCARP2ILLOPC 0x00010000
301 #define ENWAITTO 0x00008000
302 #define PERRORDIS 0x00004000
303 #define FAILDIS 0x00002000
304 #define CIOPERRDIS 0x00001000
305 #define BREAKEN3 0x00000800
306 #define BREAKEN2 0x00000400
307 #define BREAKEN1 0x00000200
308 #define BREAKEN0 0x00000100
309 #define EPAUSE 0x00000008
310 #define PAUSED 0x00000004 /* ro */
311 #define STEP 0x00000002
312 #define ARP2RESET 0x00000001 /* wo */
314 #define ARP2INT 0x04
316 #define HALTCODE_MASK 0x00FF0000 /* ro */
317 #define ARP2WAITTO 0x00000100
318 #define ARP2HALTC 0x00000080
319 #define ARP2ILLOPC 0x00000040
320 #define ARP2PERR 0x00000020
321 #define ARP2CIOPERR 0x00000010
322 #define ARP2BREAK3 0x00000008
323 #define ARP2BREAK2 0x00000004
324 #define ARP2BREAK1 0x00000002
325 #define ARP2BREAK0 0x00000001
327 #define ARP2INTEN 0x08
329 #define EN_ARP2WAITTO 0x00000100
330 #define EN_ARP2HALTC 0x00000080
331 #define EN_ARP2ILLOPC 0x00000040
332 #define EN_ARP2PERR 0x00000020
333 #define EN_ARP2CIOPERR 0x00000010
334 #define EN_ARP2BREAK3 0x00000008
335 #define EN_ARP2BREAK2 0x00000004
336 #define EN_ARP2BREAK1 0x00000002
337 #define EN_ARP2BREAK0 0x00000001
339 #define ARP2BREAKADR01 0x0C
341 #define BREAKADR1_MASK 0x0FFF0000
342 #define BREAKADR0_MASK 0x00000FFF
344 #define ARP2BREAKADR23 0x10
346 #define BREAKADR3_MASK 0x0FFF0000
347 #define BREAKADR2_MASK 0x00000FFF
349 /* 0x14h - 0x1Ch are reserved */
352 * ARP2 Registers, Address Range : (0x00-0x1F)
356 #define MODEPTR 0x00
358 #define DSTMODE 0xF0
359 #define SRCMODE 0x0F
361 #define ALTMODE 0x01
363 #define ALTDMODE 0xF0
364 #define ALTSMODE 0x0F
366 #define ATOMICXCHG 0x02
368 #define FLAG 0x04
370 #define INTCODE_MASK 0xF0
371 #define ALTMODEV2 0x04
372 #define CARRY_INT 0x02
373 #define CARRY 0x01
375 #define ARP2INTCTL 0x05
377 #define PAUSEDIS 0x80
378 #define RSTINTCTL 0x40
379 #define POPALTMODE 0x08
380 #define ALTMODEV 0x04
381 #define INTMASK 0x02
382 #define IRET 0x01
384 #define STACK 0x06
386 #define FUNCTION1 0x07
388 #define PRGMCNT 0x08
390 #define ACCUM 0x0A
392 #define SINDEX 0x0C
394 #define DINDEX 0x0E
396 #define ALLONES 0x10
398 #define ALLZEROS 0x11
400 #define SINDIR 0x12
402 #define DINDIR 0x13
404 #define JUMLDIR 0x14
406 #define ARP2HALTCODE 0x15
408 #define CURRADDR 0x16
410 #define LASTADDR 0x18
412 #define NXTLADDR 0x1A
414 #define DBGPORTPTR 0x1C
416 #define DBGPORT 0x1D
423 #define MnSCBPTR 0x20
425 #define MnDDBPTR 0x22
427 #define SCRATCHPAGE 0x24
429 #define MnSCRATCHPAGE 0x25
431 #define SCRATCHPAGESV 0x26
433 #define MnSCRATCHPAGESV 0x27
435 #define MnDMAERRS 0x46
437 #define MnSGDMAERRS 0x47
439 #define MnSGBUF 0x53
441 #define MnSGDMASTAT 0x5b
443 #define MnDDMACTL 0x5c /* RAZOR.rspec.fm rev 1.5 is wrong */
445 #define MnDDMASTAT 0x5d /* RAZOR.rspec.fm rev 1.5 is wrong */
447 #define MnDDMAMODE 0x5e /* RAZOR.rspec.fm rev 1.5 is wrong */
449 #define MnDMAENG 0x60
451 #define MnPIPECTL 0x61
453 #define MnSGBADR 0x65
455 #define MnSCB_SITE 0x100
457 #define MnDDB_SITE 0x180
463 #define BISTCTL0 0x4C
465 #define BISTCTL1 0x50
467 #define MAPPEDSCR 0x800
470 * CSEQ Host Register, Address Range : (0x000-0xFFC)
472 #define CSEQ_HOST_REG_BASE_ADR 0xB8001000
486 #define CSEQRAMBISTEN 0x00000040
487 #define CSEQRAMBISTDN 0x00000020 /* ro */
488 #define CSEQRAMBISTFAIL 0x00000010 /* ro */
489 #define CSEQSCRBISTEN 0x00000004
490 #define CSEQSCRBISTDN 0x00000002 /* ro */
491 #define CSEQSCRBISTFAIL 0x00000001 /* ro */
496 * CSEQ CIO Bus Registers, Address Range : (0x0000-0x1FFC)
558 #define CLINKCON (CSEQ_CIO_REG_BASE_ADR + 0x28)
560 #define CCIOAACESS (CSEQ_CIO_REG_BASE_ADR + 0x2C)
562 /* mode 0-7 */
563 #define MnREQMBX 0x30
564 #define CMnREQMBX(Mode) CSEQm_CIO_REG(Mode, 0x30)
567 #define CSEQCON CSEQm_CIO_REG(8, 0x30)
569 /* mode 0-7 */
570 #define MnRSPMBX 0x34
571 #define CMnRSPMBX(Mode) CSEQm_CIO_REG(Mode, 0x34)
574 #define CSEQCOMCTL CSEQm_CIO_REG(8, 0x34)
577 #define CSEQCOMSTAT CSEQm_CIO_REG(8, 0x35)
580 #define CSEQCOMINTEN CSEQm_CIO_REG(8, 0x36)
583 #define CSEQCOMDMACTL CSEQm_CIO_REG(8, 0x37)
585 #define CSHALTERR 0x10
586 #define RESETCSDMA 0x08 /* wo */
587 #define STARTCSDMA 0x04
588 #define STOPCSDMA 0x02 /* wo */
589 #define CSDMAACT 0x01 /* ro */
591 /* mode 0-7 */
592 #define MnINT 0x38
593 #define CMnINT(Mode) CSEQm_CIO_REG(Mode, 0x38)
595 #define CMnREQMBXE 0x02
596 #define CMnRSPMBXF 0x01
597 #define CMnINT_MASK 0x00000003
600 #define CSEQREQMBX CSEQm_CIO_REG(8, 0x38)
602 /* mode 0-7 */
603 #define MnINTEN 0x3C
604 #define CMnINTEN(Mode) CSEQm_CIO_REG(Mode, 0x3C)
606 #define EN_CMnRSPMBXF 0x01
609 #define CSEQRSPMBX CSEQm_CIO_REG(8, 0x3C)
612 #define CSDMAADR CSEQm_CIO_REG(8, 0x40)
615 #define CSDMACNT CSEQm_CIO_REG(8, 0x48)
618 #define CSEQDLCTL CSEQm_CIO_REG(8, 0x4D)
620 #define DONELISTEND 0x10
621 #define DONELISTSIZE_MASK 0x0F
622 #define DONELISTSIZE_8ELEM 0x01
623 #define DONELISTSIZE_16ELEM 0x02
624 #define DONELISTSIZE_32ELEM 0x03
625 #define DONELISTSIZE_64ELEM 0x04
626 #define DONELISTSIZE_128ELEM 0x05
627 #define DONELISTSIZE_256ELEM 0x06
628 #define DONELISTSIZE_512ELEM 0x07
629 #define DONELISTSIZE_1024ELEM 0x08
630 #define DONELISTSIZE_2048ELEM 0x09
631 #define DONELISTSIZE_4096ELEM 0x0A
632 #define DONELISTSIZE_8192ELEM 0x0B
633 #define DONELISTSIZE_16384ELEM 0x0C
636 #define CSEQDLOFFS CSEQm_CIO_REG(8, 0x4E)
639 #define CM11INTVEC0 CSEQm_CIO_REG(11, 0x50)
642 #define CM11INTVEC1 CSEQm_CIO_REG(11, 0x52)
645 #define CM11INTVEC2 CSEQm_CIO_REG(11, 0x54)
647 #define CCONMSK (CSEQ_CIO_REG_BASE_ADR + 0x60)
649 #define CCONEXIST (CSEQ_CIO_REG_BASE_ADR + 0x61)
651 #define CCONMODE (CSEQ_CIO_REG_BASE_ADR + 0x62)
653 #define CTIMERCALC (CSEQ_CIO_REG_BASE_ADR + 0x64)
655 #define CINTDIS (CSEQ_CIO_REG_BASE_ADR + 0x68)
658 #define CSBUFFER CSEQm_CIO_REG(8, 0x80)
660 #define CSCRATCH (CSEQ_CIO_REG_BASE_ADR + 0x1C0)
662 /* mode 0-8 */
663 #define CMnSCRATCH(Mode) CSEQm_CIO_REG(Mode, 0x1E0)
666 * CSEQ Mapped Instruction RAM Page, Address Range : (0x0000-0x1FFC)
668 #define CSEQ_RAM_REG_BASE_ADR 0xB8004000
674 #define MODECTL 0x40
676 #define DBGMODE 0x44
678 #define CONTROL 0x48
679 #define LEDTIMER 0x00010000
680 #define LEDTIMERS_10us 0x00000000
681 #define LEDTIMERS_1ms 0x00000800
682 #define LEDTIMERS_100ms 0x00001000
683 #define LEDMODE_TXRX 0x00000000
684 #define LEDMODE_CONNECTED 0x00000200
685 #define LEDPOL 0x00000100
687 #define LSEQRAM 0x1000
690 * LmSEQ Host Registers, Address Range : (0x0000-0x3FFC)
692 #define LSEQ0_HOST_REG_BASE_ADR 0xB8020000
693 #define LSEQ1_HOST_REG_BASE_ADR 0xB8024000
694 #define LSEQ2_HOST_REG_BASE_ADR 0xB8028000
695 #define LSEQ3_HOST_REG_BASE_ADR 0xB802C000
696 #define LSEQ4_HOST_REG_BASE_ADR 0xB8030000
697 #define LSEQ5_HOST_REG_BASE_ADR 0xB8034000
698 #define LSEQ6_HOST_REG_BASE_ADR 0xB8038000
699 #define LSEQ7_HOST_REG_BASE_ADR 0xB803C000
733 #define LmAUTODISCI 0x08000000
734 #define LmDSBLBITLT 0x04000000
735 #define LmDSBLANTT 0x02000000
736 #define LmDSBLCRTT 0x01000000
737 #define LmDSBLCONT 0x00000100
738 #define LmPRIMODE 0x00000080
739 #define LmDSBLHOLD 0x00000040
740 #define LmDISACK 0x00000020
741 #define LmBLIND48 0x00000010
742 #define LmRCVMODE_MASK 0x0000000C
743 #define LmRCVMODE_PLD 0x00000000
744 #define LmRCVMODE_HPC 0x00000004
750 #define LmFRCPERR 0x80000000
751 #define LmMEMSEL_MASK 0x30000000
752 #define LmFRCRBPERR 0x00000000
753 #define LmFRCTBPERR 0x10000000
754 #define LmFRCSGBPERR 0x20000000
755 #define LmFRCARBPERR 0x30000000
756 #define LmRCVIDW 0x00080000
757 #define LmINVDWERR 0x00040000
758 #define LmRCVDISP 0x00004000
759 #define LmDISPERR 0x00002000
760 #define LmDSBLDSCR 0x00000800
761 #define LmDSBLSCR 0x00000400
762 #define LmFRCNAK 0x00000200
763 #define LmFRCROFS 0x00000100
764 #define LmFRCCRC 0x00000080
765 #define LmFRMTYPE_MASK 0x00000070
766 #define LmSG_DATA 0x00000000
767 #define LmSG_COMMAND 0x00000010
768 #define LmSG_TASK 0x00000020
769 #define LmSG_TGTXFER 0x00000030
770 #define LmSG_RESPONSE 0x00000040
771 #define LmSG_IDENADDR 0x00000050
772 #define LmSG_OPENADDR 0x00000060
773 #define LmDISCRCGEN 0x00000008
774 #define LmDISCRCCHK 0x00000004
775 #define LmSSXMTFRM 0x00000002
776 #define LmSSRCVFRM 0x00000001
782 #define LmSTEPXMTFRM 0x00000002
783 #define LmSTEPRCVFRM 0x00000001
789 #define ARBBISTEN 0x40000000
790 #define ARBBISTDN 0x20000000 /* ro */
791 #define ARBBISTFAIL 0x10000000 /* ro */
792 #define TBBISTEN 0x00000400
793 #define TBBISTDN 0x00000200 /* ro */
794 #define TBBISTFAIL 0x00000100 /* ro */
795 #define RBBISTEN 0x00000040
796 #define RBBISTDN 0x00000020 /* ro */
797 #define RBBISTFAIL 0x00000010 /* ro */
798 #define SGBISTEN 0x00000004
799 #define SGBISTDN 0x00000002 /* ro */
800 #define SGBISTFAIL 0x00000001 /* ro */
806 #define LmRAMPAGE1 0x00000200
807 #define LmRAMPAGE0 0x00000100
808 #define LmIMEMBISTEN 0x00000040
809 #define LmIMEMBISTDN 0x00000020 /* ro */
810 #define LmIMEMBISTFAIL 0x00000010 /* ro */
811 #define LmSCRBISTEN 0x00000004
812 #define LmSCRBISTDN 0x00000002 /* ro */
813 #define LmSCRBISTFAIL 0x00000001 /* ro */
815 #define LmRAMPAGE_LSHIFT 0x8
826 * LmSEQ CIO Bus Register, Address Range : (0x0000-0xFFC)
830 #define LmSEQ_CIOBUS_REG_BASE 0x2000
841 #define LmMODEPTR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, MODEPTR)
843 #define LmALTMODE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ALTMODE)
845 #define LmATOMICXCHG(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ATOMICXCHG)
847 #define LmFLAG(LinkNum) LmSEQ_PHY_REG(0, LinkNum, FLAG)
849 #define LmARP2INTCTL(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ARP2INTCTL)
851 #define LmSTACK(LinkNum) LmSEQ_PHY_REG(0, LinkNum, STACK)
853 #define LmFUNCTION1(LinkNum) LmSEQ_PHY_REG(0, LinkNum, FUNCTION1)
855 #define LmPRGMCNT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, PRGMCNT)
857 #define LmACCUM(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ACCUM)
859 #define LmSINDEX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, SINDEX)
861 #define LmDINDEX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DINDEX)
863 #define LmALLONES(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ALLONES)
865 #define LmALLZEROS(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ALLZEROS)
867 #define LmSINDIR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, SINDIR)
869 #define LmDINDIR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DINDIR)
871 #define LmJUMLDIR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, JUMLDIR)
873 #define LmARP2HALTCODE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ARP2HALTCODE)
875 #define LmCURRADDR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, CURRADDR)
877 #define LmLASTADDR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, LASTADDR)
879 #define LmNXTLADDR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, NXTLADDR)
881 #define LmDBGPORTPTR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DBGPORTPTR)
883 #define LmDBGPORT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DBGPORT)
885 #define LmSCRATCHPAGE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, SCRATCHPAGE)
890 #define LmTIMERCALC(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x28)
892 #define LmREQMBX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x30)
894 #define LmRSPMBX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x34)
896 #define LmMnINT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x38)
898 #define CTXMEMSIZE 0x80000000 /* ro */
899 #define LmACKREQ 0x08000000
900 #define LmNAKREQ 0x04000000
901 #define LmMnXMTERR 0x02000000
902 #define LmM5OOBSVC 0x01000000
903 #define LmHWTINT 0x00800000
904 #define LmMnCTXDONE 0x00100000
905 #define LmM2REQMBXF 0x00080000
906 #define LmM2RSPMBXE 0x00040000
907 #define LmMnDMAERR 0x00020000
908 #define LmRCVPRIM 0x00010000
909 #define LmRCVERR 0x00008000
910 #define LmADDRRCV 0x00004000
911 #define LmMnHDRMISS 0x00002000
912 #define LmMnWAITSCB 0x00001000
913 #define LmMnRLSSCB 0x00000800
914 #define LmMnSAVECTX 0x00000400
915 #define LmMnFETCHSG 0x00000200
916 #define LmMnLOADCTX 0x00000100
917 #define LmMnCFGICL 0x00000080
918 #define LmMnCFGSATA 0x00000040
919 #define LmMnCFGEXPSATA 0x00000020
920 #define LmMnCFGCMPLT 0x00000010
921 #define LmMnCFGRBUF 0x00000008
922 #define LmMnSAVETTR 0x00000004
923 #define LmMnCFGRDAT 0x00000002
924 #define LmMnCFGHDR 0x00000001
926 #define LmMnINTEN(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x3C)
928 #define EN_LmACKREQ 0x08000000
929 #define EN_LmNAKREQ 0x04000000
930 #define EN_LmMnXMTERR 0x02000000
931 #define EN_LmM5OOBSVC 0x01000000
932 #define EN_LmHWTINT 0x00800000
933 #define EN_LmMnCTXDONE 0x00100000
934 #define EN_LmM2REQMBXF 0x00080000
935 #define EN_LmM2RSPMBXE 0x00040000
936 #define EN_LmMnDMAERR 0x00020000
937 #define EN_LmRCVPRIM 0x00010000
938 #define EN_LmRCVERR 0x00008000
939 #define EN_LmADDRRCV 0x00004000
940 #define EN_LmMnHDRMISS 0x00002000
941 #define EN_LmMnWAITSCB 0x00001000
942 #define EN_LmMnRLSSCB 0x00000800
943 #define EN_LmMnSAVECTX 0x00000400
944 #define EN_LmMnFETCHSG 0x00000200
945 #define EN_LmMnLOADCTX 0x00000100
946 #define EN_LmMnCFGICL 0x00000080
947 #define EN_LmMnCFGSATA 0x00000040
948 #define EN_LmMnCFGEXPSATA 0x00000020
949 #define EN_LmMnCFGCMPLT 0x00000010
950 #define EN_LmMnCFGRBUF 0x00000008
951 #define EN_LmMnSAVETTR 0x00000004
952 #define EN_LmMnCFGRDAT 0x00000002
953 #define EN_LmMnCFGHDR 0x00000001
980 #define LmXMTPRIMD(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x40)
982 #define LmXMTPRIMCS(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x44)
984 #define LmCONSTAT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x45)
986 #define LmMnDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x46)
988 #define LmMnSGDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x47)
990 #define LmM0EXPHDRP(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x48)
992 #define LmM1SASALIGN(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x48)
993 #define SAS_ALIGN_DEFAULT 0xFF
995 #define LmM0MSKHDRP(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x49)
997 #define LmM1STPALIGN(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x49)
998 #define STP_ALIGN_DEFAULT 0x1F
1000 #define LmM0RCVHDRP(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x4A)
1002 #define LmM1XMTHDRP(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x4A)
1004 #define LmM0ICLADR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x4B)
1006 #define LmM1ALIGNMODE(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x4B)
1008 #define LmDISALIGN 0x20
1009 #define LmROTSTPALIGN 0x10
1010 #define LmSTPALIGN 0x08
1011 #define LmROTNOTIFY 0x04
1012 #define LmDUALALIGN 0x02
1013 #define LmROTALIGN 0x01
1015 #define LmM0EXPRCVNT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x4C)
1017 #define LmM1XMTCNT(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x4C)
1019 #define LmMnBUFSTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x4E)
1021 #define LmMnBUFPERR 0x01
1023 /* mode 0-1 */
1024 #define LmMnXFRLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x59)
1026 #define LmMnXFRLVL_128 0x05
1027 #define LmMnXFRLVL_256 0x04
1028 #define LmMnXFRLVL_512 0x03
1029 #define LmMnXFRLVL_1024 0x02
1030 #define LmMnXFRLVL_1536 0x01
1031 #define LmMnXFRLVL_2048 0x00
1033 /* mode 0-1 */
1034 #define LmMnSGDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5A)
1036 #define LmMnRESETSG 0x04
1037 #define LmMnSTOPSG 0x02
1038 #define LmMnSTARTSG 0x01
1040 /* mode 0-1 */
1041 #define LmMnSGDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5B)
1043 /* mode 0-1 */
1044 #define LmMnDDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5C)
1046 #define LmMnFLUSH 0x40 /* wo */
1047 #define LmMnRLSRTRY 0x20 /* wo */
1048 #define LmMnDISCARD 0x10 /* wo */
1049 #define LmMnRESETDAT 0x08 /* wo */
1050 #define LmMnSUSDAT 0x04 /* wo */
1051 #define LmMnSTOPDAT 0x02 /* wo */
1052 #define LmMnSTARTDAT 0x01 /* wo */
1054 /* mode 0-1 */
1055 #define LmMnDDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5D)
1057 #define LmMnDPEMPTY 0x80
1058 #define LmMnFLUSHING 0x40
1059 #define LmMnDDMAREQ 0x20
1060 #define LmMnHDMAREQ 0x10
1061 #define LmMnDATFREE 0x08
1062 #define LmMnDATSUS 0x04
1063 #define LmMnDATACT 0x02
1064 #define LmMnDATEN 0x01
1066 /* mode 0-1 */
1067 #define LmMnDDMAMODE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5E)
1069 #define LmMnDMATYPE_NORMAL 0x0000
1070 #define LmMnDMATYPE_HOST_ONLY_TX 0x0001
1071 #define LmMnDMATYPE_DEVICE_ONLY_TX 0x0002
1072 #define LmMnDMATYPE_INVALID 0x0003
1073 #define LmMnDMATYPE_MASK 0x0003
1075 #define LmMnDMAWRAP 0x0004
1076 #define LmMnBITBUCKET 0x0008
1077 #define LmMnDISHDR 0x0010
1078 #define LmMnSTPCRC 0x0020
1079 #define LmXTEST 0x0040
1080 #define LmMnDISCRC 0x0080
1081 #define LmMnENINTLK 0x0100
1082 #define LmMnADDRFRM 0x0400
1083 #define LmMnENXMTCRC 0x0800
1085 /* mode 0-1 */
1086 #define LmMnXFRCNT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x70)
1088 /* mode 0-1 */
1089 #define LmMnDPSEL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7B)
1090 #define LmMnDPSEL_MASK 0x07
1091 #define LmMnEOLPRE 0x40
1092 #define LmMnEOSPRE 0x80
1095 /* Receive Mode n = 0 */
1096 #define LmMnHRADDR 0x00
1097 #define LmMnHBYTECNT 0x01
1098 #define LmMnHREWIND 0x02
1099 #define LmMnDWADDR 0x03
1100 #define LmMnDSPACECNT 0x04
1101 #define LmMnDFRMSIZE 0x05
1105 #define LmMnHWADDR 0x00
1106 #define LmMnHSPACECNT 0x01
1107 /* #define LmMnHREWIND 0x02 */
1108 #define LmMnDRADDR 0x03
1109 #define LmMnDBYTECNT 0x04
1110 /* #define LmMnDFRMSIZE 0x05 */
1112 /* mode 0-1 */
1113 #define LmMnDPACC(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x78)
1114 #define LmMnDPACC_MASK 0x00FFFFFF
1116 /* mode 0-1 */
1117 #define LmMnHOLDLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7D)
1119 #define LmPRMSTAT0(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x80)
1120 #define LmPRMSTAT0BYTE0 0x80
1121 #define LmPRMSTAT0BYTE1 0x81
1122 #define LmPRMSTAT0BYTE2 0x82
1123 #define LmPRMSTAT0BYTE3 0x83
1125 #define LmFRAMERCVD 0x80000000
1126 #define LmXFRRDYRCVD 0x40000000
1127 #define LmUNKNOWNP 0x20000000
1128 #define LmBREAK 0x10000000
1129 #define LmDONE 0x08000000
1130 #define LmOPENACPT 0x04000000
1131 #define LmOPENRJCT 0x02000000
1132 #define LmOPENRTRY 0x01000000
1133 #define LmCLOSERV1 0x00800000
1134 #define LmCLOSERV0 0x00400000
1135 #define LmCLOSENORM 0x00200000
1136 #define LmCLOSECLAF 0x00100000
1137 #define LmNOTIFYRV2 0x00080000
1138 #define LmNOTIFYRV1 0x00040000
1139 #define LmNOTIFYRV0 0x00020000
1140 #define LmNOTIFYSPIN 0x00010000
1141 #define LmBROADRV4 0x00008000
1142 #define LmBROADRV3 0x00004000
1143 #define LmBROADRV2 0x00002000
1144 #define LmBROADRV1 0x00001000
1145 #define LmBROADSES 0x00000800
1146 #define LmBROADRVCH1 0x00000400
1147 #define LmBROADRVCH0 0x00000200
1148 #define LmBROADCH 0x00000100
1149 #define LmAIPRVWP 0x00000080
1150 #define LmAIPWP 0x00000040
1151 #define LmAIPWD 0x00000020
1152 #define LmAIPWC 0x00000010
1153 #define LmAIPRV2 0x00000008
1154 #define LmAIPRV1 0x00000004
1155 #define LmAIPRV0 0x00000002
1156 #define LmAIPNRML 0x00000001
1161 #define LmPRMSTAT1(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x84)
1162 #define LmPRMSTAT1BYTE0 0x84
1163 #define LmPRMSTAT1BYTE1 0x85
1164 #define LmPRMSTAT1BYTE2 0x86
1165 #define LmPRMSTAT1BYTE3 0x87
1167 #define LmFRMRCVDSTAT 0x80000000
1168 #define LmBREAK_DET 0x04000000
1169 #define LmCLOSE_DET 0x02000000
1170 #define LmDONE_DET 0x01000000
1171 #define LmXRDY 0x00040000
1172 #define LmSYNCSRST 0x00020000
1173 #define LmSYNC 0x00010000
1174 #define LmXHOLD 0x00008000
1175 #define LmRRDY 0x00004000
1176 #define LmHOLD 0x00002000
1177 #define LmROK 0x00001000
1178 #define LmRIP 0x00000800
1179 #define LmCRBLK 0x00000400
1180 #define LmACK 0x00000200
1181 #define LmNAK 0x00000100
1182 #define LmHARDRST 0x00000080
1183 #define LmERROR 0x00000040
1184 #define LmRERR 0x00000020
1185 #define LmPMREQP 0x00000010
1186 #define LmPMREQS 0x00000008
1187 #define LmPMACK 0x00000004
1188 #define LmPMNAK 0x00000002
1189 #define LmDMAT 0x00000001
1192 #define LmMnSATAFS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7E)
1193 #define LmMnXMTSIZE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x93)
1195 /* mode 0 */
1196 #define LmMnFRMERR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xB0)
1198 #define LmACRCERR 0x00000800
1199 #define LmPHYOVRN 0x00000400
1200 #define LmOBOVRN 0x00000200
1201 #define LmMnZERODATA 0x00000100
1202 #define LmSATAINTLK 0x00000080
1203 #define LmMnCRCERR 0x00000020
1204 #define LmRRDYOVRN 0x00000010
1205 #define LmMISSSOAF 0x00000008
1206 #define LmMISSSOF 0x00000004
1207 #define LmMISSEOAF 0x00000002
1208 #define LmMISSEOF 0x00000001
1210 #define LmFRMERREN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xB4)
1212 #define EN_LmACRCERR 0x00000800
1213 #define EN_LmPHYOVRN 0x00000400
1214 #define EN_LmOBOVRN 0x00000200
1215 #define EN_LmMnZERODATA 0x00000100
1216 #define EN_LmSATAINTLK 0x00000080
1217 #define EN_LmFRMBAD 0x00000040
1218 #define EN_LmMnCRCERR 0x00000020
1219 #define EN_LmRRDYOVRN 0x00000010
1220 #define EN_LmMISSSOAF 0x00000008
1221 #define EN_LmMISSSOF 0x00000004
1222 #define EN_LmMISSEOAF 0x00000002
1223 #define EN_LmMISSEOF 0x00000001
1231 #define LmHWTSTATEN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xC5)
1233 #define EN_LmDONETO 0x80
1234 #define EN_LmINVDISP 0x40
1235 #define EN_LmINVDW 0x20
1236 #define EN_LmDWSEVENT 0x08
1237 #define EN_LmCRTTTO 0x04
1238 #define EN_LmANTTTO 0x02
1239 #define EN_LmBITLTTO 0x01
1246 #define LmHWTSTAT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xC7)
1248 #define LmDONETO 0x80
1249 #define LmINVDISP 0x40
1250 #define LmINVDW 0x20
1251 #define LmDWSEVENT 0x08
1252 #define LmCRTTTO 0x04
1253 #define LmANTTTO 0x02
1254 #define LmBITLTTO 0x01
1256 #define LmMnDATABUFADR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xC8)
1257 #define LmDATABUFADR_MASK 0x0FFF
1259 #define LmMnDATABUF(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xCA)
1261 #define LmPRIMSTAT0EN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xE0)
1263 #define EN_LmUNKNOWNP 0x20000000
1264 #define EN_LmBREAK 0x10000000
1265 #define EN_LmDONE 0x08000000
1266 #define EN_LmOPENACPT 0x04000000
1267 #define EN_LmOPENRJCT 0x02000000
1268 #define EN_LmOPENRTRY 0x01000000
1269 #define EN_LmCLOSERV1 0x00800000
1270 #define EN_LmCLOSERV0 0x00400000
1271 #define EN_LmCLOSENORM 0x00200000
1272 #define EN_LmCLOSECLAF 0x00100000
1273 #define EN_LmNOTIFYRV2 0x00080000
1274 #define EN_LmNOTIFYRV1 0x00040000
1275 #define EN_LmNOTIFYRV0 0x00020000
1276 #define EN_LmNOTIFYSPIN 0x00010000
1277 #define EN_LmBROADRV4 0x00008000
1278 #define EN_LmBROADRV3 0x00004000
1279 #define EN_LmBROADRV2 0x00002000
1280 #define EN_LmBROADRV1 0x00001000
1281 #define EN_LmBROADRV0 0x00000800
1282 #define EN_LmBROADRVCH1 0x00000400
1283 #define EN_LmBROADRVCH0 0x00000200
1284 #define EN_LmBROADCH 0x00000100
1285 #define EN_LmAIPRVWP 0x00000080
1286 #define EN_LmAIPWP 0x00000040
1287 #define EN_LmAIPWD 0x00000020
1288 #define EN_LmAIPWC 0x00000010
1289 #define EN_LmAIPRV2 0x00000008
1290 #define EN_LmAIPRV1 0x00000004
1291 #define EN_LmAIPRV0 0x00000002
1292 #define EN_LmAIPNRML 0x00000001
1308 #define LmPRIMSTAT1EN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xE4)
1310 #define EN_LmXRDY 0x00040000
1311 #define EN_LmSYNCSRST 0x00020000
1312 #define EN_LmSYNC 0x00010000
1313 #define EN_LmXHOLD 0x00008000
1314 #define EN_LmRRDY 0x00004000
1315 #define EN_LmHOLD 0x00002000
1316 #define EN_LmROK 0x00001000
1317 #define EN_LmRIP 0x00000800
1318 #define EN_LmCRBLK 0x00000400
1319 #define EN_LmACK 0x00000200
1320 #define EN_LmNAK 0x00000100
1321 #define EN_LmHARDRST 0x00000080
1322 #define EN_LmERROR 0x00000040
1323 #define EN_LmRERR 0x00000020
1324 #define EN_LmPMREQP 0x00000010
1325 #define EN_LmPMREQS 0x00000008
1326 #define EN_LmPMACK 0x00000004
1327 #define EN_LmPMNAK 0x00000002
1328 #define EN_LmDMAT 0x00000001
1335 #define LmSMSTATE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xE8)
1337 #define LmSMSTATEBRK(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xEC)
1339 #define LmSMDBGCTL(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xF0)
1346 #define LmM3SATATIMER(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x48)
1348 #define LmM3INTVEC0(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x90)
1350 #define LmM3INTVEC1(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x92)
1352 #define LmM3INTVEC2(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x94)
1354 #define LmM3INTVEC3(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x96)
1356 #define LmM3INTVEC4(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x98)
1358 #define LmM3INTVEC5(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x9A)
1360 #define LmM3INTVEC6(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x9C)
1362 #define LmM3INTVEC7(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x9E)
1364 #define LmM3INTVEC8(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xA4)
1366 #define LmM3INTVEC9(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xA6)
1368 #define LmM3INTVEC10(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xB0)
1370 #define LmM3FRMGAP(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xB4)
1372 #define LmBITL_TIMER(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xA2)
1374 #define LmWWN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xA8)
1383 #define OOB_BFLTR 0x100
1385 #define BFLTR_THR_MASK 0xF0
1386 #define BFLTR_TC_MASK 0x0F
1388 #define OOB_INIT_MIN 0x102
1390 #define OOB_INIT_MAX 0x104
1392 #define OOB_INIT_NEG 0x106
1394 #define OOB_SAS_MIN 0x108
1396 #define OOB_SAS_MAX 0x10A
1398 #define OOB_SAS_NEG 0x10C
1400 #define OOB_WAKE_MIN 0x10E
1402 #define OOB_WAKE_MAX 0x110
1404 #define OOB_WAKE_NEG 0x112
1406 #define OOB_IDLE_MAX 0x114
1408 #define OOB_BURST_MAX 0x116
1410 #define OOB_DATA_KBITS 0x126
1412 #define OOB_ALIGN_0_DATA 0x12C
1414 #define OOB_ALIGN_1_DATA 0x130
1416 #define D10_2_DATA_k 0x00
1417 #define SYNC_DATA_k 0x02
1418 #define ALIGN_1_DATA_k 0x04
1419 #define ALIGN_0_DATA_k 0x08
1420 #define BURST_DATA_k 0x10
1422 #define OOB_PHY_RESET_COUNT 0x13C
1424 #define OOB_SIG_GEN 0x140
1426 #define START_OOB 0x80
1427 #define START_DWS 0x40
1428 #define ALIGN_CNT3 0x30
1429 #define ALIGN_CNT2 0x20
1430 #define ALIGN_CNT1 0x10
1431 #define ALIGN_CNT4 0x00
1432 #define STOP_DWS 0x08
1433 #define SEND_COMSAS 0x04
1434 #define SEND_COMINIT 0x02
1435 #define SEND_COMWAKE 0x01
1437 #define OOB_XMIT 0x141
1439 #define TX_ENABLE 0x80
1440 #define XMIT_OOB_BURST 0x10
1441 #define XMIT_D10_2 0x08
1442 #define XMIT_SYNC 0x04
1443 #define XMIT_ALIGN_1 0x02
1444 #define XMIT_ALIGN_0 0x01
1446 #define FUNCTION_MASK 0x142
1448 #define SAS_MODE_DIS 0x80
1449 #define SATA_MODE_DIS 0x40
1450 #define SPINUP_HOLD_DIS 0x20
1451 #define HOT_PLUG_DIS 0x10
1452 #define SATA_PS_DIS 0x08
1455 #define OOB_MODE 0x143
1457 #define SAS_MODE 0x80
1458 #define SATA_MODE 0x40
1459 #define SLOW_CLK 0x20
1460 #define FORCE_XMIT_15 0x08
1461 #define PHY_SPEED_60 0x04
1462 #define PHY_SPEED_30 0x02
1463 #define PHY_SPEED_15 0x01
1465 #define CURRENT_STATUS 0x144
1467 #define CURRENT_OOB_DONE 0x80
1468 #define CURRENT_LOSS_OF_SIGNAL 0x40
1469 #define CURRENT_SPINUP_HOLD 0x20
1470 #define CURRENT_HOT_PLUG_CNCT 0x10
1471 #define CURRENT_GTO_TIMEOUT 0x08
1472 #define CURRENT_OOB_TIMEOUT 0x04
1473 #define CURRENT_DEVICE_PRESENT 0x02
1474 #define CURRENT_OOB_ERROR 0x01
1504 #define SPEED_MASK 0x145
1506 #define SATA_SPEED_30_DIS 0x10
1507 #define SATA_SPEED_15_DIS 0x08
1508 #define SAS_SPEED_60_DIS 0x04
1509 #define SAS_SPEED_30_DIS 0x02
1510 #define SAS_SPEED_15_DIS 0x01
1511 #define SAS_SPEED_MASK_DEFAULT 0x00
1513 #define OOB_TIMER_ENABLE 0x14D
1515 #define HOT_PLUG_EN 0x80
1516 #define RCD_EN 0x40
1517 #define COMTIMER_EN 0x20
1518 #define SNTT_EN 0x10
1519 #define SNLT_EN 0x04
1520 #define SNWT_EN 0x02
1521 #define ALIGN_EN 0x01
1523 #define OOB_STATUS 0x14E
1525 #define OOB_DONE 0x80
1526 #define LOSS_OF_SIGNAL 0x40 /* ro */
1527 #define SPINUP_HOLD 0x20
1528 #define HOT_PLUG_CNCT 0x10 /* ro */
1529 #define GTO_TIMEOUT 0x08 /* ro */
1530 #define OOB_TIMEOUT 0x04 /* ro */
1531 #define DEVICE_PRESENT 0x02 /* ro */
1532 #define OOB_ERROR 0x01 /* ro */
1537 #define OOB_STATUS_CLEAR 0x14F
1539 #define OOB_DONE_CLR 0x80
1540 #define LOSS_OF_SIGNAL_CLR 0x40
1541 #define SPINUP_HOLD_CLR 0x20
1542 #define HOT_PLUG_CNCT_CLR 0x10
1543 #define GTO_TIMEOUT_CLR 0x08
1544 #define OOB_TIMEOUT_CLR 0x04
1545 #define OOB_ERROR_CLR 0x01
1547 #define HOT_PLUG_DELAY 0x150
1552 #define INT_ENABLE_2 0x15A
1554 #define OOB_DONE_EN 0x80
1555 #define LOSS_OF_SIGNAL_EN 0x40
1556 #define SPINUP_HOLD_EN 0x20
1557 #define HOT_PLUG_CNCT_EN 0x10
1558 #define GTO_TIMEOUT_EN 0x08
1559 #define OOB_TIMEOUT_EN 0x04
1560 #define DEVICE_PRESENT_EN 0x02
1561 #define OOB_ERROR_EN 0x01
1563 #define PHY_CONTROL_0 0x160
1565 #define PHY_LOWPWREN_TX 0x80
1566 #define PHY_LOWPWREN_RX 0x40
1567 #define SPARE_REG_160_B5 0x20
1568 #define OFFSET_CANCEL_RX 0x10
1571 #define PHY_RXCOMCENTER_60V 0x00
1572 #define PHY_RXCOMCENTER_70V 0x04
1573 #define PHY_RXCOMCENTER_80V 0x08
1574 #define PHY_RXCOMCENTER_90V 0x0C
1575 #define PHY_RXCOMCENTER_MASK 0x0C
1577 #define PHY_RESET 0x02
1578 #define SAS_DEFAULT_SEL 0x01
1580 #define PHY_CONTROL_1 0x161
1582 /* bits 2:0 */
1583 #define SATA_PHY_DETLEVEL_50mv 0x00
1584 #define SATA_PHY_DETLEVEL_75mv 0x01
1585 #define SATA_PHY_DETLEVEL_100mv 0x02
1586 #define SATA_PHY_DETLEVEL_125mv 0x03
1587 #define SATA_PHY_DETLEVEL_150mv 0x04
1588 #define SATA_PHY_DETLEVEL_175mv 0x05
1589 #define SATA_PHY_DETLEVEL_200mv 0x06
1590 #define SATA_PHY_DETLEVEL_225mv 0x07
1591 #define SATA_PHY_DETLEVEL_MASK 0x07
1594 #define SAS_PHY_DETLEVEL_50mv 0x00
1595 #define SAS_PHY_DETLEVEL_75mv 0x08
1596 #define SAS_PHY_DETLEVEL_100mv 0x10
1597 #define SAS_PHY_DETLEVEL_125mv 0x11
1598 #define SAS_PHY_DETLEVEL_150mv 0x20
1599 #define SAS_PHY_DETLEVEL_175mv 0x21
1600 #define SAS_PHY_DETLEVEL_200mv 0x30
1601 #define SAS_PHY_DETLEVEL_225mv 0x31
1602 #define SAS_PHY_DETLEVEL_MASK 0x38
1604 #define PHY_CONTROL_2 0x162
1607 #define SATA_PHY_DRV_400mv 0x00
1608 #define SATA_PHY_DRV_450mv 0x20
1609 #define SATA_PHY_DRV_500mv 0x40
1610 #define SATA_PHY_DRV_550mv 0x60
1611 #define SATA_PHY_DRV_600mv 0x80
1612 #define SATA_PHY_DRV_650mv 0xA0
1613 #define SATA_PHY_DRV_725mv 0xC0
1614 #define SATA_PHY_DRV_800mv 0xE0
1615 #define SATA_PHY_DRV_MASK 0xE0
1618 #define SATA_PREEMP_0 0x00
1619 #define SATA_PREEMP_1 0x08
1620 #define SATA_PREEMP_2 0x10
1621 #define SATA_PREEMP_3 0x18
1622 #define SATA_PREEMP_MASK 0x18
1624 #define SATA_CMSH1P5 0x04
1626 /* bits 1:0 */
1627 #define SATA_SLEW_0 0x00
1628 #define SATA_SLEW_1 0x01
1629 #define SATA_SLEW_2 0x02
1630 #define SATA_SLEW_3 0x03
1631 #define SATA_SLEW_MASK 0x03
1633 #define PHY_CONTROL_3 0x163
1636 #define SAS_PHY_DRV_400mv 0x00
1637 #define SAS_PHY_DRV_450mv 0x20
1638 #define SAS_PHY_DRV_500mv 0x40
1639 #define SAS_PHY_DRV_550mv 0x60
1640 #define SAS_PHY_DRV_600mv 0x80
1641 #define SAS_PHY_DRV_650mv 0xA0
1642 #define SAS_PHY_DRV_725mv 0xC0
1643 #define SAS_PHY_DRV_800mv 0xE0
1644 #define SAS_PHY_DRV_MASK 0xE0
1647 #define SAS_PREEMP_0 0x00
1648 #define SAS_PREEMP_1 0x08
1649 #define SAS_PREEMP_2 0x10
1650 #define SAS_PREEMP_3 0x18
1651 #define SAS_PREEMP_MASK 0x18
1653 #define SAS_CMSH1P5 0x04
1655 /* bits 1:0 */
1656 #define SAS_SLEW_0 0x00
1657 #define SAS_SLEW_1 0x01
1658 #define SAS_SLEW_2 0x02
1659 #define SAS_SLEW_3 0x03
1660 #define SAS_SLEW_MASK 0x03
1662 #define PHY_CONTROL_4 0x168
1664 #define PHY_DONE_CAL_TX 0x80
1665 #define PHY_DONE_CAL_RX 0x40
1666 #define RX_TERM_LOAD_DIS 0x20
1667 #define TX_TERM_LOAD_DIS 0x10
1668 #define AUTO_TERM_CAL_DIS 0x08
1669 #define PHY_SIGDET_FLTR_EN 0x04
1670 #define OSC_FREQ 0x02
1671 #define PHY_START_CAL 0x01
1674 * HST_PCIX2 Registers, Address Range: (0x00-0xFC)
1676 #define PCIX_REG_BASE_ADR 0xB8040000
1678 #define PCIC_VENDOR_ID 0x00
1680 #define PCIC_DEVICE_ID 0x02
1682 #define PCIC_COMMAND 0x04
1684 #define INT_DIS 0x0400
1685 #define FBB_EN 0x0200 /* ro */
1686 #define SERR_EN 0x0100
1687 #define STEP_EN 0x0080 /* ro */
1688 #define PERR_EN 0x0040
1689 #define VGA_EN 0x0020 /* ro */
1690 #define MWI_EN 0x0010
1691 #define SPC_EN 0x0008
1692 #define MST_EN 0x0004
1693 #define MEM_EN 0x0002
1694 #define IO_EN 0x0001
1696 #define PCIC_STATUS 0x06
1698 #define PERR_DET 0x8000
1699 #define SERR_GEN 0x4000
1700 #define MABT_DET 0x2000
1701 #define TABT_DET 0x1000
1702 #define TABT_GEN 0x0800
1703 #define DPERR_DET 0x0100
1704 #define CAP_LIST 0x0010
1705 #define INT_STAT 0x0008
1707 #define PCIC_DEVREV_ID 0x08
1709 #define PCIC_CLASS_CODE 0x09
1711 #define PCIC_CACHELINE_SIZE 0x0C
1713 #define PCIC_MBAR0 0x10
1715 #define PCIC_MBAR0_OFFSET 0
1717 #define PCIC_MBAR1 0x18
1721 #define PCIC_IOBAR 0x20
1725 #define PCIC_SUBVENDOR_ID 0x2C
1727 #define PCIC_SUBSYTEM_ID 0x2E
1729 #define PCIX_STATUS 0x44
1730 #define RCV_SCE 0x20000000
1731 #define UNEXP_SC 0x00080000
1732 #define SC_DISCARD 0x00040000
1734 #define ECC_CTRL_STAT 0x48
1735 #define UNCOR_ECCERR 0x00000008
1737 #define PCIC_PM_CSR 0x5C
1739 #define PWR_STATE_D0 0
1744 #define PCIC_BASE1 0x6C /* internal use only */
1746 #define BASE1_RSVD 0xFFFFFFF8
1748 #define PCIC_BASEA 0x70 /* internal use only */
1750 #define BASEA_RSVD 0xFFFFFFC0
1751 #define BASEA_START 0
1753 #define PCIC_BASEB 0x74 /* internal use only */
1755 #define BASEB_RSVD 0xFFFFFF80
1756 #define BASEB_IOMAP_MASK 0x7F
1757 #define BASEB_START 0x80
1759 #define PCIC_BASEC 0x78 /* internal use only */
1761 #define BASEC_RSVD 0xFFFFFFFC
1762 #define BASEC_MASK 0x03
1763 #define BASEC_START 0x58
1765 #define PCIC_MBAR_KEY 0x7C /* internal use only */
1767 #define MBAR_KEY_MASK 0xFFFFFFFF
1769 #define PCIC_HSTPCIX_CNTRL 0xA0
1771 #define REWIND_DIS 0x0800
1772 #define SC_TMR_DIS 0x04000000
1774 #define PCIC_MBAR0_MASK 0xA8
1775 #define PCIC_MBAR0_SIZE_MASK 0x1FFFE000
1780 #define PCIC_FLASH_MBAR 0xB8
1782 #define PCIC_INTRPT_STAT 0xD4
1784 #define PCIC_TP_CTRL 0xFC
1787 * EXSI Registers, Address Range: (0x00-0xFC)
1791 #define EXSICNFGR (EXSI_REG_BASE_ADR + 0x00)
1793 #define OCMINITIALIZED 0x80000000
1794 #define ASIEN 0x00400000
1795 #define HCMODE 0x00200000
1796 #define PCIDEF 0x00100000
1797 #define COMSTOCK 0x00080000
1798 #define SEEPROMEND 0x00040000
1799 #define MSTTIMEN 0x00020000
1800 #define XREGEX 0x00000200
1801 #define NVRAMW 0x00000100
1802 #define NVRAMEX 0x00000080
1803 #define SRAMW 0x00000040
1804 #define SRAMEX 0x00000020
1805 #define FLASHW 0x00000010
1806 #define FLASHEX 0x00000008
1807 #define SEEPROMCFG 0x00000004
1808 #define SEEPROMTYP 0x00000002
1809 #define SEEPROMEX 0x00000001
1812 #define EXSICNTRLR (EXSI_REG_BASE_ADR + 0x04)
1814 #define MODINT_EN 0x00000001
1817 #define PMSTATR (EXSI_REG_BASE_ADR + 0x10)
1819 #define FLASHRST 0x00000002
1820 #define FLASHRDY 0x00000001
1823 #define FLCNFGR (EXSI_REG_BASE_ADR + 0x14)
1825 #define FLWEH_MASK 0x30000000
1826 #define FLWESU_MASK 0x0C000000
1827 #define FLWEPW_MASK 0x03F00000
1828 #define FLOEH_MASK 0x000C0000
1829 #define FLOESU_MASK 0x00030000
1830 #define FLOEPW_MASK 0x0000FC00
1831 #define FLCSH_MASK 0x00000300
1832 #define FLCSSU_MASK 0x000000C0
1833 #define FLCSPW_MASK 0x0000003F
1835 #define SRCNFGR (EXSI_REG_BASE_ADR + 0x18)
1837 #define SRWEH_MASK 0x30000000
1838 #define SRWESU_MASK 0x0C000000
1839 #define SRWEPW_MASK 0x03F00000
1841 #define SROEH_MASK 0x000C0000
1842 #define SROESU_MASK 0x00030000
1843 #define SROEPW_MASK 0x0000FC00
1844 #define SRCSH_MASK 0x00000300
1845 #define SRCSSU_MASK 0x000000C0
1846 #define SRCSPW_MASK 0x0000003F
1848 #define NVCNFGR (EXSI_REG_BASE_ADR + 0x1C)
1850 #define NVWEH_MASK 0x30000000
1851 #define NVWESU_MASK 0x0C000000
1852 #define NVWEPW_MASK 0x03F00000
1853 #define NVOEH_MASK 0x000C0000
1854 #define NVOESU_MASK 0x00030000
1855 #define NVOEPW_MASK 0x0000FC00
1856 #define NVCSH_MASK 0x00000300
1857 #define NVCSSU_MASK 0x000000C0
1858 #define NVCSPW_MASK 0x0000003F
1860 #define XRCNFGR (EXSI_REG_BASE_ADR + 0x20)
1862 #define XRWEH_MASK 0x30000000
1863 #define XRWESU_MASK 0x0C000000
1864 #define XRWEPW_MASK 0x03F00000
1865 #define XROEH_MASK 0x000C0000
1866 #define XROESU_MASK 0x00030000
1867 #define XROEPW_MASK 0x0000FC00
1868 #define XRCSH_MASK 0x00000300
1869 #define XRCSSU_MASK 0x000000C0
1870 #define XRCSPW_MASK 0x0000003F
1872 #define XREGADDR (EXSI_REG_BASE_ADR + 0x24)
1874 #define XRADDRINCEN 0x80000000
1875 #define XREGADD_MASK 0x007FFFFF
1878 #define XREGDATAR (EXSI_REG_BASE_ADR + 0x28)
1880 #define XREGDATA_MASK 0x0000FFFF
1882 #define GPIOOER (EXSI_REG_BASE_ADR + 0x40)
1884 #define GPIOODENR (EXSI_REG_BASE_ADR + 0x44)
1886 #define GPIOINVR (EXSI_REG_BASE_ADR + 0x48)
1888 #define GPIODATAOR (EXSI_REG_BASE_ADR + 0x4C)
1890 #define GPIODATAIR (EXSI_REG_BASE_ADR + 0x50)
1892 #define GPIOCNFGR (EXSI_REG_BASE_ADR + 0x54)
1894 #define GPIO_EXTSRC 0x00000001
1896 #define SCNTRLR (EXSI_REG_BASE_ADR + 0xA0)
1898 #define SXFERDONE 0x00000100
1899 #define SXFERCNT_MASK 0x000000E0
1900 #define SCMDTYP_MASK 0x0000001C
1901 #define SXFERSTART 0x00000002
1902 #define SXFEREN 0x00000001
1904 #define SRATER (EXSI_REG_BASE_ADR + 0xA4)
1906 #define SADDRR (EXSI_REG_BASE_ADR + 0xA8)
1908 #define SADDR_MASK 0x0000FFFF
1910 #define SDATAOR (EXSI_REG_BASE_ADR + 0xAC)
1912 #define SDATAOR0 (EXSI_REG_BASE_ADR + 0xAC)
1913 #define SDATAOR1 (EXSI_REG_BASE_ADR + 0xAD)
1914 #define SDATAOR2 (EXSI_REG_BASE_ADR + 0xAE)
1915 #define SDATAOR3 (EXSI_REG_BASE_ADR + 0xAF)
1917 #define SDATAIR (EXSI_REG_BASE_ADR + 0xB0)
1919 #define SDATAIR0 (EXSI_REG_BASE_ADR + 0xB0)
1920 #define SDATAIR1 (EXSI_REG_BASE_ADR + 0xB1)
1921 #define SDATAIR2 (EXSI_REG_BASE_ADR + 0xB2)
1922 #define SDATAIR3 (EXSI_REG_BASE_ADR + 0xB3)
1924 #define ASISTAT0R (EXSI_REG_BASE_ADR + 0xD0)
1925 #define ASIFMTERR 0x00000400
1926 #define ASISEECHKERR 0x00000200
1927 #define ASIERR 0x00000100
1929 #define ASISTAT1R (EXSI_REG_BASE_ADR + 0xD4)
1930 #define CHECKSUM_MASK 0x0000FFFF
1932 #define ASIERRADDR (EXSI_REG_BASE_ADR + 0xD8)
1933 #define ASIERRDATAR (EXSI_REG_BASE_ADR + 0xDC)
1934 #define ASIERRSTATR (EXSI_REG_BASE_ADR + 0xE0)
1935 #define CPI2ASIBYTECNT_MASK 0x00070000
1936 #define CPI2ASIBYTEEN_MASK 0x0000F000
1937 #define CPI2ASITARGERR_MASK 0x00000F00
1938 #define CPI2ASITARGMID_MASK 0x000000F0
1939 #define CPI2ASIMSTERR_MASK 0x0000000F
1944 #define XSRAM_REG_BASE_ADDR 0xB8100000
1945 #define XSRAM_SIZE 0x100000
1948 * NVRAM Registers, Address Range: (0x00000 - 0x3FFFF).
1950 #define NVRAM_REG_BASE_ADR 0xBF800000
1951 #define NVRAM_MAX_BASE_ADR 0x003FFFFF
1954 #define OCM_BASE_ADDR 0xA0000000
1955 #define OCM_MAX_SIZE 0x20000
1966 * (three 32 byte pages 0-2, not contiguous), leaving 128 bytes of
1968 * dependent scratch memory, Mode 8, page 0-3 overlaps mode
1969 * independent scratch memory, pages 0-3.
1970 * - 896 bytes of mode dependent scratch, 96 bytes per Modes 0-7, and
1972 * - 259 bytes of mode independent scratch, common to modes 0-15.
1978 * dependent scratch memory for modes 0-7 (768 bytes). Mode 8 pages
1979 * 0-2 dependent scratch overlap with pages 0-2 of mode independent
1991 * 800h-83Fh Mode Dependent Scratch Mode 0 Pages 0-1
1992 * 840h-87Fh Mode Dependent Scratch Mode 1 Pages 0-1
1993 * 880h-8BFh Mode Dependent Scratch Mode 2 Pages 0-1
1994 * 8C0h-8FFh Mode Dependent Scratch Mode 3 Pages 0-1
1995 * 900h-93Fh Mode Dependent Scratch Mode 4 Pages 0-1
1996 * 940h-97Fh Mode Dependent Scratch Mode 5 Pages 0-1
1997 * 980h-9BFh Mode Dependent Scratch Mode 6 Pages 0-1
1998 * 9C0h-9FFh Mode Dependent Scratch Mode 7 Pages 0-1
1999 * A00h-A5Fh Mode Dependent Scratch Mode 8 Pages 0-2
2000 * Mode Independent Scratch Pages 0-2
2004 * B00h-B1Fh Mode Dependent Scratch Mode 0 Page 2
2017 /* All macros start with offsets from base + 0x800 (CMAPPEDSCR).
2018 * Mode dependent scratch page 0, mode 0.
2020 #define CSEQ_LRM_SAVE_SINDEX (CMAPPEDSCR + 0x0000)
2021 #define CSEQ_LRM_SAVE_SCBPTR (CMAPPEDSCR + 0x0002)
2022 #define CSEQ_Q_LINK_HEAD (CMAPPEDSCR + 0x0004)
2023 #define CSEQ_Q_LINK_TAIL (CMAPPEDSCR + 0x0006)
2024 #define CSEQ_LRM_SAVE_SCRPAGE (CMAPPEDSCR + 0x0008)
2026 /* Mode dependent scratch page 0 mode 8 macros. */
2027 #define CSEQ_RET_ADDR (CMAPPEDSCR + 0x0200)
2028 #define CSEQ_RET_SCBPTR (CMAPPEDSCR + 0x0202)
2029 #define CSEQ_SAVE_SCBPTR (CMAPPEDSCR + 0x0204)
2030 #define CSEQ_EMPTY_TRANS_CTX (CMAPPEDSCR + 0x0206)
2031 #define CSEQ_RESP_LEN (CMAPPEDSCR + 0x0208)
2032 #define CSEQ_TMF_SCBPTR (CMAPPEDSCR + 0x020A)
2033 #define CSEQ_GLOBAL_PREV_SCB (CMAPPEDSCR + 0x020C)
2034 #define CSEQ_GLOBAL_HEAD (CMAPPEDSCR + 0x020E)
2035 #define CSEQ_CLEAR_LU_HEAD (CMAPPEDSCR + 0x0210)
2036 #define CSEQ_TMF_OPCODE (CMAPPEDSCR + 0x0212)
2037 #define CSEQ_SCRATCH_FLAGS (CMAPPEDSCR + 0x0213)
2038 #define CSEQ_HSB_SITE (CMAPPEDSCR + 0x021A)
2039 #define CSEQ_FIRST_INV_SCB_SITE (CMAPPEDSCR + 0x021C)
2040 #define CSEQ_FIRST_INV_DDB_SITE (CMAPPEDSCR + 0x021E)
2043 #define CSEQ_LUN_TO_CLEAR (CMAPPEDSCR + 0x0220)
2044 #define CSEQ_LUN_TO_CHECK (CMAPPEDSCR + 0x0228)
2047 #define CSEQ_HQ_NEW_POINTER (CMAPPEDSCR + 0x0240)
2048 #define CSEQ_HQ_DONE_BASE (CMAPPEDSCR + 0x0248)
2049 #define CSEQ_HQ_DONE_POINTER (CMAPPEDSCR + 0x0250)
2050 #define CSEQ_HQ_DONE_PASS (CMAPPEDSCR + 0x0254)
2053 #define CSEQ_Q_EXE_HEAD (CMAPPEDSCR + 0x0280)
2054 #define CSEQ_Q_EXE_TAIL (CMAPPEDSCR + 0x0282)
2055 #define CSEQ_Q_DONE_HEAD (CMAPPEDSCR + 0x0284)
2056 #define CSEQ_Q_DONE_TAIL (CMAPPEDSCR + 0x0286)
2057 #define CSEQ_Q_SEND_HEAD (CMAPPEDSCR + 0x0288)
2058 #define CSEQ_Q_SEND_TAIL (CMAPPEDSCR + 0x028A)
2059 #define CSEQ_Q_DMA2CHIM_HEAD (CMAPPEDSCR + 0x028C)
2060 #define CSEQ_Q_DMA2CHIM_TAIL (CMAPPEDSCR + 0x028E)
2061 #define CSEQ_Q_COPY_HEAD (CMAPPEDSCR + 0x0290)
2062 #define CSEQ_Q_COPY_TAIL (CMAPPEDSCR + 0x0292)
2063 #define CSEQ_REG0 (CMAPPEDSCR + 0x0294)
2064 #define CSEQ_REG1 (CMAPPEDSCR + 0x0296)
2065 #define CSEQ_REG2 (CMAPPEDSCR + 0x0298)
2066 #define CSEQ_LINK_CTL_Q_MAP (CMAPPEDSCR + 0x029C)
2067 #define CSEQ_MAX_CSEQ_MODE (CMAPPEDSCR + 0x029D)
2068 #define CSEQ_FREE_LIST_HACK_COUNT (CMAPPEDSCR + 0x029E)
2071 #define CSEQ_EST_NEXUS_REQ_QUEUE (CMAPPEDSCR + 0x02A0)
2072 #define CSEQ_EST_NEXUS_REQ_COUNT (CMAPPEDSCR + 0x02A8)
2073 #define CSEQ_Q_EST_NEXUS_HEAD (CMAPPEDSCR + 0x02B0)
2074 #define CSEQ_Q_EST_NEXUS_TAIL (CMAPPEDSCR + 0x02B2)
2075 #define CSEQ_NEED_EST_NEXUS_SCB (CMAPPEDSCR + 0x02B4)
2076 #define CSEQ_EST_NEXUS_REQ_HEAD (CMAPPEDSCR + 0x02B6)
2077 #define CSEQ_EST_NEXUS_REQ_TAIL (CMAPPEDSCR + 0x02B7)
2078 #define CSEQ_EST_NEXUS_SCB_OFFSET (CMAPPEDSCR + 0x02B8)
2081 #define CSEQ_INT_ROUT_RET_ADDR0 (CMAPPEDSCR + 0x02C0)
2082 #define CSEQ_INT_ROUT_RET_ADDR1 (CMAPPEDSCR + 0x02C2)
2083 #define CSEQ_INT_ROUT_SCBPTR (CMAPPEDSCR + 0x02C4)
2084 #define CSEQ_INT_ROUT_MODE (CMAPPEDSCR + 0x02C6)
2085 #define CSEQ_ISR_SCRATCH_FLAGS (CMAPPEDSCR + 0x02C7)
2086 #define CSEQ_ISR_SAVE_SINDEX (CMAPPEDSCR + 0x02C8)
2087 #define CSEQ_ISR_SAVE_DINDEX (CMAPPEDSCR + 0x02CA)
2088 #define CSEQ_Q_MONIRTT_HEAD (CMAPPEDSCR + 0x02D0)
2089 #define CSEQ_Q_MONIRTT_TAIL (CMAPPEDSCR + 0x02D2)
2090 #define CSEQ_FREE_SCB_MASK (CMAPPEDSCR + 0x02D5)
2091 #define CSEQ_BUILTIN_FREE_SCB_HEAD (CMAPPEDSCR + 0x02D6)
2092 #define CSEQ_BUILTIN_FREE_SCB_TAIL (CMAPPEDSCR + 0x02D8)
2093 #define CSEQ_EXTENDED_FREE_SCB_HEAD (CMAPPEDSCR + 0x02DA)
2094 #define CSEQ_EXTENDED_FREE_SCB_TAIL (CMAPPEDSCR + 0x02DC)
2097 #define CSEQ_EMPTY_REQ_QUEUE (CMAPPEDSCR + 0x02E0)
2098 #define CSEQ_EMPTY_REQ_COUNT (CMAPPEDSCR + 0x02E8)
2099 #define CSEQ_Q_EMPTY_HEAD (CMAPPEDSCR + 0x02F0)
2100 #define CSEQ_Q_EMPTY_TAIL (CMAPPEDSCR + 0x02F2)
2101 #define CSEQ_NEED_EMPTY_SCB (CMAPPEDSCR + 0x02F4)
2102 #define CSEQ_EMPTY_REQ_HEAD (CMAPPEDSCR + 0x02F6)
2103 #define CSEQ_EMPTY_REQ_TAIL (CMAPPEDSCR + 0x02F7)
2104 #define CSEQ_EMPTY_SCB_OFFSET (CMAPPEDSCR + 0x02F8)
2105 #define CSEQ_PRIMITIVE_DATA (CMAPPEDSCR + 0x02FA)
2106 #define CSEQ_TIMEOUT_CONST (CMAPPEDSCR + 0x02FC)
2114 * memory for modes 0-2 (384 bytes).
2125 * 800h-85Fh Mode Dependent Scratch Mode 0 Pages 0-2
2126 * 860h-87Fh Mode Dependent Scratch Mode 0 Page 3
2127 * Mode Dependent Scratch Mode 5 Page 0
2128 * 880h-8DFh Mode Dependent Scratch Mode 1 Pages 0-2
2131 * 900h-95Fh Mode Dependent Scratch Mode 2 Pages 0-2
2134 * 980h-9DFh Mode Independent Scratch Pages 0-3
2140 #define LSEQ_MODE_SCRATCH_SIZE 0x80 /* Size of scratch RAM per mode */
2141 #define LSEQ_PAGE_SIZE 0x20 /* Scratch page size (in bytes) */
2142 #define LSEQ_MODE5_PAGE0_OFFSET 0x60
2144 /* Common mode dependent scratch page 0 macros for modes 0,1,2, and 5 */
2145 /* Indexed using LSEQ_MODE_SCRATCH_SIZE * mode, for modes 0,1,2. */
2146 #define LmSEQ_RET_ADDR(LinkNum) (LmSCRATCH(LinkNum) + 0x0000)
2147 #define LmSEQ_REG0_MODE(LinkNum) (LmSCRATCH(LinkNum) + 0x0002)
2148 #define LmSEQ_MODE_FLAGS(LinkNum) (LmSCRATCH(LinkNum) + 0x0004)
2150 /* Mode flag macros (byte 0) */
2151 #define SAS_SAVECTX_OCCURRED 0x80
2152 #define SAS_OOBSVC_OCCURRED 0x40
2153 #define SAS_OOB_DEVICE_PRESENT 0x20
2154 #define SAS_CFGHDR_OCCURRED 0x10
2155 #define SAS_RCV_INTS_ARE_DISABLED 0x08
2156 #define SAS_OOB_HOT_PLUG_CNCT 0x04
2157 #define SAS_AWAIT_OPEN_CONNECTION 0x02
2158 #define SAS_CFGCMPLT_OCCURRED 0x01
2161 #define SAS_RLSSCB_OCCURRED 0x80
2162 #define SAS_FORCED_HEADER_MISS 0x40
2164 #define LmSEQ_RET_ADDR2(LinkNum) (LmSCRATCH(LinkNum) + 0x0006)
2165 #define LmSEQ_RET_ADDR1(LinkNum) (LmSCRATCH(LinkNum) + 0x0008)
2166 #define LmSEQ_OPCODE_TO_CSEQ(LinkNum) (LmSCRATCH(LinkNum) + 0x000B)
2167 #define LmSEQ_DATA_TO_CSEQ(LinkNum) (LmSCRATCH(LinkNum) + 0x000C)
2169 /* Mode dependent scratch page 0 macros for mode 0 (non-common) */
2171 #define LmSEQ_FIRST_INV_DDB_SITE(LinkNum) (LmSCRATCH(LinkNum) + 0x000E)
2172 #define LmSEQ_EMPTY_TRANS_CTX(LinkNum) (LmSCRATCH(LinkNum) + 0x0010)
2173 #define LmSEQ_RESP_LEN(LinkNum) (LmSCRATCH(LinkNum) + 0x0012)
2174 #define LmSEQ_FIRST_INV_SCB_SITE(LinkNum) (LmSCRATCH(LinkNum) + 0x0014)
2175 #define LmSEQ_INTEN_SAVE(LinkNum) (LmSCRATCH(LinkNum) + 0x0016)
2176 #define LmSEQ_LINK_RST_FRM_LEN(LinkNum) (LmSCRATCH(LinkNum) + 0x001A)
2177 #define LmSEQ_LINK_RST_PROTOCOL(LinkNum) (LmSCRATCH(LinkNum) + 0x001B)
2178 #define LmSEQ_RESP_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x001C)
2179 #define LmSEQ_LAST_LOADED_SGE(LinkNum) (LmSCRATCH(LinkNum) + 0x001D)
2180 #define LmSEQ_SAVE_SCBPTR(LinkNum) (LmSCRATCH(LinkNum) + 0x001E)
2182 /* Mode dependent scratch page 0 macros for mode 1 (non-common) */
2184 #define LmSEQ_Q_XMIT_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x008E)
2185 #define LmSEQ_M1_EMPTY_TRANS_CTX(LinkNum) (LmSCRATCH(LinkNum) + 0x0090)
2186 #define LmSEQ_INI_CONN_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x0092)
2187 #define LmSEQ_FAILED_OPEN_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x009A)
2188 #define LmSEQ_XMIT_REQUEST_TYPE(LinkNum) (LmSCRATCH(LinkNum) + 0x009B)
2189 #define LmSEQ_M1_RESP_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x009C)
2190 #define LmSEQ_M1_LAST_LOADED_SGE(LinkNum) (LmSCRATCH(LinkNum) + 0x009D)
2191 #define LmSEQ_M1_SAVE_SCBPTR(LinkNum) (LmSCRATCH(LinkNum) + 0x009E)
2193 /* Mode dependent scratch page 0 macros for mode 2 (non-common) */
2194 #define LmSEQ_PORT_COUNTER(LinkNum) (LmSCRATCH(LinkNum) + 0x010E)
2195 #define LmSEQ_PM_TABLE_PTR(LinkNum) (LmSCRATCH(LinkNum) + 0x0110)
2196 #define LmSEQ_SATA_INTERLOCK_TMR_SAVE(LinkNum) (LmSCRATCH(LinkNum) + 0x0112)
2197 #define LmSEQ_IP_BITL(LinkNum) (LmSCRATCH(LinkNum) + 0x0114)
2198 #define LmSEQ_COPY_SMP_CONN_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x0116)
2199 #define LmSEQ_P0M2_OFFS1AH(LinkNum) (LmSCRATCH(LinkNum) + 0x011A)
2201 /* Mode dependent scratch page 0 macros for modes 4/5 (non-common) */
2203 #define LmSEQ_SAVED_OOB_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x006E)
2204 #define LmSEQ_SAVED_OOB_MODE(LinkNum) (LmSCRATCH(LinkNum) + 0x006F)
2205 #define LmSEQ_Q_LINK_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x0070)
2206 #define LmSEQ_LINK_RST_ERR(LinkNum) (LmSCRATCH(LinkNum) + 0x0072)
2207 #define LmSEQ_SAVED_OOB_SIGNALS(LinkNum) (LmSCRATCH(LinkNum) + 0x0073)
2208 #define LmSEQ_SAS_RESET_MODE(LinkNum) (LmSCRATCH(LinkNum) + 0x0074)
2209 #define LmSEQ_LINK_RESET_RETRY_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0075)
2210 #define LmSEQ_NUM_LINK_RESET_RETRIES(LinkNum) (LmSCRATCH(LinkNum) + 0x0076)
2211 #define LmSEQ_OOB_INT_ENABLES(LinkNum) (LmSCRATCH(LinkNum) + 0x0078)
2212 #define LmSEQ_NOTIFY_TIMER_DOWN_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x007A)
2213 #define LmSEQ_NOTIFY_TIMER_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x007C)
2214 #define LmSEQ_NOTIFY_TIMER_INITIAL_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x007E)
2216 /* Mode dependent scratch page 1, mode 0 and mode 1 */
2217 #define LmSEQ_SG_LIST_PTR_ADDR0(LinkNum) (LmSCRATCH(LinkNum) + 0x0020)
2218 #define LmSEQ_SG_LIST_PTR_ADDR1(LinkNum) (LmSCRATCH(LinkNum) + 0x0030)
2219 #define LmSEQ_M1_SG_LIST_PTR_ADDR0(LinkNum) (LmSCRATCH(LinkNum) + 0x00A0)
2220 #define LmSEQ_M1_SG_LIST_PTR_ADDR1(LinkNum) (LmSCRATCH(LinkNum) + 0x00B0)
2224 #define LmSEQ_INVALID_DWORD_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0120)
2225 #define LmSEQ_DISPARITY_ERROR_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0124)
2226 #define LmSEQ_LOSS_OF_SYNC_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0128)
2229 #define LmSEQ_FRAME_TYPE_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00E0)
2230 #define LmSEQ_HASHED_DEST_ADDR_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00E1)
2231 #define LmSEQ_HASHED_SRC_ADDR_MASK_PRINT(LinkNum) (LmSCRATCH(LinkNum) + 0x00E4)
2232 #define LmSEQ_HASHED_SRC_ADDR_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00E5)
2233 #define LmSEQ_NUM_FILL_BYTES_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00EB)
2234 #define LmSEQ_TAG_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00F0)
2235 #define LmSEQ_TARGET_PORT_XFER_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x00F2)
2236 #define LmSEQ_DATA_OFFSET(LinkNum) (LmSCRATCH(LinkNum) + 0x00F4)
2238 /* Mode dependent scratch page 2 macros for mode 0 */
2240 #define LmSEQ_SMP_RCV_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0040)
2241 #define LmSEQ_DEVICE_BITS(LinkNum) (LmSCRATCH(LinkNum) + 0x005B)
2242 #define LmSEQ_SDB_DDB(LinkNum) (LmSCRATCH(LinkNum) + 0x005C)
2243 #define LmSEQ_SDB_NUM_TAGS(LinkNum) (LmSCRATCH(LinkNum) + 0x005E)
2244 #define LmSEQ_SDB_CURR_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x005F)
2248 /* byte 0 bits 1-0 are domain select. */
2249 #define LmSEQ_TX_ID_ADDR_FRAME(LinkNum) (LmSCRATCH(LinkNum) + 0x00C0)
2250 #define LmSEQ_OPEN_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x00C8)
2251 #define LmSEQ_SRST_AS_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x00CC)
2252 #define LmSEQ_LAST_LOADED_SG_EL(LinkNum) (LmSCRATCH(LinkNum) + 0x00D4)
2256 #define LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0140)
2257 #define LmSEQ_CLOSE_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0144)
2258 #define LmSEQ_BREAK_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0148)
2259 #define LmSEQ_DWS_RESET_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x014C)
2261 (LmSCRATCH(LinkNum) + 0x0150)
2262 #define LmSEQ_MCTL_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0154)
2265 #define LmSEQ_COMINIT_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0160)
2266 #define LmSEQ_RCV_ID_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0164)
2267 #define LmSEQ_RCV_FIS_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0168)
2268 #define LmSEQ_DEV_PRES_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x016C)
2270 /* Mode dependent scratch page 3 macros for modes 0 and 1 */
2276 /* Mode Independent Scratch page 0 macros. */
2277 #define LmSEQ_Q_TGTXFR_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x0180)
2278 #define LmSEQ_Q_TGTXFR_TAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x0182)
2279 #define LmSEQ_LINK_NUMBER(LinkNum) (LmSCRATCH(LinkNum) + 0x0186)
2280 #define LmSEQ_SCRATCH_FLAGS(LinkNum) (LmSCRATCH(LinkNum) + 0x0187)
2282 * Currently only bit 0, SAS_DWSAQD, is used.
2284 #define SAS_DWSAQD 0x01 /*
2288 #define LmSEQ_CONNECTION_STATE(LinkNum) (LmSCRATCH(LinkNum) + 0x0188)
2289 /* Connection states (byte 0) */
2290 #define SAS_WE_OPENED_CS 0x01
2291 #define SAS_DEVICE_OPENED_CS 0x02
2292 #define SAS_WE_SENT_DONE_CS 0x04
2293 #define SAS_DEVICE_SENT_DONE_CS 0x08
2294 #define SAS_WE_SENT_CLOSE_CS 0x10
2295 #define SAS_DEVICE_SENT_CLOSE_CS 0x20
2296 #define SAS_WE_SENT_BREAK_CS 0x40
2297 #define SAS_DEVICE_SENT_BREAK_CS 0x80
2299 #define SAS_OPN_TIMEOUT_OR_OPN_RJCT_CS 0x01
2300 #define SAS_AIP_RECEIVED_CS 0x02
2301 #define SAS_CREDIT_TIMEOUT_OCCURRED_CS 0x04
2302 #define SAS_ACKNAK_TIMEOUT_OCCURRED_CS 0x08
2303 #define SAS_SMPRSP_TIMEOUT_OCCURRED_CS 0x10
2304 #define SAS_DONE_TIMEOUT_OCCURRED_CS 0x20
2306 #define SAS_SMP_RESPONSE_RECEIVED_CS 0x01
2307 #define SAS_INTLK_TIMEOUT_OCCURRED_CS 0x02
2308 #define SAS_DEVICE_SENT_DMAT_CS 0x04
2309 #define SAS_DEVICE_SENT_SYNCSRST_CS 0x08
2310 #define SAS_CLEARING_AFFILIATION_CS 0x20
2311 #define SAS_RXTASK_ACTIVE_CS 0x40
2312 #define SAS_TXTASK_ACTIVE_CS 0x80
2314 #define SAS_PHY_LOSS_OF_SIGNAL_CS 0x01
2315 #define SAS_DWS_TIMER_EXPIRED_CS 0x02
2316 #define SAS_LINK_RESET_NOT_COMPLETE_CS 0x04
2317 #define SAS_PHY_DISABLED_CS 0x08
2318 #define SAS_LINK_CTL_TASK_ACTIVE_CS 0x10
2319 #define SAS_PHY_EVENT_TASK_ACTIVE_CS 0x20
2320 #define SAS_DEVICE_SENT_ID_FRAME_CS 0x40
2321 #define SAS_DEVICE_SENT_REG_FIS_CS 0x40
2322 #define SAS_DEVICE_SENT_HARD_RESET_CS 0x80
2333 #define LmSEQ_CONCTL(LinkNum) (LmSCRATCH(LinkNum) + 0x018C)
2334 #define LmSEQ_CONSTAT(LinkNum) (LmSCRATCH(LinkNum) + 0x018E)
2335 #define LmSEQ_CONNECTION_MODES(LinkNum) (LmSCRATCH(LinkNum) + 0x018F)
2336 #define LmSEQ_REG1_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0192)
2337 #define LmSEQ_REG2_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0194)
2338 #define LmSEQ_REG3_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0196)
2339 #define LmSEQ_REG0_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0198)
2342 #define LmSEQ_EST_NEXUS_SCBPTR0(LinkNum) (LmSCRATCH(LinkNum) + 0x01A0)
2343 #define LmSEQ_EST_NEXUS_SCBPTR1(LinkNum) (LmSCRATCH(LinkNum) + 0x01A2)
2344 #define LmSEQ_EST_NEXUS_SCBPTR2(LinkNum) (LmSCRATCH(LinkNum) + 0x01A4)
2345 #define LmSEQ_EST_NEXUS_SCBPTR3(LinkNum) (LmSCRATCH(LinkNum) + 0x01A6)
2346 #define LmSEQ_EST_NEXUS_SCB_OPCODE0(LinkNum) (LmSCRATCH(LinkNum) + 0x01A8)
2347 #define LmSEQ_EST_NEXUS_SCB_OPCODE1(LinkNum) (LmSCRATCH(LinkNum) + 0x01A9)
2348 #define LmSEQ_EST_NEXUS_SCB_OPCODE2(LinkNum) (LmSCRATCH(LinkNum) + 0x01AA)
2349 #define LmSEQ_EST_NEXUS_SCB_OPCODE3(LinkNum) (LmSCRATCH(LinkNum) + 0x01AB)
2350 #define LmSEQ_EST_NEXUS_SCB_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x01AC)
2351 #define LmSEQ_EST_NEXUS_SCB_TAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01AD)
2352 #define LmSEQ_EST_NEXUS_BUF_AVAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01AE)
2353 #define LmSEQ_TIMEOUT_CONST(LinkNum) (LmSCRATCH(LinkNum) + 0x01B8)
2354 #define LmSEQ_ISR_SAVE_SINDEX(LinkNum) (LmSCRATCH(LinkNum) + 0x01BC)
2355 #define LmSEQ_ISR_SAVE_DINDEX(LinkNum) (LmSCRATCH(LinkNum) + 0x01BE)
2358 #define LmSEQ_EMPTY_SCB_PTR0(LinkNum) (LmSCRATCH(LinkNum) + 0x01C0)
2359 #define LmSEQ_EMPTY_SCB_PTR1(LinkNum) (LmSCRATCH(LinkNum) + 0x01C2)
2360 #define LmSEQ_EMPTY_SCB_PTR2(LinkNum) (LmSCRATCH(LinkNum) + 0x01C4)
2361 #define LmSEQ_EMPTY_SCB_PTR3(LinkNum) (LmSCRATCH(LinkNum) + 0x01C6)
2362 #define LmSEQ_EMPTY_SCB_OPCD0(LinkNum) (LmSCRATCH(LinkNum) + 0x01C8)
2363 #define LmSEQ_EMPTY_SCB_OPCD1(LinkNum) (LmSCRATCH(LinkNum) + 0x01C9)
2364 #define LmSEQ_EMPTY_SCB_OPCD2(LinkNum) (LmSCRATCH(LinkNum) + 0x01CA)
2365 #define LmSEQ_EMPTY_SCB_OPCD3(LinkNum) (LmSCRATCH(LinkNum) + 0x01CB)
2366 #define LmSEQ_EMPTY_SCB_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x01CC)
2367 #define LmSEQ_EMPTY_SCB_TAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01CD)
2368 #define LmSEQ_EMPTY_BUFS_AVAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01CE)
2369 #define LmSEQ_ATA_SCR_REGS(LinkNum) (LmSCRATCH(LinkNum) + 0x01D4)
2372 #define LmSEQ_DEV_PRES_TMR_TOUT_CONST(LinkNum) (LmSCRATCH(LinkNum) + 0x01E0)
2373 #define LmSEQ_SATA_INTERLOCK_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01E4)
2374 #define LmSEQ_STP_SHUTDOWN_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01E8)
2375 #define LmSEQ_SRST_ASSERT_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01EC)
2376 #define LmSEQ_RCV_FIS_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01F0)
2377 #define LmSEQ_ONE_MILLISEC_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01F4)
2378 #define LmSEQ_TEN_MS_COMINIT_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01F8)
2379 #define LmSEQ_SMP_RCV_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01FC)