Lines Matching +full:wait +full:- +full:free +full:- +full:us
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
24 * GNU General Public License ("GPL") version 2 as published by the Free
60 * use byte 27 of the SCB as a pseudo-next pointer and to thread a list
61 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
63 * this list every time a request sense occurs or after completing a non-tagged
78 if ((ahc->features & AHC_ULTRA2) != 0) {
82 if ((ahc->features & AHC_TWIN) != 0) {
88 if ((ahc->features & AHC_TWIN) != 0) {
93 /* Has the driver posted any work for us? */
95 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
108 if ((ahc->flags & AHC_PAGESCBS) != 0) {
111 /* In the non-paging case, the SCBID == hardware SCB index */
131 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
138 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
163 * We aren't expecting a bus free, so interrupt
167 if ((ahc->features & AHC_DT) == 0) {
172 * Guard against a bus free after (re)selection
179 if ((ahc->flags & AHC_TARGETROLE) != 0) {
180 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
199 if ((ahc->features & AHC_CMD_CHAN) != 0) {
209 /* Initiator that selected us */
212 if ((ahc->features & AHC_MULTI_TID) != 0) {
214 } else if ((ahc->features & AHC_ULTRA2) != 0) {
220 if ((ahc->features & AHC_TWIN) != 0) {
224 if ((ahc->features & AHC_CMD_CHAN) != 0) {
232 * in talking to us. Go directly to bus free.
233 * XXX SCSI-1 may require us to assume lun 0 if
241 * of the SCSI-2 spec for what messages are allowed when.
251 if ((ahc->features & AHC_CMD_CHAN) != 0) {
271 add A, -MSG_SIMPLE_Q_TAG, DINDEX;
273 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
277 if ((ahc->features & AHC_CMD_CHAN) != 0) {
286 * free.
294 if ((ahc->features & AHC_CMD_CHAN) != 0) {
304 if ((ahc->features & AHC_CMD_CHAN) != 0) {
331 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
340 if ((ahc->features & AHC_ULTRA2) != 0) {
346 if ((ahc->features & AHC_TWIN) != 0) {
361 * reset), re-enable them now. Resets are only of interest
363 * defer re-enabling the interrupt until, as an initiator,
369 if ((ahc->features & AHC_TWIN) != 0) {
376 if ((ahc->features & AHC_ULTRA2) != 0) {
378 } else if ((ahc->features & AHC_TWIN) != 0) {
383 if ((ahc->flags & AHC_TARGETROLE) != 0) {
396 if ((ahc->features & AHC_ULTRA) != 0) {
403 if ((ahc->features & AHC_ULTRA2) != 0) {
409 if ((ahc->flags & AHC_TARGETROLE) != 0) {
411 * We carefully toggle SPIOEN to allow us to return the
420 /* Wait for the byte */
442 if ((ahc->flags & AHC_TARGETROLE) != 0) {
454 * We've just re-selected an initiator.
475 * Now determine what phases the host wants us
500 if ((ahc->flags & AHC_PAGESCBS) != 0) {
526 /* Wait for preceding I/O session to complete. */
530 if ((ahc->features & AHC_ULTRA2) != 0) {
544 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
561 if ((ahc->features & AHC_CMD_CHAN) != 0) {
585 if ((ahc->features & AHC_CMD_CHAN) != 0) {
622 if ((ahc->features & AHC_CMD_CHAN) != 0) {
643 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
656 * Main loop for information transfer phases. Wait for the
678 if ((ahc->features & AHC_ULTRA2) != 0) {
690 * We assume that the kernel driver may reset us
702 if ((ahc->features & AHC_ULTRA2) != 0) {
706 if ((ahc->features & AHC_ULTRA) != 0) {
721 if ((ahc->features & AHC_CMD_CHAN) != 0) {
755 * so we don't end up referencing a non-existent page.
768 if ((ahc->features & AHC_ULTRA2) != 0) {
773 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
787 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
817 adc HCNT[1], -1;
818 adc HCNT[2], -1 ret;
825 if ((ahc->features & AHC_ULTRA2) != 0) {
832 if ((ahc->features & AHC_CMD_CHAN) != 0) {
839 * If we re-enter the data phase after going through another
841 * corrupted by the interveining, non-data, transfers. Ask
842 * the host driver to fix us up based on the transfer residual.
858 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
862 if ((ahc->features & AHC_CMD_CHAN) != 0) {
871 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
876 if ((ahc->features & AHC_ULTRA2) == 0) {
877 if ((ahc->features & AHC_CMD_CHAN) != 0) {
889 * Turn on `Bit Bucket' mode, wait until the target takes
890 * us to another phase, and then notify the host.
895 if ((ahc->features & AHC_DT) == 0) {
905 if ((ahc->features & AHC_ULTRA2) != 0) {
918 if ((ahc->features & AHC_DT) == 0) {
919 if ((ahc->flags & AHC_TARGETROLE) != 0) {
926 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
943 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
945 * On chips with broken auto-flush, start
957 * allows us to update our notion of where we are
964 * another segment. This will allow us to immediately
987 * feature of the chip allows us to load two elements
998 add SCB_RESIDUAL_SGPTR[1], -1;
999 adc SCB_RESIDUAL_SGPTR[2], -1;
1000 adc SCB_RESIDUAL_SGPTR[3], -1;
1010 * requires similar restructuring for pre-ULTRA2
1015 if ((ahc->features & AHC_DT) == 0) {
1016 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
1026 * and for FIFOEMP to de-assert. Here we
1040 * We enable the auto-ack feature on DT capable
1044 * way to detect this situation is to wait for
1046 * and then test to see if the data FIFO is non-empty.
1052 * FIFOEMP can lag LAST_SEG_DONE. Wait a few
1069 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1094 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1095 && ahc->pci_cachesize != 0) {
1099 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1101 if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0) {
1111 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1121 * PHASEMIS is active). If we are doing a SCSI->Host transfer,
1122 * the data FIFO should be flushed auto-magically on STCNT=0
1123 * or a phase change, so just wait for FIFO empty status.
1149 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
1160 * Advance the scatter-gather pointers if needed
1162 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1163 && ahc->pci_cachesize != 0) {
1169 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1192 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1193 /* Wait for the idle loop to complete */
1196 test CCSGCTL, CCSGEN jnz . - 1;
1207 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1224 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1235 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1236 && ahc->pci_cachesize != 0) {
1244 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1250 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1256 * If the target has left us in data phase, loop through
1262 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1265 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1267 if ((ahc->features & AHC_DT) == 0) {
1281 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1286 if ((ahc->features & AHC_ULTRA2) == 0) {
1292 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1304 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1305 && ahc->pci_cachesize != 0) {
1306 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1315 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1320 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1334 if ((ahc->features & AHC_ULTRA2) != 0) {
1340 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1344 * For data-in phases, wait for any pending acks from the
1346 * send Ignore Wide Residue messages for data-in phases.
1363 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1372 if ((ahc->features & AHC_ULTRA2) != 0) {
1376 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1384 add NONE, -13, SCB_CDB_LEN;
1387 if ((ahc->features & AHC_ULTRA2) != 0) {
1391 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1410 if ((ahc->features & AHC_ULTRA2) != 0) {
1413 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1414 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1428 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1441 if ((ahc->features & AHC_DT) == 0) {
1443 test SSTAT1, PHASEMIS jz . - 1;
1445 * Wait for our ACK to go-away on it's own
1464 * Status phase. Wait for the data byte to appear, then read it
1478 * control byte. This will cause us to interrupt the host and allow
1488 * BDR message in response to a bad reselection would leave us pointed to
1495 * in case the target decides to put us in this phase for some strange
1500 if ((ahc->features & AHC_DT) == 0) {
1581 if ((ahc->features & AHC_WIDE) != 0) {
1610 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
1618 * Either way, the target should take us to message out phase
1635 * to mesgin to give an invalid message, let the host abort us.
1648 * See if we attempted to deliver a message but the target ingnored us.
1679 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
1686 if ((ahc->features & AHC_QUEUE_REGS) == 0) {
1691 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1693 * Is it a disconnect message? Set a flag in the SCB to remind us
1694 * and await the bus going free. If this is an untagged transaction
1703 * should take us to message out phase and then attempt to
1705 * XXX - Wait for more testing.
1711 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1731 if ((ahc->features & AHC_ULTRA2) != 0) {
1740 * transfer, just mark us at the end rather than perform a
1745 if ((ahc->features & AHC_ULTRA2) != 0) {
1759 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1761 if ((ahc->features & AHC_ULTRA2) == 0) {
1795 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1804 * Identify message? For a reconnecting target, this tells us the lun
1805 * that the reconnection is for - find the correct SCB and switch to it,
1810 * Determine whether a target is using tagged or non-tagged
1818 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1821 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1822 add NONE, -SCB_64_BTT, SINDEX;
1826 add NONE, -(SCB_64_BTT + 16), SINDEX;
1833 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1834 add NONE, -BUSY_TARGETS, SINDEX;
1838 add NONE, -(BUSY_TARGETS + 16), SINDEX;
1846 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1851 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1855 * We only allow one untagged command per-target
1861 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1875 * SCB. With SCB paging, we must search for non-tagged
1881 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1886 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1890 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1895 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1908 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1913 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1920 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1926 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1931 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1943 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1951 if ((ahc->features & AHC_DT) == 0) {
1962 * the target until SCSIDATL is read from. So we wait until SCSIDATL is
1980 * If there is a parity error, wait for the kernel to
1996 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1999 * from out to in, wait an additional data release delay before continuing.
2002 /* Wait for preceding I/O session to complete. */
2013 * we must wait at least a data release delay plus
2043 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2083 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2096 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2111 * If there is a parity error, wait for the kernel to
2118 if ((ahc->features & AHC_DT) == 0) {
2123 if ((ahc->features & AHC_CMD_CHAN) == 0) {
2150 if ((ahc->flags & AHC_TARGETROLE) != 0) {
2196 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2201 if ((ahc->flags & AHC_SCB_BTT) != 0) {
2211 if ((ahc->features & AHC_ULTRA2) == 0) {
2216 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) {
2247 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
2264 /* Wait for at least 8 bytes of data to arrive. */
2281 cmp DINDEX, A jne . - 1;
2285 add A, -SCB_BASE, DINDEX;
2325 * Wait for DMA from host memory to data FIFO to complete, then disable
2326 * DMA and wait for it to acknowledge that it's off.
2340 * If it is not in the disconnected state, it must be free.
2343 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2347 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2357 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
2364 if ((ahc->flags & AHC_PAGESCBS) != 0) {