Lines Matching +full:address +full:- +full:address +full:- +full:data
4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
76 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
95 * Controls which of the 5, 512byte, address spaces should be used
100 address 0x000
115 address 0x001
132 address 0x002
142 * Returned to data phase
143 * that requires data
187 * A command with a non-zero
212 address 0x003
230 address 0x004
246 address 0x004
262 address 0x005
280 address 0x006
291 address 0x008
301 address 0x00B
311 address 0x00C
325 address 0x00C
339 address 0x00E
349 address 0x010
360 address 0x012
371 address 0x014
382 address 0x016
411 address 0x018
424 * Data FIFO Control
427 address 0x019
448 address 0x019
453 field DPARCKEN 0x40 /* Data Parity Check Enable */
462 * Data FIFO Status
465 address 0x01A
481 address 0x01B
491 address 0x01B
504 address 0x01B
513 * Data Channel Host Address
516 address 0x070
524 * Host Overlay DMA Address
527 address 0x070
537 address 0x070
545 * Data Channel Host Count
548 address 0x078
559 address 0x078
569 address 0x07A
575 * Scatter/Gather Host Address
578 address 0x07C
586 * SCB Host Address
589 address 0x07C
600 address 0x084
610 address 0x084
617 * Data FIFO Threshold
620 address 0x088
648 * ROM Address
651 address 0x08A
660 address 0x08D
669 * ROM Data
672 address 0x08E
677 * Data Channel Receive Message 0
680 address 0x090
691 address 0x090
702 address 0x090
713 address 0x090
725 * Data Channel Receive Message 1
728 address 0x091
738 address 0x091
748 address 0x091
758 address 0x091
770 * Data Channel Receive Message 2
773 address 0x092
783 address 0x092
793 address 0x092
803 address 0x092
809 * Data Channel Receive Message 3
812 address 0x093
822 address 0x093
832 address 0x093
839 * PCI-X Control
842 address 0x093
860 address 0x094
869 address 0x094
875 * Data Channel Sequencer Byte Count
878 address 0x094
885 * Data Channel Split Status 0
888 address 0x096
907 address 0x096
924 address 0x096
938 * Data Channel Split Status 1
941 address 0x097
953 address 0x097
963 address 0x097
973 address 0x098
984 address 0x099
994 address 0x09A
1004 address 0x09B
1011 * Slave Split Out Address 0
1014 address 0x098
1021 * Slave Split Out Address 1
1024 address 0x099
1032 * Slave Split Out Address 2
1035 address 0x09A
1042 * Slave Split Out Address 3
1045 address 0x09B
1056 address 0x09C
1065 address 0x09C
1075 address 0x09D
1086 address 0x09E
1096 address 0x09E
1115 address 0x09F
1127 address 0x09f
1136 * Data FIFO 0 PCI Status
1139 address 0x0A0
1155 * Data FIFO 1 PCI Status
1158 address 0x0A1
1175 address 0x0A2
1191 address 0x0A3
1208 address 0x0A4
1224 address 0x0A6
1239 address 0x0A7
1255 address 0x020
1268 address 0x020
1278 address 0x021
1288 address 0x022
1296 * Data Length Pointer
1297 * SCB offset for the 4 byte data length field in target mode.
1300 address 0x023
1310 address 0x024
1320 address 0x025
1333 address 0x026
1346 address 0x027
1358 address 0x028
1370 address 0x029
1383 address 0x02A
1394 address 0x02B
1406 address 0x02C
1417 address 0x02D
1426 address 0x02E
1435 address 0x02F
1445 address 0x030
1460 address 0x031
1473 address 0x032
1485 address 0x033
1497 address 0x034
1502 address 0x035
1507 address 0x036
1518 address 0x037
1527 address 0x038
1540 address 0x038
1554 address 0x039
1573 address 0x039
1588 address 0x03A
1602 address 0x03A
1614 address 0x03B
1630 address 0x03C
1644 address 0x03D
1661 address 0x03E
1674 address 0x03C
1681 * Data Length Counters
1685 address 0x03C
1692 * Data FIFO Status
1695 address 0x03F
1723 address 0x03E
1733 address 0x040
1764 address 0x041
1795 address 0x040
1807 address 0x042
1821 * SCSI Data 0 Image
1824 address 0x043
1830 * SCSI Latched Data
1833 address 0x044
1841 * SCSI Data Bus
1844 address 0x046
1854 address 0x048
1869 address 0x049
1882 address 0x04A
1897 address 0x04A
1915 address 0x04B
1933 address 0x04B
1952 address 0x04B
1969 address 0x04C
1987 address 0x04C
2004 address 0x04d
2024 address 0x04D
2038 address 0x04D
2050 address 0x04E
2068 address 0x04E
2079 address 0x04F
2089 address 0x04F
2100 address 0x050
2116 address 0x050
2133 address 0x050
2150 address 0x051
2168 address 0x051
2187 address 0x051
2206 address 0x052
2223 address 0x053
2235 address 0x053
2248 address 0x053
2261 address 0x054
2276 address 0x054
2292 address 0x054
2308 address 0x055
2322 address 0x055
2338 address 0x055
2354 address 0x056
2367 address 0x056
2380 address 0x057
2397 address 0x058
2405 * Data FIFO SCSI Transfer Control
2408 address 0x05A
2421 address 0x05A
2433 address 0x05A
2449 address 0x05B
2465 address 0x05B
2482 address 0x05C
2498 address 0x05C
2506 * Data FIFO Status
2509 address 0x05D
2516 field DLZERO 0x04 /* FIFO data ends on packet boundary. */
2525 address 0x05d
2535 address 0x05E
2543 * Data FIFO Queue Tag
2546 address 0x05E
2556 address 0x05E
2564 * SCSI I/O Cell Power-down Control
2567 address 0x05F
2576 * Shadow Host Address.
2579 address 0x060
2587 * Data Group CRC Interval.
2590 address 0x060
2597 * Data Transfer Negotiation Address
2600 address 0x060
2607 * Data Transfer Negotiation Data - Period Byte
2610 address 0x061
2621 address 0x062
2628 * Data Transfer Negotiation Data - Offset Byte
2631 address 0x062
2639 * Data Transfer Negotiation Data - PPR Options
2642 address 0x063
2654 * Data Transfer Negotiation Data - Connection Options
2657 address 0x064
2674 address 0x065
2686 address 0x066
2725 * Negotiation Table Annex Data Port.
2728 address 0x066
2740 address 0x067
2747 * 960MHz Phase-Locked Loop Control 0
2750 address 0x068
2766 address 0x069
2774 * 960MHz Phase-Locked Loop Control 1
2777 address 0x069
2789 address 0x06A
2798 address 0x068
2809 address 0x06B
2815 * 960-MHz Phase-Locked Loop Test Count
2818 address 0x06A
2825 * 400-MHz Phase-Locked Loop Control 0
2828 address 0x06C
2844 address 0x06C
2851 * 400-MHz Phase-Locked Loop Control 1
2854 address 0x06D
2866 address 0x06E
2873 * 400-MHz Phase-Locked Loop Test Count
2876 address 0x06E
2886 address 0x0A8
2899 address 0x0AB
2906 * SCB-Next Address Snooping logic. When an SCB is transferred to
2907 * the card, the next SCB address to be used by the CMC array can
2911 address 0x0AB
2922 * CMC SG Ram Address Pointer
2925 address 0x0AC
2932 * CMC SCB RAM Address Pointer
2935 address 0x0AC
2942 * CMC SCB Ram Back-up Address Pointer
2947 address 0x0AC
2956 address 0x0AD
2971 address 0x0AD
2986 address 0x0AD
2998 * CMC SG RAM Data Port
3001 address 0x0B0
3008 * CMC SCB RAM Data Port
3011 address 0x0B0
3018 * Flex DMA Address.
3021 address 0x0B0
3031 address 0x0B3
3041 address 0x0B5
3049 * Flex DMA Data Port
3052 address 0x0B6
3058 * Board Data
3061 address 0x0B8
3072 address 0x0B9
3086 * Serial EEPROM Address
3089 address 0x0BA
3097 * Serial EEPROM Data
3100 address 0x0BC
3112 address 0x0BE
3129 address 0x0BE
3160 address 0x0BF
3167 * Data FIFO Write Address
3168 * Pointer to the next QWD location to be written to the data FIFO.
3171 address 0x0C0
3182 address 0x0C0
3191 * DSP Data Channel Control
3194 address 0x0C1
3206 * Data FIFO Read Address
3207 * Pointer to the next QWD location to be read from the data FIFO.
3210 address 0x0C2
3220 address 0x0C2
3231 address 0x0C3
3239 * Data FIFO Data
3240 * Read/Write byte port into the data FIFO. The read and write
3245 address 0x0C4
3255 address 0x0C4
3270 address 0x0C5
3288 address 0x0C6
3299 address 0x0C7
3305 * Data FIFO Pointers
3310 address 0x0C8
3319 address 0x0C8
3325 * Data FIFO Backup Read Pointer
3326 * Contains the data FIFO address to be restored if the last
3327 * data accessed from the data FIFO was not transferred successfully.
3330 address 0x0C9
3340 address 0x0C9
3346 * Data FIFO Debug Control
3349 address 0x0CB
3361 * Data FIFO Space Count
3365 address 0x0CC
3372 * Data FIFO Byte Count
3376 address 0x0CE
3383 * Sequencer Program Overlay Address.
3384 * Low address must be written prior to high address.
3387 address 0x0D4
3399 address 0x0D6
3417 address 0x0D7
3430 address 0x0D8
3442 address 0x0D9
3454 * Sequencer RAM Data Port
3456 * at the address specified by OVLYADDR. To write a full instruction word,
3461 address 0x0DA
3472 address 0x0DE
3483 address 0x0E0
3499 address 0x0E2
3511 address 0x0E4
3518 * Break Address
3519 * Sequencer instruction breakpoint address address.
3522 address 0x0E6
3527 address 0x0E6
3537 address 0x0E8
3548 address 0x0EA
3559 address 0x0EA
3571 address 0x0EC
3582 address 0x0ED
3590 * (0-7 only) to the top nibble and retrieve the bit indexed by that value
3597 address 0x0F0
3607 address 0x0F2
3613 * Interrupt Vector 1 Address
3614 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
3617 address 0x0F4
3626 * Current Address
3627 * Address of the SEQRAM instruction currently executing instruction.
3630 address 0x0F4
3639 * Interrupt Vector 2 Address
3640 * Interrupt branch address for HST_SEQ_INT2 interrupts.
3643 address 0x0F6
3652 * Last Address
3653 * Address of the SEQRAM instruction executed prior to the current instruction.
3656 address 0x0F6
3663 address 0x100
3669 /* ---------------------- Scratch RAM Offsets ------------------------- */
3672 address 0x0A0
3694 * the current data phase is odd.
3703 address 0x0F8
3718 address 0x100
3722 * Per "other-id" execution queues. We use an array of
3723 * tail pointers into lists of SCBs sorted by "other-id".
3792 * Counting semaphore to prevent new select-outs
3827 field DIRECTION 0x04 /* Set indicates PCI->SCSI */
3902 * Base address of our shared data with the kernel driver in host
4014 * Number of commands "in-flight".
4038 * Target-mode CDB type to CDB length table used
4039 * in non-packetized operation.
4070 address 0x180
4141 * Overloaded field for non-packetized
4162 * The last byte is really the high address bits for
4163 * the data address.