Lines Matching refs:ISL12022_ALARM

46 #define ISL12022_ALARM		ISL12022_REG_SCA0  macro
249 ret = regmap_bulk_read(regmap, ISL12022_ALARM, buf, sizeof(buf)); in isl12022_rtc_read_alarm()
267 tm->tm_sec = bcd2bin(buf[ISL12022_REG_SCA0 - ISL12022_ALARM] & 0x7F); in isl12022_rtc_read_alarm()
268 tm->tm_min = bcd2bin(buf[ISL12022_REG_MNA0 - ISL12022_ALARM] & 0x7F); in isl12022_rtc_read_alarm()
269 tm->tm_hour = bcd2bin(buf[ISL12022_REG_HRA0 - ISL12022_ALARM] & 0x3F); in isl12022_rtc_read_alarm()
270 tm->tm_mday = bcd2bin(buf[ISL12022_REG_DTA0 - ISL12022_ALARM] & 0x3F); in isl12022_rtc_read_alarm()
271 tm->tm_mon = bcd2bin(buf[ISL12022_REG_MOA0 - ISL12022_ALARM] & 0x1F) - 1; in isl12022_rtc_read_alarm()
272 tm->tm_wday = buf[ISL12022_REG_DWA0 - ISL12022_ALARM] & 0x07; in isl12022_rtc_read_alarm()
325 regs[ISL12022_REG_SCA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_sec) | enable; in isl12022_rtc_set_alarm()
326 regs[ISL12022_REG_MNA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_min) | enable; in isl12022_rtc_set_alarm()
327 regs[ISL12022_REG_HRA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_hour) | enable; in isl12022_rtc_set_alarm()
328 regs[ISL12022_REG_DTA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_mday) | enable; in isl12022_rtc_set_alarm()
329 regs[ISL12022_REG_MOA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_mon + 1) | enable; in isl12022_rtc_set_alarm()
330 regs[ISL12022_REG_DWA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_wday & 7) | enable; in isl12022_rtc_set_alarm()
333 ret = regmap_bulk_write(regmap, ISL12022_ALARM, &regs, sizeof(regs)); in isl12022_rtc_set_alarm()
401 ret = regmap_bulk_write(regmap, ISL12022_ALARM, buf, sizeof(buf)); in isl12022_setup_irq()