14  * Note that reading the DSR (DryIce Status Register) automatically clears
55 #define DSR       0x14           /* Status Reg */  macro
103  * @dsr: copy of the DSR register
114 	u32 dsr;  member
184 static void di_report_tamper_info(struct imxdi_dev *imxdi,  u32 dsr)  in di_report_tamper_info()  argument
192 	if (dsr & DSR_VTD)  in di_report_tamper_info()
196 	if (dsr & DSR_CTD)  in di_report_tamper_info()
200 	if (dsr & DSR_TTD)  in di_report_tamper_info()
204 	if (dsr & DSR_SAD)  in di_report_tamper_info()
209 	if (dsr & DSR_EBD)  in di_report_tamper_info()
213 	if (dsr & DSR_ETAD)  in di_report_tamper_info()
217 	if (dsr & DSR_ETBD)  in di_report_tamper_info()
221 	if (dsr & DSR_WTD)  in di_report_tamper_info()
225 	if (dsr & DSR_MCO)  in di_report_tamper_info()
230 	if (dsr & DSR_TCO)  in di_report_tamper_info()
242 static int di_handle_failure_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_failure_state()  argument
246 	dev_dbg(&imxdi->pdev->dev, "DSR register reports: %08X\n", dsr);  in di_handle_failure_state()
249 	di_report_tamper_info(imxdi, dsr);  in di_handle_failure_state()
267 static int di_handle_valid_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_valid_state()  argument
274 	if (dsr & DSR_CAF)  in di_handle_valid_state()
275 		di_write_busy_wait(imxdi, DSR_CAF, DSR);  in di_handle_valid_state()
280 static int di_handle_invalid_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_invalid_state()  argument
315 	 *   - its overflow flag is set (TCO in DSR)  in di_handle_invalid_state()
317 	 *   - NVF is set in DSR  in di_handle_invalid_state()
325 	di_write_busy_wait(imxdi, DSR_NVF, DSR);  in di_handle_invalid_state()
327 	di_write_busy_wait(imxdi, DSR_TCO, DSR);  in di_handle_invalid_state()
334 	return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR));  in di_handle_invalid_state()
337 static int di_handle_invalid_and_failure_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_invalid_and_failure_state()  argument
346 	if (dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD |  in di_handle_invalid_and_failure_state()
375 	di_write_busy_wait(imxdi, dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD |  in di_handle_invalid_and_failure_state()
377 			DSR_MCO | DSR_TCO), DSR);  in di_handle_invalid_and_failure_state()
379 	dsr = readl(imxdi->ioaddr + DSR);  in di_handle_invalid_and_failure_state()
380 	if ((dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |  in di_handle_invalid_and_failure_state()
383 			 "There are still some sources of pain in DSR: %08x!\n",  in di_handle_invalid_and_failure_state()
384 			 dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |  in di_handle_invalid_and_failure_state()
391 	di_write_busy_wait(imxdi, DSR_SVF, DSR);  in di_handle_invalid_and_failure_state()
394 	dsr = readl(imxdi->ioaddr + DSR);  in di_handle_invalid_and_failure_state()
395 	if (dsr & DSR_SVF) {  in di_handle_invalid_and_failure_state()
407 	return di_handle_invalid_state(imxdi, dsr);  in di_handle_invalid_and_failure_state()
413 	u32 dsr;  in di_handle_state()  local
415 	dsr = readl(imxdi->ioaddr + DSR);  in di_handle_state()
417 	switch (dsr & (DSR_NVF | DSR_SVF)) {  in di_handle_state()
420 		rc = di_handle_invalid_state(imxdi, dsr);  in di_handle_state()
424 		rc = di_handle_failure_state(imxdi, dsr);  in di_handle_state()
429 		rc = di_handle_invalid_and_failure_state(imxdi, dsr);  in di_handle_state()
433 		rc = di_handle_valid_state(imxdi, dsr);  in di_handle_state()
479 	writel(DSR_WEF, imxdi->ioaddr + DSR);  in clear_write_error()
483 		if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)  in clear_write_error()
508 	imxdi->dsr = 0;  in di_write_wait()
515 			imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));  in di_write_wait()
526 	if (imxdi->dsr & DSR_WEF) {  in di_write_wait()
558 	u32 dcr, dsr;  in dryice_rtc_set_time()  local
562 	dsr = readl(imxdi->ioaddr + DSR);  in dryice_rtc_set_time()
564 	if (!(dcr & DCR_TCE) || (dsr & DSR_SVF)) {  in dryice_rtc_set_time()
570 		if ((dcr & DCR_TCSL) || (dsr & DSR_SVF)) {  in dryice_rtc_set_time()
617 	/* don't allow the DSR read to mess up DSR_WCF */  in dryice_rtc_read_alarm()
621 	alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;  in dryice_rtc_read_alarm()
663 	u32 dsr, dier;  in dryice_irq()  local
667 	dsr = readl(imxdi->ioaddr + DSR);  in dryice_irq()
671 		if (dsr & DSR_SVF) {  in dryice_irq()
682 			di_report_tamper_info(imxdi, dsr);  in dryice_irq()
695 		/* DSR_WCF clears itself on DSR read */  in dryice_irq()
696 		if (dsr & (DSR_WCF | DSR_WEF)) {  in dryice_irq()
700 			/* save the dsr value for the wait queue */  in dryice_irq()
701 			imxdi->dsr |= dsr;  in dryice_irq()
710 		/* DSR_WCF clears itself on DSR read */  in dryice_irq()
711 		if (dsr & DSR_CAF) {  in dryice_irq()
733 	di_write_wait(imxdi, DSR_CAF, DSR);  in dryice_work()