Lines Matching +full:1 +full:x64 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
4 * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
10 * up to 255 * 0.25 = 63.75 µs. For RST_TYPE_FLUSH, the reset bit is
16 * unambiguously signal whether hardware reset removal or clock-stop period
21 …* https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87…
30 #include <linux/reset-controller.h>
33 #include <dt-bindings/reset/canaan,k230-rst.h>
36 * enum k230_rst_type - K230 reset types
38 * Automatically clears, has write enable and done bit, active high
40 * Manually clears, has write enable and done bit, active high
42 * Automatically clears, has write enable, no done bit, active high
44 * Automatically clears, no write enable, has done bit, active high
46 * Manually clears, no write enable and done bit,
67 /* protect register read-modify-write */
72 [RST_CPU0] = { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) },
73 [RST_CPU1] = { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) },
74 [RST_CPU0_FLUSH] = { 0x4, RST_TYPE_FLUSH, 0, BIT(4) },
75 [RST_CPU1_FLUSH] = { 0xc, RST_TYPE_FLUSH, 0, BIT(4) },
76 [RST_AI] = { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
77 [RST_VPU] = { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
78 [RST_HISYS] = { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) },
79 [RST_HISYS_AHB] = { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) },
80 [RST_SDIO0] = { 0x34, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
81 [RST_SDIO1] = { 0x34, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
82 [RST_SDIO_AXI] = { 0x34, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
83 [RST_USB0] = { 0x3c, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
84 [RST_USB1] = { 0x3c, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
85 [RST_USB0_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(30), BIT(0) },
86 [RST_USB1_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(31), BIT(1) },
87 [RST_SPI0] = { 0x44, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
88 [RST_SPI1] = { 0x44, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
89 [RST_SPI2] = { 0x44, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
90 [RST_SEC] = { 0x4c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
91 [RST_PDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
92 [RST_SDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
93 [RST_DECOMPRESS] = { 0x5c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
94 [RST_SRAM] = { 0x64, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
95 [RST_SHRM_AXIM] = { 0x64, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
96 [RST_SHRM_AXIS] = { 0x64, RST_TYPE_HW_DONE, BIT(31), BIT(3) },
97 [RST_NONAI2D] = { 0x6c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
98 [RST_MCTL] = { 0x74, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
99 [RST_ISP] = { 0x80, RST_TYPE_HW_DONE, BIT(29), BIT(6) },
100 [RST_ISP_DW] = { 0x80, RST_TYPE_HW_DONE, BIT(28), BIT(5) },
101 [RST_DPU] = { 0x88, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
102 [RST_DISP] = { 0x90, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
103 [RST_GPU] = { 0x98, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
104 [RST_AUDIO] = { 0xa4, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
105 [RST_TIMER0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(0) },
106 [RST_TIMER1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(1) },
107 [RST_TIMER2] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(2) },
108 [RST_TIMER3] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(3) },
109 [RST_TIMER4] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(4) },
110 [RST_TIMER5] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(5) },
111 [RST_TIMER_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(6) },
112 [RST_HDI] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(7) },
113 [RST_WDT0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(12) },
114 [RST_WDT1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(13) },
115 [RST_WDT0_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(14) },
116 [RST_WDT1_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(15) },
117 [RST_TS_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(16) },
118 [RST_MAILBOX] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(17) },
119 [RST_STC] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(18) },
120 [RST_PMU] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(19) },
121 [RST_LOSYS_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(0) },
122 [RST_UART0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(1) },
123 [RST_UART1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(2) },
124 [RST_UART2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(3) },
125 [RST_UART3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(4) },
126 [RST_UART4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(5) },
127 [RST_I2C0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(6) },
128 [RST_I2C1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(7) },
129 [RST_I2C2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(8) },
130 [RST_I2C3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(9) },
131 [RST_I2C4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(10) },
132 [RST_JAMLINK0_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(11) },
133 [RST_JAMLINK1_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(12) },
134 [RST_JAMLINK2_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(13) },
135 [RST_JAMLINK3_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(14) },
136 [RST_CODEC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(17) },
137 [RST_GPIO_DB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(18) },
138 [RST_GPIO_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(19) },
139 [RST_ADC] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(20) },
140 [RST_ADC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(21) },
141 [RST_PWM_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(22) },
142 [RST_SHRM_APB] = { 0x64, RST_TYPE_SW_DONE, 0, BIT(1) },
143 [RST_CSI0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(0) },
144 [RST_CSI1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(1) },
145 [RST_CSI2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(2) },
146 [RST_CSI_DPHY] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(3) },
147 [RST_ISP_AHB] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(4) },
148 [RST_M0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(7) },
149 [RST_M1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(8) },
150 [RST_M2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(9) },
151 [RST_SPI2AXI] = { 0xa8, RST_TYPE_SW_DONE, 0, BIT(0) }
165 guard(spinlock_irqsave)(&rstc->lock); in k230_rst_clear_done()
167 reg = readl(rstc->base + rmap->offset); in k230_rst_clear_done()
168 reg |= rmap->done; /* write 1 to clear */ in k230_rst_clear_done()
170 reg |= rmap->done << 16; in k230_rst_clear_done()
171 writel(reg, rstc->base + rmap->offset); in k230_rst_clear_done()
181 ret = readl_poll_timeout(rstc->base + rmap->offset, reg, in k230_rst_wait_and_clear_done()
182 reg & rmap->done, 10, 1000); in k230_rst_wait_and_clear_done()
184 dev_err(rstc->rcdev.dev, "Wait for reset done timeout\n"); in k230_rst_wait_and_clear_done()
199 guard(spinlock_irqsave)(&rstc->lock); in k230_rst_update()
201 reg = readl(rstc->base + rmap->offset); in k230_rst_update()
203 reg |= rmap->reset; in k230_rst_update()
205 reg &= ~rmap->reset; in k230_rst_update()
207 reg |= rmap->reset << 16; in k230_rst_update()
208 writel(reg, rstc->base + rmap->offset); in k230_rst_update()
226 return -EOPNOTSUPP; in k230_rst_assert()
257 return -EOPNOTSUPP; in k230_rst_deassert()
277 switch (rmap->type) { in k230_rst_reset()
294 /* Wait flush request bit auto cleared by hardware */ in k230_rst_reset()
295 ret = readl_poll_timeout(rstc->base + rmap->offset, reg, in k230_rst_reset()
296 !(reg & rmap->reset), 10, 1000); in k230_rst_reset()
298 dev_err(rcdev->dev, "Wait for flush done timeout\n"); in k230_rst_reset()
332 struct device *dev = &pdev->dev; in k230_rst_probe()
337 return -ENOMEM; in k230_rst_probe()
339 rstc->base = devm_platform_ioremap_resource(pdev, 0); in k230_rst_probe()
340 if (IS_ERR(rstc->base)) in k230_rst_probe()
341 return PTR_ERR(rstc->base); in k230_rst_probe()
343 spin_lock_init(&rstc->lock); in k230_rst_probe()
345 rstc->rcdev.dev = dev; in k230_rst_probe()
346 rstc->rcdev.owner = THIS_MODULE; in k230_rst_probe()
347 rstc->rcdev.ops = &k230_rst_ops; in k230_rst_probe()
348 rstc->rcdev.nr_resets = ARRAY_SIZE(k230_resets); in k230_rst_probe()
349 rstc->rcdev.of_node = dev->of_node; in k230_rst_probe()
351 return devm_reset_controller_register(dev, &rstc->rcdev); in k230_rst_probe()
355 { .compatible = "canaan,k230-rst", },
363 .name = "k230-rst",