Lines Matching +full:0 +full:x24
72 [RST_CPU0] = { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) },
73 [RST_CPU1] = { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) },
74 [RST_CPU0_FLUSH] = { 0x4, RST_TYPE_FLUSH, 0, BIT(4) },
75 [RST_CPU1_FLUSH] = { 0xc, RST_TYPE_FLUSH, 0, BIT(4) },
76 [RST_AI] = { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
77 [RST_VPU] = { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
78 [RST_HISYS] = { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) },
79 [RST_HISYS_AHB] = { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) },
80 [RST_SDIO0] = { 0x34, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
81 [RST_SDIO1] = { 0x34, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
82 [RST_SDIO_AXI] = { 0x34, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
83 [RST_USB0] = { 0x3c, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
84 [RST_USB1] = { 0x3c, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
85 [RST_USB0_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(30), BIT(0) },
86 [RST_USB1_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(31), BIT(1) },
87 [RST_SPI0] = { 0x44, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
88 [RST_SPI1] = { 0x44, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
89 [RST_SPI2] = { 0x44, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
90 [RST_SEC] = { 0x4c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
91 [RST_PDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
92 [RST_SDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
93 [RST_DECOMPRESS] = { 0x5c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
94 [RST_SRAM] = { 0x64, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
95 [RST_SHRM_AXIM] = { 0x64, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
96 [RST_SHRM_AXIS] = { 0x64, RST_TYPE_HW_DONE, BIT(31), BIT(3) },
97 [RST_NONAI2D] = { 0x6c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
98 [RST_MCTL] = { 0x74, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
99 [RST_ISP] = { 0x80, RST_TYPE_HW_DONE, BIT(29), BIT(6) },
100 [RST_ISP_DW] = { 0x80, RST_TYPE_HW_DONE, BIT(28), BIT(5) },
101 [RST_DPU] = { 0x88, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
102 [RST_DISP] = { 0x90, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
103 [RST_GPU] = { 0x98, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
104 [RST_AUDIO] = { 0xa4, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
105 [RST_TIMER0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(0) },
106 [RST_TIMER1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(1) },
107 [RST_TIMER2] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(2) },
108 [RST_TIMER3] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(3) },
109 [RST_TIMER4] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(4) },
110 [RST_TIMER5] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(5) },
111 [RST_TIMER_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(6) },
112 [RST_HDI] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(7) },
113 [RST_WDT0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(12) },
114 [RST_WDT1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(13) },
115 [RST_WDT0_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(14) },
116 [RST_WDT1_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(15) },
117 [RST_TS_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(16) },
118 [RST_MAILBOX] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(17) },
119 [RST_STC] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(18) },
120 [RST_PMU] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(19) },
121 [RST_LOSYS_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(0) },
122 [RST_UART0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(1) },
123 [RST_UART1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(2) },
124 [RST_UART2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(3) },
125 [RST_UART3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(4) },
126 [RST_UART4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(5) },
127 [RST_I2C0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(6) },
128 [RST_I2C1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(7) },
129 [RST_I2C2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(8) },
130 [RST_I2C3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(9) },
131 [RST_I2C4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(10) },
132 [RST_JAMLINK0_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(11) },
133 [RST_JAMLINK1_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(12) },
134 [RST_JAMLINK2_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(13) },
135 [RST_JAMLINK3_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(14) },
136 [RST_CODEC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(17) },
137 [RST_GPIO_DB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(18) },
138 [RST_GPIO_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(19) },
139 [RST_ADC] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(20) },
140 [RST_ADC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(21) },
141 [RST_PWM_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(22) },
142 [RST_SHRM_APB] = { 0x64, RST_TYPE_SW_DONE, 0, BIT(1) },
143 [RST_CSI0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(0) },
144 [RST_CSI1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(1) },
145 [RST_CSI2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(2) },
146 [RST_CSI_DPHY] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(3) },
147 [RST_ISP_AHB] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(4) },
148 [RST_M0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(7) },
149 [RST_M1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(8) },
150 [RST_M2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(9) },
151 [RST_SPI2AXI] = { 0xa8, RST_TYPE_SW_DONE, 0, BIT(0) }
190 return 0; in k230_rst_wait_and_clear_done()
236 return 0; in k230_rst_assert()
243 int ret = 0; in k230_rst_deassert()
275 int ret = 0; in k230_rst_reset()
339 rstc->base = devm_platform_ioremap_resource(pdev, 0); in k230_rst_probe()