Lines Matching full:true
40 [SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) },
41 [SCU0_RESET_DDRPHY] = { true, SCU0_RESET_CTRL1, BIT(1) },
42 [SCU0_RESET_RSA] = { true, SCU0_RESET_CTRL1, BIT(2) },
43 [SCU0_RESET_SHA3] = { true, SCU0_RESET_CTRL1, BIT(3) },
44 [SCU0_RESET_HACE] = { true, SCU0_RESET_CTRL1, BIT(4) },
45 [SCU0_RESET_SOC] = { true, SCU0_RESET_CTRL1, BIT(5) },
46 [SCU0_RESET_VIDEO] = { true, SCU0_RESET_CTRL1, BIT(6) },
47 [SCU0_RESET_2D] = { true, SCU0_RESET_CTRL1, BIT(7) },
48 [SCU0_RESET_PCIS] = { true, SCU0_RESET_CTRL1, BIT(8) },
49 [SCU0_RESET_RVAS0] = { true, SCU0_RESET_CTRL1, BIT(9) },
50 [SCU0_RESET_RVAS1] = { true, SCU0_RESET_CTRL1, BIT(10) },
51 [SCU0_RESET_SM3] = { true, SCU0_RESET_CTRL1, BIT(11) },
52 [SCU0_RESET_SM4] = { true, SCU0_RESET_CTRL1, BIT(12) },
53 [SCU0_RESET_CRT0] = { true, SCU0_RESET_CTRL1, BIT(13) },
54 [SCU0_RESET_ECC] = { true, SCU0_RESET_CTRL1, BIT(14) },
55 [SCU0_RESET_DP_PCI] = { true, SCU0_RESET_CTRL1, BIT(15) },
56 [SCU0_RESET_UFS] = { true, SCU0_RESET_CTRL1, BIT(16) },
57 [SCU0_RESET_EMMC] = { true, SCU0_RESET_CTRL1, BIT(17) },
58 [SCU0_RESET_PCIE1RST] = { true, SCU0_RESET_CTRL1, BIT(18) },
59 [SCU0_RESET_PCIE1RSTOE] = { true, SCU0_RESET_CTRL1, BIT(19) },
60 [SCU0_RESET_PCIE0RST] = { true, SCU0_RESET_CTRL1, BIT(20) },
61 [SCU0_RESET_PCIE0RSTOE] = { true, SCU0_RESET_CTRL1, BIT(21) },
62 [SCU0_RESET_JTAG] = { true, SCU0_RESET_CTRL1, BIT(22) },
63 [SCU0_RESET_MCTP0] = { true, SCU0_RESET_CTRL1, BIT(23) },
64 [SCU0_RESET_MCTP1] = { true, SCU0_RESET_CTRL1, BIT(24) },
65 [SCU0_RESET_XDMA0] = { true, SCU0_RESET_CTRL1, BIT(25) },
66 [SCU0_RESET_XDMA1] = { true, SCU0_RESET_CTRL1, BIT(26) },
67 [SCU0_RESET_H2X1] = { true, SCU0_RESET_CTRL1, BIT(27) },
68 [SCU0_RESET_DP] = { true, SCU0_RESET_CTRL1, BIT(28) },
69 [SCU0_RESET_DP_MCU] = { true, SCU0_RESET_CTRL1, BIT(29) },
70 [SCU0_RESET_SSP] = { true, SCU0_RESET_CTRL1, BIT(30) },
71 [SCU0_RESET_H2X0] = { true, SCU0_RESET_CTRL1, BIT(31) },
72 [SCU0_RESET_PORTA_VHUB] = { true, SCU0_RESET_CTRL2, BIT(0) },
73 [SCU0_RESET_PORTA_PHY3] = { true, SCU0_RESET_CTRL2, BIT(1) },
74 [SCU0_RESET_PORTA_XHCI] = { true, SCU0_RESET_CTRL2, BIT(2) },
75 [SCU0_RESET_PORTB_VHUB] = { true, SCU0_RESET_CTRL2, BIT(3) },
76 [SCU0_RESET_PORTB_PHY3] = { true, SCU0_RESET_CTRL2, BIT(4) },
77 [SCU0_RESET_PORTB_XHCI] = { true, SCU0_RESET_CTRL2, BIT(5) },
78 [SCU0_RESET_PORTA_VHUB_EHCI] = { true, SCU0_RESET_CTRL2, BIT(6) },
79 [SCU0_RESET_PORTB_VHUB_EHCI] = { true, SCU0_RESET_CTRL2, BIT(7) },
80 [SCU0_RESET_UHCI] = { true, SCU0_RESET_CTRL2, BIT(8) },
81 [SCU0_RESET_TSP] = { true, SCU0_RESET_CTRL2, BIT(9) },
82 [SCU0_RESET_E2M0] = { true, SCU0_RESET_CTRL2, BIT(10) },
83 [SCU0_RESET_E2M1] = { true, SCU0_RESET_CTRL2, BIT(11) },
84 [SCU0_RESET_VLINK] = { true, SCU0_RESET_CTRL2, BIT(12) },
88 [SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) },
89 [SCU1_RESET_LPC1] = { true, SCU1_RESET_CTRL1, BIT(1) },
90 [SCU1_RESET_MII] = { true, SCU1_RESET_CTRL1, BIT(2) },
91 [SCU1_RESET_PECI] = { true, SCU1_RESET_CTRL1, BIT(3) },
92 [SCU1_RESET_PWM] = { true, SCU1_RESET_CTRL1, BIT(4) },
93 [SCU1_RESET_MAC0] = { true, SCU1_RESET_CTRL1, BIT(5) },
94 [SCU1_RESET_MAC1] = { true, SCU1_RESET_CTRL1, BIT(6) },
95 [SCU1_RESET_MAC2] = { true, SCU1_RESET_CTRL1, BIT(7) },
96 [SCU1_RESET_ADC] = { true, SCU1_RESET_CTRL1, BIT(8) },
97 [SCU1_RESET_SD] = { true, SCU1_RESET_CTRL1, BIT(9) },
98 [SCU1_RESET_ESPI0] = { true, SCU1_RESET_CTRL1, BIT(10) },
99 [SCU1_RESET_ESPI1] = { true, SCU1_RESET_CTRL1, BIT(11) },
100 [SCU1_RESET_JTAG1] = { true, SCU1_RESET_CTRL1, BIT(12) },
101 [SCU1_RESET_SPI0] = { true, SCU1_RESET_CTRL1, BIT(13) },
102 [SCU1_RESET_SPI1] = { true, SCU1_RESET_CTRL1, BIT(14) },
103 [SCU1_RESET_SPI2] = { true, SCU1_RESET_CTRL1, BIT(15) },
104 [SCU1_RESET_I3C0] = { true, SCU1_RESET_CTRL1, BIT(16) },
105 [SCU1_RESET_I3C1] = { true, SCU1_RESET_CTRL1, BIT(17) },
106 [SCU1_RESET_I3C2] = { true, SCU1_RESET_CTRL1, BIT(18) },
107 [SCU1_RESET_I3C3] = { true, SCU1_RESET_CTRL1, BIT(19) },
108 [SCU1_RESET_I3C4] = { true, SCU1_RESET_CTRL1, BIT(20) },
109 [SCU1_RESET_I3C5] = { true, SCU1_RESET_CTRL1, BIT(21) },
110 [SCU1_RESET_I3C6] = { true, SCU1_RESET_CTRL1, BIT(22) },
111 [SCU1_RESET_I3C7] = { true, SCU1_RESET_CTRL1, BIT(23) },
112 [SCU1_RESET_I3C8] = { true, SCU1_RESET_CTRL1, BIT(24) },
113 [SCU1_RESET_I3C9] = { true, SCU1_RESET_CTRL1, BIT(25) },
114 [SCU1_RESET_I3C10] = { true, SCU1_RESET_CTRL1, BIT(26) },
115 [SCU1_RESET_I3C11] = { true, SCU1_RESET_CTRL1, BIT(27) },
116 [SCU1_RESET_I3C12] = { true, SCU1_RESET_CTRL1, BIT(28) },
117 [SCU1_RESET_I3C13] = { true, SCU1_RESET_CTRL1, BIT(29) },
118 [SCU1_RESET_I3C14] = { true, SCU1_RESET_CTRL1, BIT(30) },
119 [SCU1_RESET_I3C15] = { true, SCU1_RESET_CTRL1, BIT(31) },
120 [SCU1_RESET_MCU0] = { true, SCU1_RESET_CTRL2, BIT(0) },
121 [SCU1_RESET_MCU1] = { true, SCU1_RESET_CTRL2, BIT(1) },
122 [SCU1_RESET_H2A_SPI1] = { true, SCU1_RESET_CTRL2, BIT(2) },
123 [SCU1_RESET_H2A_SPI2] = { true, SCU1_RESET_CTRL2, BIT(3) },
124 [SCU1_RESET_UART0] = { true, SCU1_RESET_CTRL2, BIT(4) },
125 [SCU1_RESET_UART1] = { true, SCU1_RESET_CTRL2, BIT(5) },
126 [SCU1_RESET_UART2] = { true, SCU1_RESET_CTRL2, BIT(6) },
127 [SCU1_RESET_UART3] = { true, SCU1_RESET_CTRL2, BIT(7) },
128 [SCU1_RESET_I2C_FILTER] = { true, SCU1_RESET_CTRL2, BIT(8) },
129 [SCU1_RESET_CALIPTRA] = { true, SCU1_RESET_CTRL2, BIT(9) },
130 [SCU1_RESET_XDMA] = { true, SCU1_RESET_CTRL2, BIT(10) },
131 [SCU1_RESET_FSI] = { true, SCU1_RESET_CTRL2, BIT(12) },
132 [SCU1_RESET_CAN] = { true, SCU1_RESET_CTRL2, BIT(13) },
133 [SCU1_RESET_MCTP] = { true, SCU1_RESET_CTRL2, BIT(14) },
134 [SCU1_RESET_I2C] = { true, SCU1_RESET_CTRL2, BIT(15) },
135 [SCU1_RESET_UART6] = { true, SCU1_RESET_CTRL2, BIT(16) },
136 [SCU1_RESET_UART7] = { true, SCU1_RESET_CTRL2, BIT(17) },
137 [SCU1_RESET_UART8] = { true, SCU1_RESET_CTRL2, BIT(18) },
138 [SCU1_RESET_UART9] = { true, SCU1_RESET_CTRL2, BIT(19) },
139 [SCU1_RESET_LTPI0] = { true, SCU1_RESET_CTRL2, BIT(20) },
140 [SCU1_RESET_VGAL] = { true, SCU1_RESET_CTRL2, BIT(21) },
141 [SCU1_RESET_LTPI1] = { true, SCU1_RESET_CTRL2, BIT(22) },
142 [SCU1_RESET_ACE] = { true, SCU1_RESET_CTRL2, BIT(23) },
143 [SCU1_RESET_E2M] = { true, SCU1_RESET_CTRL2, BIT(24) },
144 [SCU1_RESET_UHCI] = { true, SCU1_RESET_CTRL2, BIT(25) },
145 [SCU1_RESET_PORTC_USB2UART] = { true, SCU1_RESET_CTRL2, BIT(26) },
146 [SCU1_RESET_PORTC_VHUB_EHCI] = { true, SCU1_RESET_CTRL2, BIT(27) },
147 [SCU1_RESET_PORTD_USB2UART] = { true, SCU1_RESET_CTRL2, BIT(28) },
148 [SCU1_RESET_PORTD_VHUB_EHCI] = { true, SCU1_RESET_CTRL2, BIT(29) },
149 [SCU1_RESET_H2X] = { true, SCU1_RESET_CTRL2, BIT(30) },
150 [SCU1_RESET_I3CDMA] = { true, SCU1_RESET_CTRL2, BIT(31) },