28 #define Q6SS_RESET_REG		0x014
29 #define Q6SS_GFMUX_CTL_REG		0x020
30 #define Q6SS_PWR_CTL_REG		0x030
31 #define Q6SS_MEM_PWR_CTL		0x0B0
32 #define Q6SS_STRAP_ACC			0x110
33 #define Q6SS_CGC_OVERRIDE		0x034
34 #define Q6SS_BCR_REG			0x6000
37 #define AXI_HALTREQ_REG			0x0
38 #define AXI_HALTACK_REG			0x4
39 #define AXI_IDLE_REG			0x8
44 #define Q6SS_STOP_CORE			BIT(0)
49 #define Q6SS_BRC_BLK_ARES		BIT(0)
60 #define QDSS_Q6_MEMORIES		GENMASK(15, 0)
72 #define TCSR_GLOBAL_CFG0	0x0
73 #define TCSR_GLOBAL_CFG1	0x4
74 #define SSCAON_CONFIG		0x8
75 #define SSCAON_STATUS		0xc
76 #define Q6SS_BHS_STATUS		0x78
77 #define Q6SS_RST_EVB		0x10
79 #define BHS_EN_REST_ACK		BIT(0)
85 #define TCSR_WCSS_CLK_MASK	0x1F
86 #define TCSR_WCSS_CLK_ENABLE	0x14
168 	val |= 0x1;  in q6v5_wcss_reset()
201 	for (i = MEM_BANKS; i >= 0; i--) {  in q6v5_wcss_reset()
236 	return 0;  in q6v5_wcss_reset()
269 				 1, 0);  in q6v5_wcss_start()
346 	val |= BIT(0);  in q6v5_wcss_qcs404_power_on()
358 	writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE);  in q6v5_wcss_qcs404_power_on()
362 	val |= BIT(0);  in q6v5_wcss_qcs404_power_on()
376 	writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_qcs404_power_on()
378 	writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_qcs404_power_on()
380 	writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_qcs404_power_on()
382 	writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_qcs404_power_on()
388 	for (idx = 28; idx >= 0; idx--) {  in q6v5_wcss_qcs404_power_on()
393 	writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_qcs404_power_on()
394 	writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_qcs404_power_on()
410 	return 0;  in q6v5_wcss_qcs404_power_on()
446 	writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC);  in q6v5_wcss_qcs404_reset()
453 	return 0;  in q6v5_wcss_qcs404_reset()
487 	return 0;  in q6v5_qcs404_wcss_start()
528 	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);  in q6v5_wcss_halt_axi_port()
560 	val &= ~BIT(0);  in q6v5_qcs404_wcss_shutdown()
564 	val &= ~BIT(0);  in q6v5_qcs404_wcss_shutdown()
592 	return 0;  in q6v5_qcs404_wcss_shutdown()
619 				 val, (val & 0xffff) == 0x400, 1000,  in q6v5_wcss_powerdown()
638 	return 0;  in q6v5_wcss_powerdown()
673 	for (i = 0; i < 20; i++) {  in q6v5_q6_powerdown()
705 	return 0;  in q6v5_q6_powerdown()
739 	return 0;  in q6v5_wcss_stop()
748 	if (offset < 0 || offset + len > wcss->mem_size)  in q6v5_wcss_da_to_va()
760 				    0, wcss->mem_region, wcss->mem_phys,  in q6v5_wcss_load()
820 	return 0;  in q6v5_wcss_init_reset()
826 	unsigned int halt_reg[MAX_HALT_REG] = {0};  in q6v5_wcss_init_mmio()
847 				  "qcom,halt-regs", 0);  in q6v5_wcss_init_mmio()
860 						  halt_reg, 0,  in q6v5_wcss_init_mmio()
862 	if (ret < 0) {  in q6v5_wcss_init_mmio()
867 	wcss->halt_q6 = halt_reg[0];  in q6v5_wcss_init_mmio()
871 	return 0;  in q6v5_wcss_init_mmio()
880 	node = of_parse_phandle(dev->of_node, "memory-region", 0);  in q6v5_alloc_memory_region()
900 	return 0;  in q6v5_alloc_memory_region()
990 	return 0;  in q6v5_wcss_init_clock()
1001 	return 0;  in q6v5_wcss_init_regulator()
1070 	return 0;  in q6v5_wcss_probe()
1100 	.ssctl_id = 0x12,