30 #define IMX7D_SRC_SCR			0x0C
34 #define IMX7D_SW_M4C_NON_SCLR_RST	BIT(0)
48 #define IMX8M_GPR22			0x58
49 #define IMX8M_GPR22_CM7_CPUWAIT		BIT(0)
51 /* Address: 0x020D8000 */
52 #define IMX6SX_SRC_SCR			0x00
68 #define IMX_SIP_RPROC			0xC2000005
69 #define IMX_SIP_RPROC_START		0x00
70 #define IMX_SIP_RPROC_STARTED		0x01
71 #define IMX_SIP_RPROC_STOP		0x02
92 #define ATT_CORE_MASK   0xffff
124 	{ 0x0FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM },
127 	{ 0x1FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM },
130 	{ 0x20000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM },
133 	{ 0x30000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM },
136 	{ 0x80000000, 0x80000000, 0x10000000, 0 },
137 	{ 0x90000000, 0x80000000, 0x10000000, 0 },
139 	{ 0xC0000000, 0xC0000000, 0x10000000, 0 },
140 	{ 0xD0000000, 0xC0000000, 0x10000000, 0 },
145 	{ 0x08000000, 0x08000000, 0x10000000, 0},
147 	{ 0x1FFE0000, 0x34FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
148 	{ 0x1FFE0000, 0x38FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
150 	{ 0x20000000, 0x35000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
151 	{ 0x20000000, 0x39000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
153 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
157 	{ 0x08000000, 0x08000000, 0x10000000, 0 },
159 	{ 0x1FFE0000, 0x34FE0000, 0x00040000, ATT_OWN | ATT_IOMEM },
161 	{ 0x21000000, 0x00100000, 0x00018000, 0 },
163 	{ 0x21100000, 0x00100000, 0x00040000, 0 },
165 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
171 	{ 0x00000000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM },
173 	{ 0x00180000, 0x00180000, 0x00009000, 0 },
175 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
177 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
179 	{ 0x00940000, 0x00940000, 0x00050000, 0 },
181 	{ 0x08000000, 0x08000000, 0x08000000, 0 },
183 	{ 0x10000000, 0x40000000, 0x0FFE0000, 0 },
185 	{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM },
187 	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
189 	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
191 	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
193 	{ 0x20240000, 0x00940000, 0x00040000, ATT_OWN },
195 	{ 0x40000000, 0x40000000, 0x80000000, 0 },
201 	{ 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM},
203 	{ 0x00180000, 0x00180000, 0x00008000, 0 },
205 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
207 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
209 	{ 0x08000000, 0x08000000, 0x08000000, 0 },
211 	{ 0x10000000, 0x40000000, 0x0FFE0000, 0 },
213 	{ 0x1FFE0000, 0x007E0000, 0x00040000, ATT_OWN  | ATT_IOMEM},
215 	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
217 	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
219 	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
221 	{ 0x40000000, 0x40000000, 0x80000000, 0 },
225 	{0x1FFC0000, 0x1FFC0000, 0xC0000, ATT_OWN},
226 	{0x21000000, 0x21000000, 0x10000, ATT_OWN},
227 	{0x80000000, 0x80000000, 0x60000000, 0}
231 	{0x1FFD0000, 0x1FFD0000, 0x30000, ATT_OWN},
232 	{0x20000000, 0x20000000, 0x10000, ATT_OWN},
233 	{0x2F000000, 0x2F000000, 0x20000, ATT_OWN},
234 	{0x2F020000, 0x2F020000, 0x20000, ATT_OWN},
235 	{0x60000000, 0x60000000, 0x40000000, 0}
241 	{ 0x00000000, 0x00180000, 0x00008000, 0 },
243 	{ 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
245 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
247 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
249 	{ 0x00940000, 0x00940000, 0x00008000, 0 },
251 	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
253 	{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
256 	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
258 	{ 0x20200000, 0x00900000, 0x00020000, 0 },
260 	{ 0x20220000, 0x00920000, 0x00020000, 0 },
262 	{ 0x20240000, 0x00940000, 0x00008000, 0 },
264 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
270 	{ 0x00000000, 0x007F8000, 0x00008000, ATT_IOMEM },
272 	{ 0x00180000, 0x008F8000, 0x00004000, 0 },
274 	{ 0x00180000, 0x008FC000, 0x00004000, 0 },
276 	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
278 	{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },
281 	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
283 	{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
285 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
391 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_START, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_start()
431 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STOP, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_stop()
458 	for (i = 0; i < dcfg->att_size; i++) {  in imx_rproc_da_to_sys()
463 		 * i.MX8QM has dual general M4_[0,1] cores, M4_0's own entries  in imx_rproc_da_to_sys()
464 		 * has "ATT_CORE(0) & BIT(0)" true, M4_1's own entries has  in imx_rproc_da_to_sys()
478 			return 0;  in imx_rproc_da_to_sys()
482 	dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",  in imx_rproc_da_to_sys()
494 	if (len == 0)  in imx_rproc_da_to_va()
504 	for (i = 0; i < IMX_RPROC_MEM_MAX; i++) {  in imx_rproc_da_to_va()
514 	dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",  in imx_rproc_da_to_va()
537 	return 0;  in imx_rproc_mem_alloc()
546 	return 0;  in imx_rproc_mem_release()
559 	of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);  in imx_rproc_prepare()
560 	while (of_phandle_iterator_next(&it) == 0) {  in imx_rproc_prepare()
596 	return  0;  in imx_rproc_prepare()
607 	return 0;  in imx_rproc_parse_fw()
628 	if (err < 0)  in imx_rproc_kick()
651 	return 0;  in imx_rproc_detach()
699 	int a, b = 0, err, nph;  in imx_rproc_addr_init()
702 	for (a = 0; a < dcfg->att_size; a++) {  in imx_rproc_addr_init()
728 	if (nph <= 0)  in imx_rproc_addr_init()
729 		return 0;  in imx_rproc_addr_init()
732 	for (a = 0; a < nph; a++) {  in imx_rproc_addr_init()
744 		err = of_address_to_resource(node, 0, &res);  in imx_rproc_addr_init()
771 	return 0;  in imx_rproc_addr_init()
780 	return 0;  in imx_rproc_notified_idr_cb()
816 		return 0;  in imx_rproc_xtr_mbox_init()
819 		return 0;  in imx_rproc_xtr_mbox_init()
840 	return 0;  in imx_rproc_xtr_mbox_init()
882 		return 0;  in imx_rproc_partition_notify()
888 	return 0;  in imx_rproc_partition_notify()
902 		return 0;  in imx_rproc_attach_pd()
905 	if (ret < 0)  in imx_rproc_attach_pd()
912 	for (i = 0; i < ret; i++) {  in imx_rproc_attach_pd()
922 	return 0;  in imx_rproc_attach_pd()
939 		return 0;  in imx_rproc_detect_mode()
941 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STARTED, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_detect_mode()
944 		return 0;  in imx_rproc_detect_mode()
958 			priv->core_index = 0;  in imx_rproc_detect_mode()
999 		return 0;  in imx_rproc_detect_mode()
1026 			return 0;  in imx_rproc_detect_mode()
1039 	return 0;  in imx_rproc_detect_mode()
1050 		return 0;  in imx_rproc_clk_enable()
1068 	return 0;  in imx_rproc_clk_enable()
1180 	return 0;  in imx_rproc_probe()