Lines Matching +full:strobe +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0+
75 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
80 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
81 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
82 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
99 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
100 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
102 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
110 int sel; in rtmv20_lsw_set_current_limit() local
113 return -EINVAL; in rtmv20_lsw_set_current_limit()
118 sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA; in rtmv20_lsw_set_current_limit()
121 if ((sel * RTMV20_LSW_STEPUA + RTMV20_LSW_MINUA) < min_uA) in rtmv20_lsw_set_current_limit()
122 return -EINVAL; in rtmv20_lsw_set_current_limit()
124 sel <<= ffs(rdev->desc->csel_mask) - 1; in rtmv20_lsw_set_current_limit()
126 return regmap_update_bits(rdev->regmap, rdev->desc->csel_reg, in rtmv20_lsw_set_current_limit()
127 rdev->desc->csel_mask, sel); in rtmv20_lsw_set_current_limit()
135 ret = regmap_read(rdev->regmap, rdev->desc->csel_reg, &val); in rtmv20_lsw_get_current_limit()
139 val &= rdev->desc->csel_mask; in rtmv20_lsw_get_current_limit()
140 val >>= ffs(rdev->desc->csel_mask) - 1; in rtmv20_lsw_get_current_limit()
172 ret = regmap_read(priv->regmap, RTMV20_REG_LDIRQ, &val); in rtmv20_irq_handler()
174 dev_err(priv->dev, "Failed to get irq flags\n"); in rtmv20_irq_handler()
179 regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_TEMP, NULL); in rtmv20_irq_handler()
182 regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_CURRENT, NULL); in rtmv20_irq_handler()
185 regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_FAIL, NULL); in rtmv20_irq_handler()
194 return (retval - min) / step; in clamp_to_selector()
208 { "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY, in rtmv20_properties_init()
210 { "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH, in rtmv20_properties_init()
212 { "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1, in rtmv20_properties_init()
214 { "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3, in rtmv20_properties_init()
216 { "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1, in rtmv20_properties_init()
218 { "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3, in rtmv20_properties_init()
220 { "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH, in rtmv20_properties_init()
222 { "richtek,es-ld-current-microamp", 3000000, 0, 6000000, 30000, in rtmv20_properties_init()
224 { "richtek,lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP, in rtmv20_properties_init()
226 { "richtek,lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK }, in rtmv20_properties_init()
227 { "richtek,strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, in rtmv20_properties_init()
229 { "richtek,vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, in rtmv20_properties_init()
231 { "richtek,fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK }, in rtmv20_properties_init()
232 { "richtek,fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK }, in rtmv20_properties_init()
233 { "richtek,es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK }, in rtmv20_properties_init()
242 int shift = ffs(props[i].mask) - 1; in rtmv20_properties_init()
245 ret = device_property_read_u32(priv->dev, props[i].name, &temp); in rtmv20_properties_init()
249 temp = device_property_read_bool(priv->dev, props[i].name); in rtmv20_properties_init()
255 ret = regmap_raw_read(priv->regmap, props[i].addr, &bval16, sizeof(bval16)); in rtmv20_properties_init()
264 ret = regmap_raw_write(priv->regmap, props[i].addr, &bval16, in rtmv20_properties_init()
267 ret = regmap_update_bits(priv->regmap, props[i].addr, props[i].mask, in rtmv20_properties_init()
283 ret = regmap_read(priv->regmap, RTMV20_REG_DEVINFO, &val); in rtmv20_check_chip_exist()
288 return -ENODEV; in rtmv20_check_chip_exist()
330 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL); in rtmv20_probe()
332 return -ENOMEM; in rtmv20_probe()
334 priv->dev = &i2c->dev; in rtmv20_probe()
337 priv->enable_gpio = devm_gpiod_get(&i2c->dev, "enable", GPIOD_OUT_HIGH); in rtmv20_probe()
338 if (IS_ERR(priv->enable_gpio)) { in rtmv20_probe()
339 dev_err(&i2c->dev, "Failed to get enable gpio\n"); in rtmv20_probe()
340 return PTR_ERR(priv->enable_gpio); in rtmv20_probe()
346 priv->regmap = devm_regmap_init_i2c(i2c, &rtmv20_regmap_config); in rtmv20_probe()
347 if (IS_ERR(priv->regmap)) { in rtmv20_probe()
348 dev_err(&i2c->dev, "Failed to allocate register map\n"); in rtmv20_probe()
349 return PTR_ERR(priv->regmap); in rtmv20_probe()
354 dev_err(&i2c->dev, "Chip vendor info is not matched\n"); in rtmv20_probe()
360 dev_err(&i2c->dev, "Failed to init properties\n"); in rtmv20_probe()
368 regcache_cache_only(priv->regmap, true); in rtmv20_probe()
369 regcache_mark_dirty(priv->regmap); in rtmv20_probe()
370 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_probe()
372 config.dev = &i2c->dev; in rtmv20_probe()
373 config.regmap = priv->regmap; in rtmv20_probe()
375 priv->rdev = devm_regulator_register(&i2c->dev, &rtmv20_lsw_desc, &config); in rtmv20_probe()
376 if (IS_ERR(priv->rdev)) { in rtmv20_probe()
377 dev_err(&i2c->dev, "Failed to register regulator\n"); in rtmv20_probe()
378 return PTR_ERR(priv->rdev); in rtmv20_probe()
382 ret = regmap_write(priv->regmap, RTMV20_REG_LDMASK, 0); in rtmv20_probe()
386 return devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rtmv20_irq_handler, in rtmv20_probe()
387 IRQF_ONESHOT, dev_name(&i2c->dev), priv); in rtmv20_probe()
398 disable_irq(i2c->irq); in rtmv20_suspend()
400 enable_irq_wake(i2c->irq); in rtmv20_suspend()
410 enable_irq(i2c->irq); in rtmv20_resume()
412 disable_irq_wake(i2c->irq); in rtmv20_resume()