Lines Matching +full:0 +full:x1400
25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
37 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08
38 #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
39 #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
49 SPMI_VS_SOFT_START_STR_0P05_UA = 0,
108 SPMI_REGULATOR_TYPE_BUCK = 0x03,
109 SPMI_REGULATOR_TYPE_LDO = 0x04,
110 SPMI_REGULATOR_TYPE_VS = 0x05,
111 SPMI_REGULATOR_TYPE_BOOST = 0x1b,
112 SPMI_REGULATOR_TYPE_FTS = 0x1c,
113 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f,
114 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21,
115 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22,
119 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08,
120 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09,
121 SPMI_REGULATOR_SUBTYPE_N50 = 0x01,
122 SPMI_REGULATOR_SUBTYPE_N150 = 0x02,
123 SPMI_REGULATOR_SUBTYPE_N300 = 0x03,
124 SPMI_REGULATOR_SUBTYPE_N600 = 0x04,
125 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05,
126 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06,
127 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07,
128 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14,
129 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15,
130 SPMI_REGULATOR_SUBTYPE_P50 = 0x08,
131 SPMI_REGULATOR_SUBTYPE_P150 = 0x09,
132 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a,
133 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b,
134 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c,
135 SPMI_REGULATOR_SUBTYPE_LN = 0x10,
136 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28,
137 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29,
138 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a,
139 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b,
140 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c,
141 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d,
142 SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30,
143 SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31,
144 SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32,
145 SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b,
146 SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c,
147 SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42,
148 SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43,
149 SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46,
150 SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47,
151 SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49,
152 SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d,
153 SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f,
154 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01,
155 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02,
156 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08,
157 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09,
158 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10,
159 SPMI_REGULATOR_SUBTYPE_OTG = 0x11,
160 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01,
161 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08,
162 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09,
163 SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a,
164 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01,
165 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d,
166 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e,
167 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
168 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
169 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
170 SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
171 SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d,
172 SPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0a,
173 SPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 0x0b,
174 SPMI_REGULATOR_SUBTYPE_LV_P150_510 = 0x71,
175 SPMI_REGULATOR_SUBTYPE_LV_P300_510 = 0x72,
176 SPMI_REGULATOR_SUBTYPE_LV_P600_510 = 0x73,
177 SPMI_REGULATOR_SUBTYPE_N300_510 = 0x6a,
178 SPMI_REGULATOR_SUBTYPE_N600_510 = 0x6b,
179 SPMI_REGULATOR_SUBTYPE_N1200_510 = 0x6c,
180 SPMI_REGULATOR_SUBTYPE_MV_P50_510 = 0x7a,
181 SPMI_REGULATOR_SUBTYPE_MV_P150_510 = 0x7b,
182 SPMI_REGULATOR_SUBTYPE_MV_P600_510 = 0x7d,
186 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01,
187 SPMI_COMMON_REG_TYPE = 0x04,
188 SPMI_COMMON_REG_SUBTYPE = 0x05,
189 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40,
190 SPMI_COMMON_REG_VOLTAGE_SET = 0x41,
191 SPMI_COMMON_REG_MODE = 0x45,
192 SPMI_COMMON_REG_ENABLE = 0x46,
193 SPMI_COMMON_REG_PULL_DOWN = 0x48,
194 SPMI_COMMON_REG_SOFT_START = 0x4c,
195 SPMI_COMMON_REG_STEP_CTRL = 0x61,
204 SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40,
205 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41,
206 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68,
207 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69,
214 SPMI_HFSMPS_REG_STEP_CTRL = 0x3c,
215 SPMI_HFSMPS_REG_PULL_DOWN = 0xa0,
219 SPMI_VS_REG_OCP = 0x4a,
220 SPMI_VS_REG_SOFT_START = 0x4c,
224 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a,
228 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b,
232 SAW3_SECURE = 0x00,
233 SAW3_ID = 0x04,
234 SAW3_SPM_STS = 0x0C,
235 SAW3_AVS_STS = 0x10,
236 SAW3_PMIC_STS = 0x14,
237 SAW3_RST = 0x18,
238 SAW3_VCTL = 0x1C,
239 SAW3_AVS_CTL = 0x20,
240 SAW3_AVS_LIMIT = 0x24,
241 SAW3_AVS_DLY = 0x28,
242 SAW3_AVS_HYSTERESIS = 0x2C,
243 SAW3_SPM_STS2 = 0x38,
244 SAW3_SPM_PMIC_DATA_3 = 0x4C,
245 SAW3_VERSION = 0xFD0,
248 /* Used for indexing into ctrl_reg. These are offsets from 0x40 */
250 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0,
257 #define SPMI_COMMON_ENABLE_MASK 0x80
258 #define SPMI_COMMON_ENABLE 0x80
259 #define SPMI_COMMON_DISABLE 0x00
260 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08
261 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04
262 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02
263 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01
264 #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f
267 #define SPMI_COMMON_MODE_HPM_MASK 0x80
268 #define SPMI_COMMON_MODE_AUTO_MASK 0x40
269 #define SPMI_COMMON_MODE_BYPASS_MASK 0x20
270 #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10
271 #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08
272 #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04
273 #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02
274 #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01
275 #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f
283 #define SPMI_FTSMPS426_MODE_MASK 0x07
292 #define SPMI_HFSMPS_MODE_MASK 0x07
295 #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80
298 #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80
301 #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80
304 #define SPMI_VS_OCP_OVERRIDE 0x01
305 #define SPMI_VS_OCP_NO_OVERRIDE 0x00
308 #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80
309 #define SPMI_VS_SOFT_START_SEL_MASK 0x03
312 #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80
313 #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07
320 #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18
322 #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07
323 #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0
342 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03
343 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0
362 #define ULT_SMPS_RANGE_SPLIT 0x60
367 * set point register value 0x00
380 * (max_uV - min_uV) % step_uV == 0
381 * (set_point_min_uV - min_uV) % step_uV == 0*
382 * (set_point_max_uV - min_uV) % step_uV == 0*
385 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to
503 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500),
509 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
510 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500),
511 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500),
516 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000),
520 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
525 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000),
526 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000),
530 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000),
535 SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000),
539 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000),
543 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000),
547 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
548 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000),
552 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000),
556 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
560 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500),
564 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000),
568 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
572 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000),
576 SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000),
580 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
584 SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
588 SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000),
592 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
596 SPMI_VOLTAGE_RANGE(0, 300000, 300000, 1372000, 1372000, 4000),
647 vreg->ocp_count = 0; in spmi_regulator_vs_enable()
675 lim_min_uV = vreg->set_points->range[0].set_point_min_uV; in spmi_regulator_select_voltage()
690 for (i = vreg->set_points->count - 1; i > 0; i--) { in spmi_regulator_select_voltage()
692 if (uV > range_max_uV && range_max_uV > 0) in spmi_regulator_select_voltage()
714 selector = 0; in spmi_regulator_select_voltage()
715 for (i = 0; i < range_id; i++) in spmi_regulator_select_voltage()
742 return 0; in spmi_sw_selector_to_hw()
754 unsigned sw_sel = 0; in spmi_hw_selector_to_sw()
837 selector = 0; in spmi_regulator_select_voltage_same_range()
838 for (i = 0; i < vreg->set_points->count; i++) { in spmi_regulator_select_voltage_same_range()
883 buf[0] = range_sel; in spmi_regulator_common_set_voltage()
900 buf[0] = mV & 0xff; in spmi_regulator_ftsmps426_set_voltage()
941 uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000; in spmi_regulator_ftsmps426_get_voltage()
994 * In case of range 0: voltage_sel is a 7 bit value, can be written in spmi_regulator_ult_lo_smps_set_voltage()
1003 voltage_sel, 0xff); in spmi_regulator_ult_lo_smps_set_voltage()
1028 int uV = 0; in spmi_regulator_common_list_voltage()
1032 return 0; in spmi_regulator_common_list_voltage()
1034 for (i = 0; i < vreg->set_points->count; i++) { in spmi_regulator_common_list_voltage()
1052 u8 val = 0; in spmi_regulator_common_set_bypass()
1141 val = 0; in spmi_regulator_common_set_mode()
1255 if (ilim_uA > max || ilim_uA <= 0) in spmi_regulator_set_ilim()
1304 vreg->ocp_count = 0; in spmi_regulator_vs_ocp_isr()
1306 /* Wait for switch output to settle back to 0 V after OCP triggered. */ in spmi_regulator_vs_ocp_isr()
1327 #define SAW3_VCTL_DATA_MASK 0xFF
1328 #define SAW3_VCTL_CLEAR_MASK 0x700FF
1329 #define SAW3_AVS_CTL_EN_MASK 0x1
1330 #define SAW3_AVS_CTL_TGGL_MASK 0x8000000
1331 #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00
1377 pmic_sts &= 0x3f; in spmi_saw_set_vdd()
1397 if (0 != range_sel) { in spmi_regulator_saw_set_voltage()
1404 return smp_call_function_single(0, spmi_saw_set_vdd, \ in spmi_regulator_saw_set_voltage()
1581 #define INF 0xFF
1585 SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000),
1586 SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
1587 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
1588 SPMI_VREG(BUCK, HFS430, 0, 3, HFS430, hfs430, hfs430, 10000),
1590 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
1591 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000),
1592 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000),
1595 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000),
1596 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000),
1599 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000),
1600 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000),
1601 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000),
1602 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000),
1603 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000),
1604 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0),
1605 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000),
1606 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000),
1607 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000),
1608 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000),
1609 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000),
1610 SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1612 SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1614 SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426,
1616 SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426,
1618 SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426,
1620 SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1622 SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1624 SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426,
1626 SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426,
1628 SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426,
1630 SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426,
1632 SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426,
1634 SPMI_VREG_VS(LV100, 0, INF),
1635 SPMI_VREG_VS(LV300, 0, INF),
1636 SPMI_VREG_VS(MV300, 0, INF),
1637 SPMI_VREG_VS(MV500, 0, INF),
1638 SPMI_VREG_VS(HDMI, 0, INF),
1639 SPMI_VREG_VS(OTG, 0, INF),
1640 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
1641 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000),
1642 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000),
1643 SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000),
1644 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0),
1645 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1647 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1649 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1651 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps,
1653 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1654 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1655 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1656 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1657 SPMI_VREG(ULT_LDO, LV_P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1658 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1659 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1660 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1661 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1662 SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1663 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1664 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000),
1665 SPMI_VREG(LDO, LV_P150_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000),
1666 SPMI_VREG(LDO, LV_P300_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000),
1667 SPMI_VREG(LDO, LV_P600_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000),
1668 SPMI_VREG(LDO, MV_P50_510, 0, INF, LDO_510, hfsmps, pldo660, 10000),
1669 SPMI_VREG(LDO, MV_P150_510, 0, INF, LDO_510, hfsmps, pldo660, 10000),
1670 SPMI_VREG(LDO, MV_P600_510, 0, INF, LDO_510, hfsmps, pldo660, 10000),
1671 SPMI_VREG(LDO, N300_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000),
1672 SPMI_VREG(LDO, N600_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000),
1673 SPMI_VREG(LDO, N1200_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000),
1674 SPMI_VREG(FTS, FTSMPS_510, 0, INF, FTSMPS3, hfsmps, ftsmps510, 100000),
1683 n = 0; in spmi_calculate_num_voltages()
1720 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { in spmi_regulator_match()
1729 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", in spmi_regulator_match()
1746 return 0; in spmi_regulator_match()
1752 u8 reg = 0; in spmi_regulator_init_slew_rate()
1787 /* Ensure that the slew rate is greater than 0 */ in spmi_regulator_init_slew_rate()
1797 u8 reg = 0; in spmi_regulator_init_slew_rate_ftsmps426()
1799 const struct spmi_voltage_range *range = &vreg->set_points->range[0]; in spmi_regulator_init_slew_rate_ftsmps426()
1816 /* Ensure that the slew rate is greater than 0 */ in spmi_regulator_init_slew_rate_ftsmps426()
1825 u8 reg = 0; in spmi_regulator_init_slew_rate_hfsmps()
1913 return 0; in spmi_regulator_init_registers()
2003 vreg->ocp_irq = 0; in spmi_regulator_of_parse()
2009 if (ret < 0) { in spmi_regulator_of_parse()
2021 return 0; in spmi_regulator_of_parse()
2025 { "s1", 0x1400, "vdd_s1" },
2026 { "s2", 0x1700, "vdd_s2" },
2027 { "s3", 0x1a00, "vdd_s3" },
2028 { "s4", 0x1d00, "vdd_s4" },
2029 { "s5", 0x2000, "vdd_s5" },
2030 { "s6", 0x2300, "vdd_s6" },
2031 { "s7", 0x2600, "vdd_s7" },
2032 { "s8", 0x2900, "vdd_s8" },
2033 { "l1", 0x4000, "vdd_l1_l7_l17_l18" },
2034 { "l2", 0x4100, "vdd_l2_l3_l4" },
2035 { "l3", 0x4200, "vdd_l2_l3_l4" },
2036 { "l4", 0x4300, "vdd_l2_l3_l4" },
2037 { "l5", 0x4400, "vdd_l5_l15_l19_l20_l21_l22" },
2038 { "l6", 0x4500, "vdd_l6_l8" },
2039 { "l7", 0x4600, "vdd_l1_l7_l17_l18" },
2040 { "l8", 0x4700, "vdd_l6_l8" },
2041 { "l9", 0x4800, "vdd_l9_l11" },
2042 { "l10", 0x4900, "vdd_l10_l13_l14" },
2043 { "l11", 0x4a00, "vdd_l9_l11" },
2044 { "l12", 0x4b00, "vdd_l12_l16" },
2045 { "l13", 0x4c00, "vdd_l10_l13_l14" },
2046 { "l14", 0x4d00, "vdd_l10_l13_l14" },
2047 { "l15", 0x4e00, "vdd_l5_l15_l19_l20_l21_l22" },
2048 { "l16", 0x4f00, "vdd_l12_l16" },
2049 { "l17", 0x5000, "vdd_l1_l7_l17_l18" },
2050 { "l18", 0x5100, "vdd_l1_l7_l17_l18" },
2051 { "l19", 0x5200, "vdd_l5_l15_l19_l20_l21_l22" },
2052 { "l20", 0x5300, "vdd_l5_l15_l19_l20_l21_l22" },
2053 { "l21", 0x5400, "vdd_l5_l15_l19_l20_l21_l22" },
2054 { "l22", 0x5500, "vdd_l5_l15_l19_l20_l21_l22" },
2055 { "l23", 0x5600, "vdd_l23_l24" },
2056 { "l24", 0x5700, "vdd_l23_l24" },
2060 { "s1", 0x1400, "vdd_s1", },
2061 { "s2", 0x1700, "vdd_s2", },
2062 { "s3", 0x1a00, "vdd_s3", },
2063 { "s4", 0x1d00, "vdd_s3", },
2064 { "s5", 0x2000, "vdd_s5", },
2065 { "s6", 0x2300, "vdd_s6", },
2066 { "l1", 0x4000, "vdd_l1_l6_l7", },
2067 { "l2", 0x4100, "vdd_l2_l3", },
2068 { "l3", 0x4200, "vdd_l2_l3", },
2070 { "l5", 0x4400, "vdd_l5", },
2071 { "l6", 0x4500, "vdd_l1_l6_l7", },
2072 { "l7", 0x4600, "vdd_l1_l6_l7", },
2073 { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2074 { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2075 { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2076 { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2077 { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2078 { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2079 { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2080 { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
2081 { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
2082 { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
2083 { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
2084 { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
2089 { "s1", 0x1400, "vdd_s1", },
2090 { "s2", 0x1700, "vdd_s2", },
2091 { "s3", 0x1a00, "vdd_s3", },
2092 { "s4", 0x1d00, "vdd_s4", },
2093 { "s5", 0x2000, "vdd_s5", },
2094 { "l1", 0x4000, "vdd_l1_l9_l10", },
2095 { "l2", 0x4100, "vdd_l2", },
2096 { "l3", 0x4200, "vdd_l3_l5_l7_l8", },
2097 { "l4", 0x4300, "vdd_l4_l6", },
2098 { "l5", 0x4400, "vdd_l3_l5_l7_l8", },
2099 { "l6", 0x4500, "vdd_l4_l6", },
2100 { "l7", 0x4600, "vdd_l3_l5_l7_l8", },
2101 { "l8", 0x4700, "vdd_l3_l5_l7_l8", },
2102 { "l9", 0x4800, "vdd_l1_l9_l10", },
2103 { "l10", 0x4900, "vdd_l1_l9_l10", },
2108 { "s2", 0x1700, "vdd_s2", },
2109 { "s5", 0x2000, "vdd_s5", },
2114 { "s1", 0x1400, "vdd_s1", },
2115 { "s2", 0x1700, "vdd_s2", },
2116 { "s3", 0x1a00, "vdd_s3", },
2117 { "s4", 0x1d00, "vdd_s4", },
2122 { "s1", 0x1400, "vdd_s1", },
2123 { "s2", 0x1700, "vdd_s2", },
2124 { "s3", 0x1a00, "vdd_s3", },
2125 { "s4", 0x1d00, "vdd_s4", },
2126 { "l1", 0x4000, "vdd_l1", },
2127 { "l2", 0x4100, "vdd_l2_l3", },
2128 { "l3", 0x4200, "vdd_l2_l3", },
2129 { "l4", 0x4300, "vdd_l4_l5_l6", },
2130 { "l5", 0x4400, "vdd_l4_l5_l6", },
2131 { "l6", 0x4500, "vdd_l4_l5_l6", },
2132 { "l7", 0x4600, "vdd_l7_l8_l11", },
2133 { "l8", 0x4700, "vdd_l7_l8_l11", },
2134 { "l9", 0x4800, "vdd_l9", },
2135 { "l10", 0x4900, "vdd_l10", },
2136 { "l11", 0x4a00, "vdd_l7_l8_l11", },
2137 { "l12", 0x4b00, "vdd_l12", },
2138 { "l13", 0x4c00, "vdd_l13_l14", },
2139 { "l14", 0x4d00, "vdd_l13_l14", },
2144 { "s1", 0x1400, "vdd_s1", },
2145 { "s2", 0x1700, "vdd_s2", },
2146 { "s3", 0x1a00, "vdd_s3", },
2147 { "s4", 0x1d00, "vdd_s4", },
2148 { "s5", 0x2000, "vdd_s5", },
2149 { "l1", 0x4000, "vdd_l1_l2_l4_l5", },
2150 { "l2", 0x4100, "vdd_l1_l2_l4_l5", },
2151 { "l3", 0x4200, "vdd_l3_l24_l26", },
2152 { "l4", 0x4300, "vdd_l1_l2_l4_l5", },
2153 { "l5", 0x4400, "vdd_l1_l2_l4_l5", },
2154 { "l6", 0x4500, "vdd_l6_l7_l8_l9_l27", },
2155 { "l7", 0x4600, "vdd_l6_l7_l8_l9_l27", },
2156 { "l8", 0x4700, "vdd_l6_l7_l8_l9_l27", },
2157 { "l9", 0x4800, "vdd_l6_l7_l8_l9_l27", },
2158 { "l10", 0x4900, "vdd_l10_l11_l13", },
2159 { "l11", 0x4a00, "vdd_l10_l11_l13", },
2160 { "l12", 0x4b00, "vdd_l12_l14", },
2161 { "l13", 0x4c00, "vdd_l10_l11_l13", },
2162 { "l14", 0x4d00, "vdd_l12_l14", },
2163 { "l15", 0x4e00, "vdd_l15_l16_l17_l18", },
2164 { "l16", 0x4f00, "vdd_l15_l16_l17_l18", },
2165 { "l17", 0x5000, "vdd_l15_l16_l17_l18", },
2166 { "l18", 0x5100, "vdd_l15_l16_l17_l18", },
2167 { "l19", 0x5200, "vdd_l19_l20_l21_l22_l23_l28", },
2168 { "l20", 0x5300, "vdd_l19_l20_l21_l22_l23_l28", },
2169 { "l21", 0x5400, "vdd_l19_l20_l21_l22_l23_l28", },
2170 { "l22", 0x5500, "vdd_l19_l20_l21_l22_l23_l28", },
2171 { "l23", 0x5600, "vdd_l19_l20_l21_l22_l23_l28", },
2172 { "l24", 0x5700, "vdd_l3_l24_l26", },
2173 { "l25", 0x5800, "vdd_l25", },
2174 { "l26", 0x5900, "vdd_l3_l24_l26", },
2175 { "l27", 0x5a00, "vdd_l6_l7_l8_l9_l27", },
2176 { "l28", 0x5b00, "vdd_l19_l20_l21_l22_l23_l28", },
2177 { "lvs1", 0x8000, "vdd_lvs1", },
2182 { "s1", 0x1400, "vdd_s1", },
2183 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 },
2184 { "s3", 0x1a00, "vdd_s3", },
2185 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 },
2186 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 },
2187 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 },
2188 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 },
2189 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 },
2194 { "s1", 0x1400, "vdd_s1", },
2195 { "s2", 0x1700, "vdd_s2", },
2196 { "l1", 0x4000, "vdd_l1", },
2197 { "l2", 0x4100, "vdd_l2_l5", },
2198 { "l3", 0x4200, "vdd_l3_l6_l10", },
2199 { "l4", 0x4300, "vdd_l4_l7", },
2200 { "l5", 0x4400, "vdd_l2_l5", },
2201 { "l6", 0x4500, "vdd_l3_l6_l10", },
2202 { "l7", 0x4600, "vdd_l4_l7", },
2203 { "l8", 0x4700, "vdd_l8_l11_l15_l18", },
2204 { "l9", 0x4800, "vdd_l9_l12_l14_l17", },
2205 { "l10", 0x4900, "vdd_l3_l6_l10", },
2206 { "l11", 0x4a00, "vdd_l8_l11_l15_l18", },
2207 { "l12", 0x4b00, "vdd_l9_l12_l14_l17", },
2208 { "l13", 0x4c00, "vdd_l13", },
2209 { "l14", 0x4d00, "vdd_l9_l12_l14_l17", },
2210 { "l15", 0x4e00, "vdd_l8_l11_l15_l18", },
2211 { "l17", 0x5000, "vdd_l9_l12_l14_l17", },
2212 { "l18", 0x5100, "vdd_l8_l11_l15_l18", },
2217 { "s1", 0x1400, "vdd_s1", },
2218 { "s2", 0x1700, "vdd_s2", },
2219 { "s3", 0x1a00, "vdd_s3", },
2220 { "s4", 0x1d00, "vdd_s4", },
2221 { "l1", 0x4000, "vdd_l1_l3", },
2222 { "l2", 0x4100, "vdd_l2", },
2223 { "l3", 0x4200, "vdd_l1_l3", },
2224 { "l4", 0x4300, "vdd_l4_l5_l6", },
2225 { "l5", 0x4400, "vdd_l4_l5_l6", },
2226 { "l6", 0x4500, "vdd_l4_l5_l6", },
2227 { "l7", 0x4600, "vdd_l7", },
2228 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", },
2229 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", },
2230 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", },
2231 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", },
2232 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", },
2233 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", },
2234 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", },
2235 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", },
2236 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", },
2237 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", },
2238 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", },
2243 { "s1", 0x1400, "vdd_s1", },
2244 { "s2", 0x1700, "vdd_s2", },
2245 { "s3", 0x1a00, "vdd_s3", },
2246 { "s4", 0x1d00, "vdd_s4", },
2247 { "s5", 0x2000, "vdd_s5", },
2248 { "s6", 0x2300, "vdd_s6", },
2249 { "l1", 0x4000, "vdd_l1_l19", },
2250 { "l2", 0x4100, "vdd_l2_l23", },
2251 { "l3", 0x4200, "vdd_l3", },
2252 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
2253 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
2254 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
2255 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
2256 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
2257 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
2258 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
2259 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
2260 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
2261 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
2262 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
2263 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
2264 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
2265 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
2266 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
2267 { "l19", 0x5200, "vdd_l1_l19", },
2268 { "l20", 0x5300, "vdd_l20_l21", },
2269 { "l21", 0x5400, "vdd_l21_l21", },
2270 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
2271 { "l23", 0x5600, "vdd_l2_l23", },
2276 { "s1", 0x1400, "vdd_s1", },
2277 { "s2", 0x1700, "vdd_s2", },
2278 { "s3", 0x1a00, "vdd_s3", },
2279 { "s4", 0xa000, },
2280 { "l1", 0x4000, "vdd_l1_l3", },
2281 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", },
2282 { "l3", 0x4200, "vdd_l1_l3", },
2283 { "l4", 0x4300, "vdd_l4_l11", },
2284 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 },
2285 { "l6", 0x4500, "vdd_l6_l12_l14_l15", },
2286 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 },
2287 { "l8", 0x4700, "vdd_l8_l16_l18_19", },
2288 { "l9", 0x4800, "vdd_l9_l10_l17_l22", },
2289 { "l10", 0x4900, "vdd_l9_l10_l17_l22", },
2290 { "l11", 0x4a00, "vdd_l4_l11", },
2291 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", },
2292 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", },
2293 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", },
2294 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", },
2295 { "l16", 0x4f00, "vdd_l8_l16_l18_19", },
2296 { "l17", 0x5000, "vdd_l9_l10_l17_l22", },
2297 { "l18", 0x5100, "vdd_l8_l16_l18_19", },
2298 { "l19", 0x5200, "vdd_l8_l16_l18_19", },
2299 { "l20", 0x5300, "vdd_l13_l20_l23_l24", },
2300 { "l21", 0x5400, "vdd_l21", },
2301 { "l22", 0x5500, "vdd_l9_l10_l17_l22", },
2302 { "l23", 0x5600, "vdd_l13_l20_l23_l24", },
2303 { "l24", 0x5700, "vdd_l13_l20_l23_l24", },
2304 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
2305 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
2306 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
2307 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
2308 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
2313 { "s1", 0x1400, "vdd_s1", },
2314 { "s2", 0x1700, "vdd_s2", },
2315 { "s3", 0x1a00, "vdd_s3", },
2316 { "s4", 0x1d00, "vdd_s4", },
2317 { "s5", 0x2000, "vdd_s5", },
2318 { "s6", 0x2300, "vdd_s6", },
2319 { "l1", 0x4000, "vdd_l1_l19", },
2320 { "l2", 0x4100, "vdd_l2_l23", },
2321 { "l3", 0x4200, "vdd_l3", },
2322 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
2323 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
2324 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
2325 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
2326 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
2327 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
2328 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
2329 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
2330 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
2331 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
2332 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
2333 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
2334 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
2335 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
2336 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
2337 { "l19", 0x5200, "vdd_l1_l19", },
2338 { "l20", 0x5300, "vdd_l20", },
2339 { "l21", 0x5400, "vdd_l21", },
2340 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
2341 { "l23", 0x5600, "vdd_l2_l23", },
2346 { "s1", 0x1400, "vdd_s1", },
2347 { "s2", 0x1700, "vdd_s2", },
2348 { "s3", 0x1a00, "vdd_s3", },
2349 { "s4", 0x1d00, "vdd_s4", },
2350 { "s5", 0x2000, "vdd_s5", },
2351 { "s6", 0x2300, "vdd_s6", },
2352 { "s7", 0x2600, "vdd_s7", },
2353 { "s8", 0x2900, "vdd_s8", },
2354 { "s9", 0x2c00, "vdd_s9", },
2355 { "s10", 0x2f00, "vdd_s10", },
2356 { "s11", 0x3200, "vdd_s11", },
2357 { "s12", 0x3500, "vdd_s12", },
2358 { "l1", 0x4000, "vdd_l1", },
2359 { "l2", 0x4100, "vdd_l2_l26_l28", },
2360 { "l3", 0x4200, "vdd_l3_l11", },
2361 { "l4", 0x4300, "vdd_l4_l27_l31", },
2362 { "l5", 0x4400, "vdd_l5_l7", },
2363 { "l6", 0x4500, "vdd_l6_l12_l32", },
2364 { "l7", 0x4600, "vdd_l5_l7", },
2365 { "l8", 0x4700, "vdd_l8_l16_l30", },
2366 { "l9", 0x4800, "vdd_l9_l10_l18_l22", },
2367 { "l10", 0x4900, "vdd_l9_l10_l18_l22", },
2368 { "l11", 0x4a00, "vdd_l3_l11", },
2369 { "l12", 0x4b00, "vdd_l6_l12_l32", },
2370 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", },
2371 { "l14", 0x4d00, "vdd_l14_l15", },
2372 { "l15", 0x4e00, "vdd_l14_l15", },
2373 { "l16", 0x4f00, "vdd_l8_l16_l30", },
2374 { "l17", 0x5000, "vdd_l17_l29", },
2375 { "l18", 0x5100, "vdd_l9_l10_l18_l22", },
2376 { "l19", 0x5200, "vdd_l13_l19_l23_l24", },
2377 { "l20", 0x5300, "vdd_l20_l21", },
2378 { "l21", 0x5400, "vdd_l20_l21", },
2379 { "l22", 0x5500, "vdd_l9_l10_l18_l22", },
2380 { "l23", 0x5600, "vdd_l13_l19_l23_l24", },
2381 { "l24", 0x5700, "vdd_l13_l19_l23_l24", },
2382 { "l25", 0x5800, "vdd_l25", },
2383 { "l26", 0x5900, "vdd_l2_l26_l28", },
2384 { "l27", 0x5a00, "vdd_l4_l27_l31", },
2385 { "l28", 0x5b00, "vdd_l2_l26_l28", },
2386 { "l29", 0x5c00, "vdd_l17_l29", },
2387 { "l30", 0x5d00, "vdd_l8_l16_l30", },
2388 { "l31", 0x5e00, "vdd_l4_l27_l31", },
2389 { "l32", 0x5f00, "vdd_l6_l12_l32", },
2390 { "lvs1", 0x8000, "vdd_lvs_1_2", },
2391 { "lvs2", 0x8100, "vdd_lvs_1_2", },
2396 { "s1", 0x1400, "vdd_s1", },
2397 { "s2", 0x1700, "vdd_s2", },
2398 { "s3", 0x1a00, "vdd_s3", },
2399 { "s4", 0x1d00, "vdd_s4", },
2400 { "s5", 0x2000, "vdd_s5", },
2401 { "s6", 0x2300, "vdd_s6", },
2402 { "s7", 0x2600, "vdd_s7", },
2403 { "s8", 0x2900, "vdd_s8", },
2404 { "s9", 0x2c00, "vdd_s9", },
2405 { "s10", 0x2f00, "vdd_s10", },
2406 { "s11", 0x3200, "vdd_s11", },
2407 { "s12", 0x3500, "vdd_s12", },
2408 { "l1", 0x4000, "vdd_l1_l11", },
2409 { "l2", 0x4100, "vdd_l2_l3_l4_l27", },
2410 { "l3", 0x4200, "vdd_l2_l3_l4_l27", },
2411 { "l4", 0x4300, "vdd_l2_l3_l4_l27", },
2412 { "l5", 0x4400, "vdd_l5_l7", },
2413 { "l6", 0x4500, "vdd_l6_l12_l14_l15_l26", },
2414 { "l7", 0x4600, "vdd_l5_l7", },
2415 { "l8", 0x4700, "vdd_l8", },
2416 { "l9", 0x4800, "vdd_l9_l10_l13_l20_l23_l24", },
2417 { "l10", 0x4900, "vdd_l9_l10_l13_l20_l23_l24", },
2418 { "l11", 0x4a00, "vdd_l1_l11", },
2419 { "l12", 0x4b00, "vdd_l6_l12_l14_l15_l26", },
2420 { "l13", 0x4c00, "vdd_l9_l10_l13_l20_l23_l24", },
2421 { "l14", 0x4d00, "vdd_l6_l12_l14_l15_l26", },
2422 { "l15", 0x4e00, "vdd_l6_l12_l14_l15_l26", },
2423 { "l16", 0x4f00, "vdd_l16_l25", },
2424 { "l17", 0x5000, "vdd_l17", },
2425 { "l18", 0x5100, "vdd_l18", },
2426 { "l19", 0x5200, "vdd_l19", },
2427 { "l20", 0x5300, "vdd_l9_l10_l13_l20_l23_l24", },
2428 { "l21", 0x5400, "vdd_l21", },
2429 { "l22", 0x5500, "vdd_l22", },
2430 { "l23", 0x5600, "vdd_l9_l10_l13_l20_l23_l24", },
2431 { "l24", 0x5700, "vdd_l9_l10_l13_l20_l23_l24", },
2432 { "l25", 0x5800, "vdd_l16_l25", },
2433 { "l26", 0x5900, "vdd_l6_l12_l14_l15_l26", },
2434 { "l27", 0x5a00, "vdd_l2_l3_l4_l27", },
2435 { "lvs1", 0x8000, "vdd_lvs1_2", },
2436 { "lvs2", 0x8100, "vdd_lvs1_2", },
2437 { "lvs3", 0x8200, "vdd_lvs3_4", },
2438 { "lvs4", 0x8300, "vdd_lvs3_4", },
2439 { "5vs1", 0x8400, "vdd_5vs1", },
2444 { "s1", 0x1400, "vdd_s1", },
2445 { "s2", 0x1700, "vdd_s2", },
2446 { "s3", 0x1a00, "vdd_s3", },
2447 { "l1", 0x4000, "vdd_l1", },
2452 { "s1", 0x1400, "vdd_s1"},
2453 { "s2", 0x1700, "vdd_s2"},
2454 { "s3", 0x1a00, "vdd_s3"},
2455 { "s4", 0x1d00, "vdd_s4"},
2456 { "s5", 0x2000, "vdd_s5"},
2457 { "l1", 0x4000, "vdd_l1_l2"},
2458 { "l2", 0x4100, "vdd_l1_l2"},
2459 { "l3", 0x4200, "vdd_l3_l8"},
2460 { "l4", 0x4300, "vdd_l4"},
2461 { "l5", 0x4400, "vdd_l5_l6_l15"},
2462 { "l6", 0x4500, "vdd_l5_l6_l15"},
2463 { "l7", 0x4600, "vdd_l7"},
2464 { "l8", 0x4700, "vdd_l3_l8"},
2465 { "l9", 0x4800, "vdd_l9"},
2467 { "l11", 0x4a00, "vdd_l10_l11_l12_l13"},
2468 { "l12", 0x4b00, "vdd_l10_l11_l12_l13"},
2469 { "l13", 0x4c00, "vdd_l10_l11_l12_l13"},
2474 { "s3", 0x1a00, "vdd_s3"},
2531 syscon = of_parse_phandle(node, "qcom,saw-reg", 0); in qcom_spmi_regulator_probe()
2559 if (vreg->ocp_irq < 0) in qcom_spmi_regulator_probe()
2608 return 0; in qcom_spmi_regulator_probe()