Lines Matching +full:0 +full:xe0
54 .enable_mask = BIT(0), \
103 REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
107 REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
111 REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
184 if (ret != 0) { in mt6397_regulator_set_mode()
190 return 0; in mt6397_regulator_set_mode()
199 if (ret != 0) { in mt6397_regulator_get_mode()
225 if (ret != 0) { in mt6397_get_status()
270 buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
273 buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
277 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5,
281 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5,
284 buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
287 MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
290 MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
293 buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
298 MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
302 MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
304 MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
306 MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
308 MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
310 MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
312 MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
314 MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
316 MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
318 MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
320 MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
329 for (i = 0; i < MT6397_MAX_REGULATOR; i++) { in mt6397_set_buck_vosel_reg()
333 ®val) < 0) { in mt6397_set_buck_vosel_reg()
346 return 0; in mt6397_set_buck_vosel_reg()
362 if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) { in mt6397_regulator_probe()
366 dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); in mt6397_regulator_probe()
368 version = (reg_value & 0xFF); in mt6397_regulator_probe()
378 for (i = 0; i < MT6397_MAX_REGULATOR; i++) { in mt6397_regulator_probe()
391 return 0; in mt6397_regulator_probe()
395 {"mt6397-regulator", 0},