Lines Matching full:vreg
121 * vreg - voltage select register
129 #define HI6421_LDO(_id, _match, v_table, vreg, vmask, ereg, emask, \ argument
142 .vsel_reg = HI6421_REG_TO_BUS_ADDR(vreg), \
160 * vreg - voltage select register
168 #define HI6421_LDO_LINEAR(_id, _match, _min_uV, n_volt, vstep, vreg, vmask,\ argument
182 .vsel_reg = HI6421_REG_TO_BUS_ADDR(vreg), \
200 * vreg - voltage select register
208 #define HI6421_LDO_LINEAR_RANGE(_id, _match, n_volt, volt_ranges, vreg, vmask,\ argument
222 .vsel_reg = HI6421_REG_TO_BUS_ADDR(vreg), \
237 * vreg - voltage select register
245 #define HI6421_BUCK012(_id, _match, vreg, vmask, ereg, emask, sleepmask,\ argument
259 .vsel_reg = HI6421_REG_TO_BUS_ADDR(vreg), \
275 * vreg - voltage select register
282 #define HI6421_BUCK345(_id, _match, v_table, vreg, vmask, ereg, emask, \ argument
295 .vsel_reg = HI6421_REG_TO_BUS_ADDR(vreg), \