26 	0x393, 0x293, 0x193, 0x093,
27 	0x392, 0x292, 0x192, 0x092,
28 	0x391, 0x291, 0x191, 0x091,
29 	0x390, 0x290, 0x190, 0x090,
30 	0x793, 0x693, 0x593, 0x493,
31 	0x792, 0x692, 0x592, 0x492,
32 	0x791, 0x691, 0x591, 0x491,
33 	0x790, 0x690, 0x590, 0x490,
42 	for (i = 0; i < ARRAY_SIZE(umc_coh_st_map); i++) {  in get_coh_st_inst_id_mi300()
55 	u16 tmp = 0;  in bitwise_xor_bits()
58 	for (i = 0; i < 16; i++)  in bitwise_xor_bits()
59 		tmp ^= (val >> i) & 0x1;  in bitwise_xor_bits()
96 #define MI300_UMC_CH_BASE	0x90000
97 #define MI300_ADDR_CFG		(MI300_UMC_CH_BASE + 0x30)
98 #define MI300_ADDR_SEL		(MI300_UMC_CH_BASE + 0x40)
99 #define MI300_COL_SEL_LO	(MI300_UMC_CH_BASE + 0x50)
100 #define MI300_ADDR_SEL_2	(MI300_UMC_CH_BASE + 0xA4)
101 #define MI300_ADDR_HASH_BANK0	(MI300_UMC_CH_BASE + 0xC8)
102 #define MI300_ADDR_HASH_PC	(MI300_UMC_CH_BASE + 0xE0)
103 #define MI300_ADDR_HASH_PC2	(MI300_UMC_CH_BASE + 0xE4)
105 #define ADDR_HASH_XOR_EN	BIT(0)
108 #define ADDR_HASH_BANK_XOR	GENMASK(5, 0)
113 #define ADDR_SEL_BANK0		GENMASK(3, 0)
121 #define COL_SEL_LO_COL0		GENMASK(3, 0)
127 #define ADDR_SEL_2_BANK5	GENMASK(4, 0)
142  * design of MI300 systems. So read the values from Node 0 UMC 0 and keep a
151 	for (i = 0; i < NUM_BANK_BITS; i++) {  in get_umc_info_mi300()
152 		ret = amd_smn_read(0, MI300_ADDR_HASH_BANK0 + (i * 4), &temp);  in get_umc_info_mi300()
161 	ret = amd_smn_read(0, MI300_ADDR_HASH_PC, &temp);  in get_umc_info_mi300()
169 	ret = amd_smn_read(0, MI300_ADDR_HASH_PC2, &temp);  in get_umc_info_mi300()
175 	ret = amd_smn_read(0, MI300_ADDR_CFG, &temp);  in get_umc_info_mi300()
182 	ret = amd_smn_read(0, MI300_ADDR_SEL, &temp);  in get_umc_info_mi300()
186 	bit_shifts.bank[0] = 5 + FIELD_GET(ADDR_SEL_BANK0, temp);  in get_umc_info_mi300()
191 	bit_shifts.sid[0]  = 5 + FIELD_GET(ADDR_SEL_BANK4, temp);  in get_umc_info_mi300()
195 	ret = amd_smn_read(0, MI300_COL_SEL_LO, &temp);  in get_umc_info_mi300()
199 	bit_shifts.col[0] = 2 + FIELD_GET(COL_SEL_LO_COL0, temp);  in get_umc_info_mi300()
205 	ret = amd_smn_read(0, MI300_ADDR_SEL_2, &temp);  in get_umc_info_mi300()
213 	return 0;  in get_umc_info_mi300()
227  *	MCA_ADDR[27:0] = {S[1:0], P[0], R[14:0], B[3:0], C[4:0], Z[0]}
250 	for (i = 0; i < NUM_BANK_BITS; i++) {  in convert_dram_to_norm_addr_mi300()
263 		/* Bits SID[1:0] act as Bank[5:4] for PC hash, so apply them here. */  in convert_dram_to_norm_addr_mi300()
268 	/* Reconstruct the normalized address starting with NA[4:0] = 0 */  in convert_dram_to_norm_addr_mi300()
269 	addr  = 0;  in convert_dram_to_norm_addr_mi300()
272 	for (i = 0; i < NUM_COL_BITS; i++) {  in convert_dram_to_norm_addr_mi300()
273 		temp  = (col >> i) & 0x1;  in convert_dram_to_norm_addr_mi300()
278 	for (i = 0; i < NUM_BANK_BITS; i++) {  in convert_dram_to_norm_addr_mi300()
279 		temp  = (bank >> i) & 0x1;  in convert_dram_to_norm_addr_mi300()
284 	for (i = 0; i < bit_shifts.num_row_lo; i++) {  in convert_dram_to_norm_addr_mi300()
285 		temp  = (row >> i) & 0x1;  in convert_dram_to_norm_addr_mi300()
290 	for (i = 0; i < bit_shifts.num_row_hi; i++) {  in convert_dram_to_norm_addr_mi300()
291 		temp  = (row >> (i + bit_shifts.num_row_lo)) & 0x1;  in convert_dram_to_norm_addr_mi300()
299 	for (i = 0; i < NUM_SID_BITS; i++) {  in convert_dram_to_norm_addr_mi300()
300 		temp  = (sid >> i) & 0x1;  in convert_dram_to_norm_addr_mi300()
304 	pr_debug("Addr=0x%016lx", addr);  in convert_dram_to_norm_addr_mi300()
329 	for (col = 0; col < MI300_NUM_COL; col++) {  in retire_row_mi300()
350 		memory_failure(addr, 0);  in retire_row_mi300()
406 	pr_debug("socket_id=0x%x die_id=0x%x coh_st_inst_id=0x%x addr=0x%016lx",  in convert_umc_mca_addr_to_sys_addr()