1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * drivers/pwm/pwm-tegra.c
5  * Tegra pulse-width-modulation controller driver
7  * Copyright (c) 2010-2020, NVIDIA Corporation.
8  * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11  * 1. 13-bit: Frequency division (SCALE)
12  * 2. 8-bit : Pulse division (DUTY)
13  * 3. 1-bit : Enable bit
18  * achieved is (max rate of source clock) / 256.
19  * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
24  * To achieve 100% duty cycle, program Bit [24] of this register to
28  * -	When PWM is disabled, the output is driven to inactive.
29  * -	It does not allow the current PWM period to complete and
32  * -	If the register is reconfigured while PWM is running,
35  * -	If the user input duty is beyond acceptible limits,
36  *	-EINVAL is returned.
86 	return readl(pc->regs + (offset << 4));  in pwm_readl()
91 	writel(value, pc->regs + (offset << 4));  in pwm_writel()
99 	unsigned long rate, required_clk_rate;  in tegra_pwm_config()  local
114 	 *  min period = max clock limit >> PWM_DUTY_WIDTH  in tegra_pwm_config()
116 	if (period_ns < pc->min_period_ns)  in tegra_pwm_config()
117 		return -EINVAL;  in tegra_pwm_config()
121 	 * cycles at the PWM clock rate will take period_ns nanoseconds.  in tegra_pwm_config()
129 	 * nums_channels == 1 then only the clock rate can be modified  in tegra_pwm_config()
132 	if (pc->soc->num_channels == 1) {  in tegra_pwm_config()
134 		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches  in tegra_pwm_config()
135 		 * with the maximum possible rate that the controller can  in tegra_pwm_config()
139 		 * required_clk_rate is a reference rate for source clock and  in tegra_pwm_config()
141 		 * source clock rate as required_clk_rate, PWM controller will  in tegra_pwm_config()
147 		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))  in tegra_pwm_config()
150 			 * rate; for lower rates there is no value for PWM_SCALE  in tegra_pwm_config()
153 			 * required_clk_rate to get a clock rate that can meet  in tegra_pwm_config()
160 			return -EINVAL;  in tegra_pwm_config()
162 		/* Store the new rate for further references */  in tegra_pwm_config()
163 		pc->clk_rate = clk_get_rate(pc->clk);  in tegra_pwm_config()
166 	/* Consider precision in PWM_SCALE_WIDTH rate calculation */  in tegra_pwm_config()
167 	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,  in tegra_pwm_config()
175 	if (rate > 0)  in tegra_pwm_config()
176 		rate--;  in tegra_pwm_config()
178 		return -EINVAL;  in tegra_pwm_config()
181 	 * Make sure that the rate will fit in the register's frequency  in tegra_pwm_config()
184 	if (rate >> PWM_SCALE_WIDTH)  in tegra_pwm_config()
185 		return -EINVAL;  in tegra_pwm_config()
187 	val |= rate << PWM_SCALE_SHIFT;  in tegra_pwm_config()
200 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_config()
221 	val = pwm_readl(pc, pwm->hwpwm);  in tegra_pwm_enable()
223 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_enable()
233 	val = pwm_readl(pc, pwm->hwpwm);  in tegra_pwm_disable()
235 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_disable()
244 	bool enabled = pwm->state.enabled;  in tegra_pwm_apply()
246 	if (state->polarity != PWM_POLARITY_NORMAL)  in tegra_pwm_apply()
247 		return -EINVAL;  in tegra_pwm_apply()
249 	if (!state->enabled) {  in tegra_pwm_apply()
256 	err = tegra_pwm_config(chip, pwm, state->duty_cycle, state->period);  in tegra_pwm_apply()
277 	soc = of_device_get_match_data(&pdev->dev);  in tegra_pwm_probe()
279 	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc));  in tegra_pwm_probe()
284 	pc->soc = soc;  in tegra_pwm_probe()
286 	pc->regs = devm_platform_ioremap_resource(pdev, 0);  in tegra_pwm_probe()
287 	if (IS_ERR(pc->regs))  in tegra_pwm_probe()
288 		return PTR_ERR(pc->regs);  in tegra_pwm_probe()
292 	pc->clk = devm_clk_get(&pdev->dev, NULL);  in tegra_pwm_probe()
293 	if (IS_ERR(pc->clk))  in tegra_pwm_probe()
294 		return PTR_ERR(pc->clk);  in tegra_pwm_probe()
296 	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);  in tegra_pwm_probe()
300 	pm_runtime_enable(&pdev->dev);  in tegra_pwm_probe()
301 	ret = pm_runtime_resume_and_get(&pdev->dev);  in tegra_pwm_probe()
306 	ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);  in tegra_pwm_probe()
308 		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);  in tegra_pwm_probe()
317 	pc->clk_rate = clk_get_rate(pc->clk);  in tegra_pwm_probe()
320 	pc->min_period_ns =  in tegra_pwm_probe()
321 	    (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;  in tegra_pwm_probe()
323 	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");  in tegra_pwm_probe()
324 	if (IS_ERR(pc->rst)) {  in tegra_pwm_probe()
325 		ret = PTR_ERR(pc->rst);  in tegra_pwm_probe()
326 		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);  in tegra_pwm_probe()
330 	reset_control_deassert(pc->rst);  in tegra_pwm_probe()
332 	chip->ops = &tegra_pwm_ops;  in tegra_pwm_probe()
336 		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);  in tegra_pwm_probe()
337 		reset_control_assert(pc->rst);  in tegra_pwm_probe()
341 	pm_runtime_put(&pdev->dev);  in tegra_pwm_probe()
345 	pm_runtime_put_sync_suspend(&pdev->dev);  in tegra_pwm_probe()
346 	pm_runtime_force_suspend(&pdev->dev);  in tegra_pwm_probe()
357 	reset_control_assert(pc->rst);  in tegra_pwm_remove()
359 	pm_runtime_force_suspend(&pdev->dev);  in tegra_pwm_remove()
368 	clk_disable_unprepare(pc->clk);  in tegra_pwm_runtime_suspend()
372 		clk_prepare_enable(pc->clk);  in tegra_pwm_runtime_suspend()
389 	err = clk_prepare_enable(pc->clk);  in tegra_pwm_runtime_resume()
414 	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
415 	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
416 	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
430 		.name = "tegra-pwm",
443 MODULE_ALIAS("platform:tegra-pwm");