1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8  * - When outputing the source clock directly, the PWM logic will be bypassed
47 #define PWM_PRD(prd)		(((prd) - 1) << 16)
100 	return readl(sun4ichip->base + offset);  in sun4i_pwm_readl()
106 	writel(val, sun4ichip->base + offset);  in sun4i_pwm_writel()
118 	clk_rate = clk_get_rate(sun4ichip->clk);  in sun4i_pwm_get_state()
120 		return -EINVAL;  in sun4i_pwm_get_state()
129 	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&  in sun4i_pwm_get_state()
130 	    sun4ichip->data->has_direct_mod_clk_output) {  in sun4i_pwm_get_state()
131 		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);  in sun4i_pwm_get_state()
132 		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);  in sun4i_pwm_get_state()
133 		state->polarity = PWM_POLARITY_NORMAL;  in sun4i_pwm_get_state()
134 		state->enabled = true;  in sun4i_pwm_get_state()
138 	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&  in sun4i_pwm_get_state()
139 	    sun4ichip->data->has_prescaler_bypass)  in sun4i_pwm_get_state()
142 		prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];  in sun4i_pwm_get_state()
145 		return -EINVAL;  in sun4i_pwm_get_state()
147 	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))  in sun4i_pwm_get_state()
148 		state->polarity = PWM_POLARITY_NORMAL;  in sun4i_pwm_get_state()
150 		state->polarity = PWM_POLARITY_INVERSED;  in sun4i_pwm_get_state()
152 	if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==  in sun4i_pwm_get_state()
153 	    BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))  in sun4i_pwm_get_state()
154 		state->enabled = true;  in sun4i_pwm_get_state()
156 		state->enabled = false;  in sun4i_pwm_get_state()
158 	val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm));  in sun4i_pwm_get_state()
161 	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);  in sun4i_pwm_get_state()
164 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);  in sun4i_pwm_get_state()
177 	clk_rate = clk_get_rate(sun4ichip->clk);  in sun4i_pwm_calculate()
179 	*bypass = sun4ichip->data->has_direct_mod_clk_output &&  in sun4i_pwm_calculate()
180 		  state->enabled &&  in sun4i_pwm_calculate()
181 		  (state->period * clk_rate >= NSEC_PER_SEC) &&  in sun4i_pwm_calculate()
182 		  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&  in sun4i_pwm_calculate()
183 		  (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);  in sun4i_pwm_calculate()
185 	/* Skip calculation of other parameters if we bypass them */  in sun4i_pwm_calculate()
189 	if (sun4ichip->data->has_prescaler_bypass) {  in sun4i_pwm_calculate()
193 		 * When not using any prescaler, the clock period in nanoseconds  in sun4i_pwm_calculate()
197 		div = clk_rate * state->period + NSEC_PER_SEC / 2;  in sun4i_pwm_calculate()
199 		if (div - 1 > PWM_PRD_MASK)  in sun4i_pwm_calculate()
213 			div = div * state->period;  in sun4i_pwm_calculate()
215 			if (div - 1 <= PWM_PRD_MASK)  in sun4i_pwm_calculate()
219 		if (div - 1 > PWM_PRD_MASK)  in sun4i_pwm_calculate()
220 			return -EINVAL;  in sun4i_pwm_calculate()
224 	div *= state->duty_cycle;  in sun4i_pwm_calculate()
225 	do_div(div, state->period);  in sun4i_pwm_calculate()
245 		ret = clk_prepare_enable(sun4ichip->clk);  in sun4i_pwm_apply()
247 			dev_err(pwmchip_parent(chip), "failed to enable PWM clock\n");  in sun4i_pwm_apply()
257 			clk_disable_unprepare(sun4ichip->clk);  in sun4i_pwm_apply()
261 	spin_lock(&sun4ichip->ctrl_lock);  in sun4i_pwm_apply()
264 	if (sun4ichip->data->has_direct_mod_clk_output) {  in sun4i_pwm_apply()
266 			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);  in sun4i_pwm_apply()
267 			/* We can skip other parameter */  in sun4i_pwm_apply()
269 			spin_unlock(&sun4ichip->ctrl_lock);  in sun4i_pwm_apply()
273 		ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);  in sun4i_pwm_apply()
276 	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {  in sun4i_pwm_apply()
277 		/* Prescaler changed, the clock has to be gated */  in sun4i_pwm_apply()
278 		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);  in sun4i_pwm_apply()
281 		ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);  in sun4i_pwm_apply()
282 		ctrl |= BIT_CH(prescaler, pwm->hwpwm);  in sun4i_pwm_apply()
286 	sun4i_pwm_writel(sun4ichip, val, PWM_CH_PRD(pwm->hwpwm));  in sun4i_pwm_apply()
288 	if (state->polarity != PWM_POLARITY_NORMAL)  in sun4i_pwm_apply()
289 		ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);  in sun4i_pwm_apply()
291 		ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);  in sun4i_pwm_apply()
293 	ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);  in sun4i_pwm_apply()
295 	if (state->enabled)  in sun4i_pwm_apply()
296 		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);  in sun4i_pwm_apply()
300 	spin_unlock(&sun4ichip->ctrl_lock);  in sun4i_pwm_apply()
302 	if (state->enabled)  in sun4i_pwm_apply()
312 	spin_lock(&sun4ichip->ctrl_lock);  in sun4i_pwm_apply()
314 	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);  in sun4i_pwm_apply()
315 	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);  in sun4i_pwm_apply()
317 	spin_unlock(&sun4ichip->ctrl_lock);  in sun4i_pwm_apply()
319 	clk_disable_unprepare(sun4ichip->clk);  in sun4i_pwm_apply()
358 		.compatible = "allwinner,sun4i-a10-pwm",
361 		.compatible = "allwinner,sun5i-a10s-pwm",
364 		.compatible = "allwinner,sun5i-a13-pwm",
367 		.compatible = "allwinner,sun7i-a20-pwm",
370 		.compatible = "allwinner,sun8i-h3-pwm",
373 		.compatible = "allwinner,sun50i-a64-pwm",
376 		.compatible = "allwinner,sun50i-h6-pwm",
391 	data = of_device_get_match_data(&pdev->dev);  in sun4i_pwm_probe()
393 		return -ENODEV;  in sun4i_pwm_probe()
395 	chip = devm_pwmchip_alloc(&pdev->dev, data->npwm, sizeof(*sun4ichip));  in sun4i_pwm_probe()
400 	sun4ichip->data = data;  in sun4i_pwm_probe()
401 	sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);  in sun4i_pwm_probe()
402 	if (IS_ERR(sun4ichip->base))  in sun4i_pwm_probe()
403 		return PTR_ERR(sun4ichip->base);  in sun4i_pwm_probe()
406 	 * All hardware variants need a source clock that is divided and  in sun4i_pwm_probe()
408 	 * device tree this clock is either unnamed or called "mod".  in sun4i_pwm_probe()
409 	 * Some variants (e.g. H6) need another clock to access the  in sun4i_pwm_probe()
412 	 * parent provides a "mod" clock while the right one would be the  in sun4i_pwm_probe()
414 	 * back to the first clock of the PWM.  in sun4i_pwm_probe()
416 	sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");  in sun4i_pwm_probe()
417 	if (IS_ERR(sun4ichip->clk))  in sun4i_pwm_probe()
418 		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),  in sun4i_pwm_probe()
419 				     "get mod clock failed\n");  in sun4i_pwm_probe()
421 	if (!sun4ichip->clk) {  in sun4i_pwm_probe()
422 		sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);  in sun4i_pwm_probe()
423 		if (IS_ERR(sun4ichip->clk))  in sun4i_pwm_probe()
424 			return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),  in sun4i_pwm_probe()
425 					     "get unnamed clock failed\n");  in sun4i_pwm_probe()
428 	sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");  in sun4i_pwm_probe()
429 	if (IS_ERR(sun4ichip->bus_clk))  in sun4i_pwm_probe()
430 		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),  in sun4i_pwm_probe()
431 				     "get bus clock failed\n");  in sun4i_pwm_probe()
433 	sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);  in sun4i_pwm_probe()
434 	if (IS_ERR(sun4ichip->rst))  in sun4i_pwm_probe()
435 		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),  in sun4i_pwm_probe()
439 	ret = reset_control_deassert(sun4ichip->rst);  in sun4i_pwm_probe()
441 		dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",  in sun4i_pwm_probe()
447 	 * We're keeping the bus clock on for the sake of simplicity.  in sun4i_pwm_probe()
450 	ret = clk_prepare_enable(sun4ichip->bus_clk);  in sun4i_pwm_probe()
452 		dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",  in sun4i_pwm_probe()
457 	chip->ops = &sun4i_pwm_ops;  in sun4i_pwm_probe()
459 	spin_lock_init(&sun4ichip->ctrl_lock);  in sun4i_pwm_probe()
463 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);  in sun4i_pwm_probe()
472 	clk_disable_unprepare(sun4ichip->bus_clk);  in sun4i_pwm_probe()
474 	reset_control_assert(sun4ichip->rst);  in sun4i_pwm_probe()
486 	clk_disable_unprepare(sun4ichip->bus_clk);  in sun4i_pwm_remove()
487 	reset_control_assert(sun4ichip->rst);  in sun4i_pwm_remove()
492 		.name = "sun4i-pwm",
500 MODULE_ALIAS("platform:sun4i-pwm");
501 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");