49 	regmap_read(dev->regmap, TIM_CCER, &ccer);  in active_channels()
110 	regmap_set_bits(priv->regmap, TIM_CCER, ccen);  in stm32_pwm_raw_capture()
148 	regmap_clear_bits(priv->regmap, TIM_CCER, ccen);  in stm32_pwm_raw_capture()
207 	regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?  in stm32_pwm_capture()
300 	regmap_write(priv->regmap, TIM_CCER, 0);  in stm32_pwm_capture()
397 	regmap_update_bits(priv->regmap, TIM_CCER, mask,  in stm32_pwm_set_polarity()
417 	regmap_set_bits(priv->regmap, TIM_CCER, mask);  in stm32_pwm_enable()
437 	regmap_clear_bits(priv->regmap, TIM_CCER, mask);  in stm32_pwm_disable()
501 	ret = regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_pwm_get_state()
616 	regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);  in stm32_pwm_detect_complementary()
617 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_pwm_detect_complementary()
618 	regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);  in stm32_pwm_detect_complementary()
632 	regmap_read(regmap, TIM_CCER, &ccer_backup);  in stm32_pwm_detect_channels()
633 	regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE);  in stm32_pwm_detect_channels()
634 	regmap_read(regmap, TIM_CCER, &ccer);  in stm32_pwm_detect_channels()
635 	regmap_write(regmap, TIM_CCER, ccer_backup);  in stm32_pwm_detect_channels()