Lines Matching +full:capture +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
12 #include <linux/mfd/stm32-timers.h>
37 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ member
49 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels()
68 unsigned int ch = pwm->hwpwm; in stm32_pwm_round_waveform_tohw()
73 if (wf->period_length_ns == 0) { in stm32_pwm_round_waveform_tohw()
81 ret = clk_enable(priv->clk); in stm32_pwm_round_waveform_tohw()
85 wfhw->ccer = TIM_CCER_CCxE(ch + 1); in stm32_pwm_round_waveform_tohw()
86 if (priv->have_complementary_output) in stm32_pwm_round_waveform_tohw()
87 wfhw->ccer |= TIM_CCER_CCxNE(ch + 1); in stm32_pwm_round_waveform_tohw()
89 rate = clk_get_rate(priv->clk); in stm32_pwm_round_waveform_tohw()
95 * Other channels are already enabled, so the configured PSC and in stm32_pwm_round_waveform_tohw()
98 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc); in stm32_pwm_round_waveform_tohw()
102 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr); in stm32_pwm_round_waveform_tohw()
110 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate, in stm32_pwm_round_waveform_tohw()
111 (u64)NSEC_PER_SEC * (wfhw->psc + 1)); in stm32_pwm_round_waveform_tohw()
112 if (arr <= wfhw->arr) { in stm32_pwm_round_waveform_tohw()
119 wfhw->ccr = 0; in stm32_pwm_round_waveform_tohw()
131 * ------------------------------ < max_arr + 1 in stm32_pwm_round_waveform_tohw()
137 * ---------------------------- < prescaler + 1 in stm32_pwm_round_waveform_tohw()
145 u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate, in stm32_pwm_round_waveform_tohw()
146 (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1)); in stm32_pwm_round_waveform_tohw()
149 wfhw->psc = min_t(u64, psc, MAX_TIM_PSC); in stm32_pwm_round_waveform_tohw()
151 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate, in stm32_pwm_round_waveform_tohw()
152 (u64)NSEC_PER_SEC * (wfhw->psc + 1)); in stm32_pwm_round_waveform_tohw()
159 wfhw->arr = 0; in stm32_pwm_round_waveform_tohw()
160 wfhw->ccr = 0; in stm32_pwm_round_waveform_tohw()
167 * priv->max_arr to allow 100% duty cycle. in stm32_pwm_round_waveform_tohw()
169 wfhw->arr = min_t(u64, arr, priv->max_arr) - 1; in stm32_pwm_round_waveform_tohw()
172 duty = mul_u64_u64_div_u64(wf->duty_length_ns, rate, in stm32_pwm_round_waveform_tohw()
173 (u64)NSEC_PER_SEC * (wfhw->psc + 1)); in stm32_pwm_round_waveform_tohw()
174 duty = min_t(u64, duty, wfhw->arr + 1); in stm32_pwm_round_waveform_tohw()
176 if (wf->duty_length_ns && wf->duty_offset_ns && in stm32_pwm_round_waveform_tohw()
177 wf->duty_length_ns + wf->duty_offset_ns >= wf->period_length_ns) { in stm32_pwm_round_waveform_tohw()
178 wfhw->ccer |= TIM_CCER_CCxP(ch + 1); in stm32_pwm_round_waveform_tohw()
179 if (priv->have_complementary_output) in stm32_pwm_round_waveform_tohw()
180 wfhw->ccer |= TIM_CCER_CCxNP(ch + 1); in stm32_pwm_round_waveform_tohw()
182 ccr = wfhw->arr + 1 - duty; in stm32_pwm_round_waveform_tohw()
187 wfhw->ccr = min_t(u64, ccr, wfhw->arr + 1); in stm32_pwm_round_waveform_tohw()
189 …dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x… in stm32_pwm_round_waveform_tohw()
190 pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns, in stm32_pwm_round_waveform_tohw()
191 rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr); in stm32_pwm_round_waveform_tohw()
194 clk_disable(priv->clk); in stm32_pwm_round_waveform_tohw()
207 u64 rem = a * b - c * res; in stm32_pwm_mul_u64_u64_div_u64_roundup()
222 unsigned int ch = pwm->hwpwm; in stm32_pwm_round_waveform_fromhw()
224 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { in stm32_pwm_round_waveform_fromhw()
225 unsigned long rate = clk_get_rate(priv->clk); in stm32_pwm_round_waveform_fromhw()
229 …wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1… in stm32_pwm_round_waveform_fromhw()
232 ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr, in stm32_pwm_round_waveform_fromhw()
235 if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) { in stm32_pwm_round_waveform_fromhw()
236 wf->duty_length_ns = in stm32_pwm_round_waveform_fromhw()
237 stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr), in stm32_pwm_round_waveform_fromhw()
240 wf->duty_offset_ns = ccr_ns; in stm32_pwm_round_waveform_fromhw()
242 wf->duty_length_ns = ccr_ns; in stm32_pwm_round_waveform_fromhw()
243 wf->duty_offset_ns = 0; in stm32_pwm_round_waveform_fromhw()
246 …dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]… in stm32_pwm_round_waveform_fromhw()
247 pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate, in stm32_pwm_round_waveform_fromhw()
248 wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns); in stm32_pwm_round_waveform_fromhw()
265 unsigned int ch = pwm->hwpwm; in stm32_pwm_read_waveform()
268 ret = clk_enable(priv->clk); in stm32_pwm_read_waveform()
272 ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer); in stm32_pwm_read_waveform()
276 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { in stm32_pwm_read_waveform()
277 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc); in stm32_pwm_read_waveform()
281 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr); in stm32_pwm_read_waveform()
285 if (wfhw->arr == U32_MAX) in stm32_pwm_read_waveform()
286 wfhw->arr -= 1; in stm32_pwm_read_waveform()
288 ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr); in stm32_pwm_read_waveform()
292 if (wfhw->ccr > wfhw->arr + 1) in stm32_pwm_read_waveform()
293 wfhw->ccr = wfhw->arr + 1; in stm32_pwm_read_waveform()
297 clk_disable(priv->clk); in stm32_pwm_read_waveform()
308 unsigned int ch = pwm->hwpwm; in stm32_pwm_write_waveform()
311 ret = clk_enable(priv->clk); in stm32_pwm_write_waveform()
315 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { in stm32_pwm_write_waveform()
320 ret = regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_write_waveform()
324 /* If there are other channels enabled, don't update PSC and ARR */ in stm32_pwm_write_waveform()
328 ret = regmap_read(priv->regmap, TIM_PSC, &psc); in stm32_pwm_write_waveform()
332 if (psc != wfhw->psc) { in stm32_pwm_write_waveform()
333 ret = -EBUSY; in stm32_pwm_write_waveform()
337 ret = regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_pwm_write_waveform()
341 if (arr != wfhw->arr) { in stm32_pwm_write_waveform()
342 ret = -EBUSY; in stm32_pwm_write_waveform()
346 ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc); in stm32_pwm_write_waveform()
350 ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr); in stm32_pwm_write_waveform()
354 ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); in stm32_pwm_write_waveform()
362 ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer); in stm32_pwm_write_waveform()
366 ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr); in stm32_pwm_write_waveform()
376 ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); in stm32_pwm_write_waveform()
378 ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); in stm32_pwm_write_waveform()
382 ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); in stm32_pwm_write_waveform()
389 ret = clk_enable(priv->clk); in stm32_pwm_write_waveform()
393 ccer = (ccer & ~mask) | (wfhw->ccer & mask); in stm32_pwm_write_waveform()
394 regmap_write(priv->regmap, TIM_CCER, ccer); in stm32_pwm_write_waveform()
397 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_pwm_write_waveform()
400 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_write_waveform()
408 if (priv->have_complementary_output) in stm32_pwm_write_waveform()
411 ret = regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_write_waveform()
418 ret = regmap_write(priv->regmap, TIM_CCER, ccer); in stm32_pwm_write_waveform()
423 /* When all channels are disabled, we can disable the controller */ in stm32_pwm_write_waveform()
424 ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_write_waveform()
429 clk_disable(priv->clk); in stm32_pwm_write_waveform()
434 clk_disable(priv->clk); in stm32_pwm_write_waveform()
445 * Capture using PWM input mode:
467 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
469 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
470 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
474 * - Period = t2 - t0
475 * - Duty cycle = t1 - t0
482 struct device *parent = pwmchip_parent(chip)->parent; in stm32_pwm_raw_capture()
487 /* Ensure registers have been updated, enable counter and capture */ in stm32_pwm_raw_capture()
488 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_pwm_raw_capture()
489 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_raw_capture()
491 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ in stm32_pwm_raw_capture()
492 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; in stm32_pwm_raw_capture()
493 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; in stm32_pwm_raw_capture()
494 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; in stm32_pwm_raw_capture()
495 regmap_set_bits(priv->regmap, TIM_CCER, ccen); in stm32_pwm_raw_capture()
499 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. in stm32_pwm_raw_capture()
500 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } in stm32_pwm_raw_capture()
503 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, in stm32_pwm_raw_capture()
508 /* Period: t2 - t0 (take care of counter overflow) */ in stm32_pwm_raw_capture()
509 if (priv->capture[0] <= priv->capture[2]) in stm32_pwm_raw_capture()
510 *raw_prd = priv->capture[2] - priv->capture[0]; in stm32_pwm_raw_capture()
512 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; in stm32_pwm_raw_capture()
514 /* Duty cycle capture requires at least two capture units */ in stm32_pwm_raw_capture()
515 if (pwm->chip->npwm < 2) in stm32_pwm_raw_capture()
517 else if (priv->capture[0] <= priv->capture[3]) in stm32_pwm_raw_capture()
518 *raw_dty = priv->capture[3] - priv->capture[0]; in stm32_pwm_raw_capture()
520 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; in stm32_pwm_raw_capture()
525 * falling edge triggers new capture on TI2/4 before DMA in stm32_pwm_raw_capture()
526 * had a chance to read CCR2/4. It means capture[1] in stm32_pwm_raw_capture()
529 *raw_dty -= *raw_prd; in stm32_pwm_raw_capture()
533 regmap_clear_bits(priv->regmap, TIM_CCER, ccen); in stm32_pwm_raw_capture()
534 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_raw_capture()
549 mutex_lock(&priv->lock); in stm32_pwm_capture()
552 ret = -EBUSY; in stm32_pwm_capture()
556 ret = clk_enable(priv->clk); in stm32_pwm_capture()
562 rate = clk_get_rate(priv->clk); in stm32_pwm_capture()
564 ret = -EINVAL; in stm32_pwm_capture()
572 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { in stm32_pwm_capture()
577 regmap_write(priv->regmap, TIM_ARR, priv->max_arr); in stm32_pwm_capture()
578 regmap_write(priv->regmap, TIM_PSC, psc); in stm32_pwm_capture()
581 regmap_write(priv->regmap, TIM_TISEL, 0x0); in stm32_pwm_capture()
582 regmap_write(priv->regmap, TIM_SMCR, 0x0); in stm32_pwm_capture()
585 regmap_update_bits(priv->regmap, in stm32_pwm_capture()
586 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
587 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? in stm32_pwm_capture()
591 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ in stm32_pwm_capture()
592 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? in stm32_pwm_capture()
593 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? in stm32_pwm_capture()
601 * Got a capture. Try to improve accuracy at high rates: in stm32_pwm_capture()
602 * - decrease counter clock prescaler, scale up to max rate. in stm32_pwm_capture()
603 * - use input prescaler, capture once every /2 /4 or /8 edges. in stm32_pwm_capture()
606 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ in stm32_pwm_capture()
610 scale = priv->max_arr; /* below resolution, use max scale */ in stm32_pwm_capture()
616 regmap_write(priv->regmap, TIM_PSC, psc); in stm32_pwm_capture()
629 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) in stm32_pwm_capture()
639 regmap_update_bits(priv->regmap, in stm32_pwm_capture()
640 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
652 * capture starts on high side (before falling edge). in stm32_pwm_capture()
653 * Example with icpsc to capture on each 4 events: in stm32_pwm_capture()
655 * start 1st capture 2nd capture in stm32_pwm_capture()
666 * Capture0: .<----------------------------->. in stm32_pwm_capture()
667 * Capture1: .<-------------------------->. . in stm32_pwm_capture()
669 * Period: .<------> . . in stm32_pwm_capture()
673 * - Period = Capture0 / icpsc in stm32_pwm_capture()
674 * - Duty = Period - Low side = Period - (Capture0 - Capture1) in stm32_pwm_capture()
676 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); in stm32_pwm_capture()
681 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); in stm32_pwm_capture()
683 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); in stm32_pwm_capture()
685 regmap_write(priv->regmap, TIM_CCER, 0); in stm32_pwm_capture()
686 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); in stm32_pwm_capture()
687 regmap_write(priv->regmap, TIM_PSC, 0); in stm32_pwm_capture()
689 clk_disable(priv->clk); in stm32_pwm_capture()
691 mutex_unlock(&priv->lock); in stm32_pwm_capture()
703 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
709 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); in stm32_pwm_set_breakinput()
710 u32 bke = TIM_BDTR_BKE(bi->index); in stm32_pwm_set_breakinput()
711 u32 bkp = TIM_BDTR_BKP(bi->index); in stm32_pwm_set_breakinput()
712 u32 bkf = TIM_BDTR_BKF(bi->index); in stm32_pwm_set_breakinput()
716 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; in stm32_pwm_set_breakinput()
718 if (bi->level) in stm32_pwm_set_breakinput()
721 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); in stm32_pwm_set_breakinput()
723 regmap_read(priv->regmap, TIM_BDTR, &bdtr); in stm32_pwm_set_breakinput()
725 return (bdtr & bke) ? 0 : -EINVAL; in stm32_pwm_set_breakinput()
733 for (i = 0; i < priv->num_breakinputs; i++) { in stm32_pwm_apply_breakinputs()
734 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); in stm32_pwm_apply_breakinputs()
759 return -EINVAL; in stm32_pwm_probe_breakinputs()
761 priv->num_breakinputs = nb; in stm32_pwm_probe_breakinputs()
764 (u32 *)priv->breakinputs, array_size); in stm32_pwm_probe_breakinputs()
768 for (i = 0; i < priv->num_breakinputs; i++) { in stm32_pwm_probe_breakinputs()
769 if (priv->breakinputs[i].index > 1 || in stm32_pwm_probe_breakinputs()
770 priv->breakinputs[i].level > 1 || in stm32_pwm_probe_breakinputs()
771 priv->breakinputs[i].filter > 15) in stm32_pwm_probe_breakinputs()
772 return -EINVAL; in stm32_pwm_probe_breakinputs()
786 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); in stm32_pwm_detect_complementary()
787 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_detect_complementary()
788 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); in stm32_pwm_detect_complementary()
790 priv->have_complementary_output = (ccer != 0); in stm32_pwm_detect_complementary()
799 * If channels enable bits don't exist writing 1 will have no in stm32_pwm_detect_channels()
814 struct device *dev = &pdev->dev; in stm32_pwm_probe()
815 struct device_node *np = dev->of_node; in stm32_pwm_probe()
816 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); in stm32_pwm_probe()
823 npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled); in stm32_pwm_probe()
830 mutex_init(&priv->lock); in stm32_pwm_probe()
831 priv->regmap = ddata->regmap; in stm32_pwm_probe()
832 priv->clk = ddata->clk; in stm32_pwm_probe()
833 priv->max_arr = ddata->max_arr; in stm32_pwm_probe()
835 if (!priv->regmap || !priv->clk) in stm32_pwm_probe()
836 return dev_err_probe(dev, -EINVAL, "Failed to get %s\n", in stm32_pwm_probe()
837 priv->regmap ? "clk" : "regmap"); in stm32_pwm_probe()
846 ret = devm_clk_rate_exclusive_get(dev, priv->clk); in stm32_pwm_probe()
854 if (clk_get_rate(priv->clk) > 1000000000) in stm32_pwm_probe()
855 return dev_err_probe(dev, -EINVAL, "Clock freq too high (%lu)\n", in stm32_pwm_probe()
856 clk_get_rate(priv->clk)); in stm32_pwm_probe()
858 chip->ops = &stm32pwm_ops; in stm32_pwm_probe()
860 /* Initialize clock refcount to number of enabled PWM channels. */ in stm32_pwm_probe()
862 clk_enable(priv->clk); in stm32_pwm_probe()
881 /* Look for active channels */ in stm32_pwm_suspend()
884 for (i = 0; i < chip->npwm; i++) { in stm32_pwm_suspend()
888 i, chip->pwms[i].label); in stm32_pwm_suspend()
889 return -EBUSY; in stm32_pwm_suspend()
913 { .compatible = "st,stm32-pwm", },
921 .name = "stm32-pwm",
928 MODULE_ALIAS("platform:stm32-pwm");